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I C Controller - The Lab Book Pages

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Dr. Andrew Greensted Last modified: 8th July 2010 Hide Menu

I C Controller
The I C standard is used in a wide variety of electronic components. Everything from microcontrollers to digital compasses make use of the standard for inter-device communication. The VHDL modules described here can be used to master an I C bus. The Simple Master Module provides a simple method of interfacing a microcontroller to a I C bus, whereas the Controller Module is programmable and allows complex sequences of basic I C communication operations to be offloaded from the main host processor. System Overview The Simple Master Module The Controller Module

S stem Overview
The Simple Master Module performs the basic I C operations: S A T S O , R S A T W I E R A A Kand R A N C . This module can be TR, TP ETR, RT, ED C ED AK used on its own and can easily be interfaced to a microcontroller, see (a) in figure below. The second module is a basic controller that can be programmed to perform whole sequences of I C communication operations. The idea is to offload the task of low-level bus control from the host processor, see (b) in the figure below. For example, the controller could be programmed to periodically read values from a thermometer, compass and accelerometer without any other control required from the host processor, which then only has to read off the sensor data values once collected.

The I C Controller Module makes it possible to offload a lot of low level I C operations from the host processor

If you have a very complex I C slave peripheral, then direct control available with the Simple Master Module is probably best way to go. However, for most other tasks, you can free up valuable microprocessor cycles by making use of the Controller Module. The VHDL for the modules is linked to below. I C VHDL Modules

The Simple Master Module

The Simple Master performs the basic I C Master operations, these are shown in the figure below. Full communication with a peripheral is achieved by chaining together a set of these basic operations. Internal to the Simple Master Module, each operation is split into groups of 4 stages (labelled A to D).

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I C Controller - The Lab Book Pages

I C operations are constructed from groups of 4 stages

The

f he VHDL

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The e i ed e a i i a ied he o e a i ni prto ,a e a da a d t M t 2 u if he e a i i a I C W I E D T . aasrBs 2_RT_AA The e a i i a ed b a i g e ab e. Whe he e a i i c e e he d n ig a i g high (i e ai high oe i he e e ab e e). If he e a i a a I C W I E D T , he ac 2_RT_AA edge e e f he a e i a ai ab e s a e c . If he e a i lvAk a a I C R A _ A A A K I C R A _ A A N C he ead da a i a ai ab e 2_EDDT_C 2_EDDT_AK dtBsMt. aau2sr
File E cerpt: I C i p e a t r h l 2SmlMse. d ett ICipeatri ni 2SmlMse s gnrc TC_U eei( IKNM pr ( ck ot l rst ee slu cOt san dI sau dOt eal nbe oeain prto dn oe dtMt2u aasrBs dtBsMt aau2sr saec lvAk edICipeatr n 2SmlMse; :itgr; nee) :i sdlgc n t_oi; :i sdlgc n t_oi; :otsdlgc u t_oi; :i sdlgc n t_oi; :otsdlgc u t_oi; :i sdlgc n t_oi; :i ICMSE_P n 2_ATRO; :otsdlgc u t_oi; :i sdlgcvco( dwt 0; n t_oi_etr7 ono ) :otsdlgcvco( dwt 0; u t_oi_etr7 ono ) :otsdlgc; u t_oi)

- Sata oeain - tr n prto - Oeainrqie - prto eurd - IdctsMse i dn (o bs) - niae atr s oe nt uy - Dt fo Mse t ICBs - aa rm atr o u - Dt fo ICBs(lv)t Mse - aa rm u sae o atr - Akoldelvlfo sae(nwie - cnweg ee rm lv o rt)

The I C M S E _ P e i dec a ed i I C k . h l The a id a e a e h 2_ATRO 2Pgvd. i he e ce a a ai ab e f c e i g a s d l g c v c o i t_oi_etr a I C M S E _ P ha d if i e faci g 2_ATRO,

File E cerpt: I C k . h l 2Pg d tp ICMSE_Pi (ICSAT e 2_ATRO s 2_TR, ICRSAT 2_ETR, ICSO, 2_TP ICWIEDT, 2_RT_AA ICRA_AAAK 2_EDDT_C, ICRA_AANC) 2_EDDT_AK;

be . A f a ic c

ci

ca ed t _ 2 _ A T R O i oICMSE_P e da a b .

fnto t_2_ATRO(vle:sdlgcvco( dwt 0 )rtr ICMSE_Pi ucin oICMSE_P au t_oi_etr2 ono ) eun 2_ATRO s vral rsl :ICMSE_P aibe eut 2_ATRO; bgn ei cs vlei ae au s we b00 = rsl : ICSAT hn "0" > eut = 2_TR; - 0 we b01 = rsl : ICRSAT hn "0" > eut = 2_ETR; - 1 we b00 = rsl : ICSO; hn "1" > eut = 2_TP - 2 we b01 = rsl : ICWIEDT; hn "1" > eut = 2_RT_AA - 3 we b10 = rsl : ICRA_AAAK hn "0" > eut = 2_EDDT_C; - 4 we ohr = rsl : ICRA_AANC; hn tes > eut = 2_EDDT_AK - 5 edcs; n ae rtr rsl; eun eut

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edfnto t_2_ATRO; n ucin oICMSE_P

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edfnto t_2_ATRO; n ucin oICMSE_P

I C Controller - The Lab Book Pages

The waveforms below show the Simple Master in operation. Note that this simulation does not include any slave response. So, the slave acknowledge and read data is always read as logic 1.

Simple Master Module waveforms showing a basic I C communication

Setting the Bus Clock Speed

The T C _ U generic sets the frequency of the I C bus clock signal (s l driven by the master. IKNM c) TCNM=(Ck/( *sed)-2 IKU fl 4 pe) wee fl: Feunyo ckipt(z hr, Ck rqec f l nu H) sed ICBssed(isscn pe: u pe bt/eod Here are some examples: fl: 1 MzCok Ck 0 H lc sed 1 ki/ (o-pe md) pe: 0 bts Lwsed oe TC_U =(0000/( *100)-2 IKNM 1000 4 00) =28 4 fl: 5 MzCok Ck 0 H lc sed 10ki/ (tnadmd) pe: 0 bts Sadr oe TC_U =(0000/( *100) -2 IKNM 5000 4 000) =13 2

I C Bus Signal Connections

The serial data signals (s a n& s a u ) and clock signal (s l n from the Simple Master Module need correct interfacing to the open-drain I C bus dI dOt cI) signals. The snippet of VHDL shows how to achieve this.
- Cet Oe-ri ICI - rae pnDan O san< sa dI = d; sa< ''we sau=0 es '' d = 0 hn dOt'' le Z; sl< ''we slu=0 es '' c = 0 hn cOt'' le Z;

This should create a circuit like the one shown below.

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Adding tri-state buffers to I C signals for correct open drain operation

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I C Controller - The Lab Book Pages

Adding tri-state buffers to I C signals for correct open drain operation

NOTE: The Simple Master Module does not respect clock stretching, a technique used by slaves to pause the master. In most cases this should not be a problem. However, keep it in mind if communication fails occasionally.

The Controller Module

The Controller Module provides a more advanced form of I C bus control. It allows sequences of the basic I C to be chained together with basic flow control and a register file for holding temporary values. The image below shows the structure of the Controller Module.

A basic block diagram of the I C Controller Module

The table below describes the available instructions. It's worth mentioning at this stage that the controller design is quite simple and so is easily adjusted to suite other requirements. Instruction ICWIERG 2_RT_E ICWIEIM 2_RT_M Argument, 3 Data, 8 bits bits Register Number Immediate Value Immediate Value Immediate Value Immediate value Address Lower 8 bits of delay count Instruction Address Description Write the data value held in the specified register to the I C bus. Write the immediate value to the I C bus. Read data from the I C bus and load into designated register. Can either A Kor N C the C AK slave. Load the immediate value into the selected register. Add the immediate value to a value held in the selected register. Subtraction is achieved by adding (256 - immediate value). Compare the immediate value with the data value held in the selected register. The result can be used for conditional jumps. Output the value held in the selected register to d u . Output the address value to Ot duAd Otd. Delay the controller for the selected number of milliseconds. Jump to instruction. If condition is E U L only jump if C M matched. If condition is QA, OP N T E U L only jump if C M did not match. If condition is A W Y always jump. O_QA, OP LA, Hold the controller until a the n t f input is asserted. Whilst held, the h l output is oi ed high

I C R A _ A A A K Register 2_EDDT_C I C R A _ A A N C Number 2_EDDT_AK LA OD AD D CM OP OTU UPT DLY EA JM UP HL OD Register Number Register Number Register number Register Number Upper 3 bits of delay count Condition -

The VHDL module entity is shown below. Like the Simple Master, it has a very simple interface. The C K F E generic is used to calibrate the L_RQ D L Yinstruction. Set it to the frequency of the c ksignal in Hertz. The T C _ U generic is set in the same way as described above. The EA l IKNM important part is the P O R Mgeneric that specifies what the controller does. RGA
File E cerpt: I C o t o l r h l 2Cnrle. d ett ICotolri ni 2Cnrle s gnrc(L_RQ eei CKFE ICTC_U 2_IKNM PORM RGA pr ( ck ot l rst ee slu cOt san dI sau dOt hl ed ntf oi duAd Otd :itgr nee; :itgr nee; :ICCNRLE_RG; 2_OTOLRPO) :i sdlgc n t_oi; :i sdlgc n t_oi; :otsdlgc u t_oi; :i sdlgc n t_oi; :otsdlgc u t_oi; :otsdlgc u t_oi; :i sdlgc n t_oi; :otsdlgcvco( dwt 0; u t_oi_etr3 ono )

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d Ad O d d O n D a e a ak o cE edICo ol ; n 2Cn le :o :o :o :o

I C Controller - The Lab Book Pages

dlgc e o( d no0; _oi_ c 3 o ) dlgc e o( d no0; _oi_ c 7 o ) dlgc _oi; dlgc e o( d no0) _oi_ c 7 o );

E ample Program
The controller program is specified as a generic when a controller module is instantiation. An example program is shown below. It is used to read ultrasonic and infrared data from 6 range finding modules. A flow chart for the program is shown to the right. Operation is quite simple. A module counter variable and address variable are first initialised. Then, each module is queried in turn. The counter variable is incremented after each query and checked to see if all 6 modules have been read. The H L instruction is then used to tell the OD host microprocessor that data is ready. When the n i input is asserted, reading loop is o f restarted.

Hold and Notif

This is a very basic interrupt system for the controller. The H L instruction causes the OD controller to pause and assert the h l signal. It will wait at this instruction until the n i ed o f input is asserted. The idea is to connect the h l signal to an interrupt input of the host ed microprocessor, such that the I C Controller Module can indicate that data is ready for reading.

Flo chart of e ample program

cn a ICPO :ICCNRLE_RG0 o1): ( o n 2_RG 2_OTOLRPO( 7 = (p= DLY o > EA, ag= b01, > "1" d a= "8) a > E", (p= LA, o > OD (p= LA, o > OD ag= R, > 0 ag= R, > 1 d a= "0) a > 0", d a= "1) a > C", d a= a > d a= a > d a= a > d a= a > d a= a > "0) 0", "0) 0", "0) 0", "0) 0", "0) 0",

- 0 Sa - :

pDl ( ) ea 1

- 1 Iiil eMdl Nme - : n ai o e b - 2 Iiil eAde - : n ai d - 3 Sa - : - 4 - : Cn o B e(ed o l Ra) - 5 - : Ra l aon ag ed d ne - 6 - : Ra ifae ag ed n d ne - 7 So - : p - 8 O p - : - 9 O p - : - 1:O p - 0 Mdl Nme o e b l aon d ifae ag n d ne

(p= ICSAT o > 2_TR, ag= VI, > OD (p= ICWIERG o > 2_RT_E, ag= R, > 1 (p= ICRA_AAAK ag= R, o > 2_EDDT_C, > 2 (p= ICRA_AANC,ag= R, o > 2_EDDT_AK > 3 (p= ICSO, o > 2_TP ag= VI, > OD (p= OTU, o > UPT (p= OTU, o > UPT (p= OTU, o > UPT (p= DLY o > EA, (p= AD o > D, (p= AD o > D, (p= CM, o > OP (p= JM, o > UP (p= HL, o > OD (p= JM, o > UP ) ; ag= R, > 0 ag= R, > 2 ag= R, > 3 ag= b00, > "0" ag= R, > 0 ag= R, > 1

d a= "0) a > 0", d a= "1) a > 0", d a= "2) a > 0", d a= "8) a > 1", d a= "1) a > 0", d a= "2) a > 0",

- 1:Dl (p o 3 m b enpn ) - 1 ea Ap 0 e e ig - 1:Cm en - 2 op e - 1:Cm en - 3 op e mdl nme o e b d ieade e c d

ag= R, > 0 d a= "6) a > 0", - 1:T - 4 e Mdl Nme o e b ag= NTEUL d a= ad(),- 1:Jm on > O_QA, a > d 3) - 5 p e oa n ag= VI, > OD ag= AWY, > LAS

ed a

d a= "0) a > 0", - 1:Wi f - 6 a o inlfo h ga m o d a= ad() - 1:Jm oiiil eAde a > d 1) - 7 p n ai d

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