IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMSII: EXPRESS BRIEFS, VOL. 53, NO.

9, SEPTEMBER 2006

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A New Simultaneous Multislope ADC Architecture for Array Implementations

Leif Lindgren
AbstractThis brief presents a new simultaneous multislope analogdigital converter (ADC) architecture suitable for array implementations in, e.g., CMOS image sensors (CISs). The simplest implementation is almost twice as fast as a conventional-slope ADC, while it requires only a small amount of extra circuitry. Measurements have been performed on a custom made CIS which implements parts of the proposed ADC. The measurements show good linearity and verify the concept of the new architecture. Index TermsAnalogdigital converter (ADC), analogdigital (A/D) conversion, CMOS image sensors (CISs), simultaneous multislope (SMS), single slope.

I. INTRODUCTION

N general, there exist three architectures for on-chip analogdigital converters (ADC) for CMOS image sensors (CISs). They are one single ADC for all pixels, a column parallel ADC, and one ADC per pixel. Also some derivatives of these exist. A drawback of the single ADC is the speed required for high-speed imaging. The pixel level ADC can handle very high speed, however, it drastically decreases the ll factor. For high-speed applications, the column parallel architecture is often chosen and it is the architecture studied in this brief. Three different types of column parallel ADCs have often been used for CISs. They are cyclic ADC, successive approximation (SA) ADC using switched capacitor charge sharing, and single-slope ADC. Drawbacks with the cyclic converters are size, speed, resolution, and problems with charge injection from switches. The cyclic converters use at least one operational transconductance amplier (OTA), one comparator, and two linear capacitors per column [1]. One converter can, typically, not t into the pixel pitch, e.g., in [2] each converter was four pixel columns wide. Furthermore, a central voltage generator needs to charge capacitors in each column and the OTA and comparators need to settle each cycle. For sensors with many columns, this severely limits the conversion rate. Fully differential solutions can be used to reduce the problems with charge injection and an accuracy of about 9 bits was then reported in [2], but this adds circuitry and power. CISs with column parallel SA ADCs using charge redistribution have been successfully demonstrated several times. It requires a comparator, bits of memory, and binary scaled capacitors per ADC channel, where is the number of bits. For

keeping column to column xed pattern noise (FPN) low a calibration circuit is also needed in each column. In [3] a 10-bit SA ADC is used and the calibration circuit alone is implemented as a 7-bit capacitor bank. The main advantage of this type of ADC is speed. Drawbacks are size and the need for matched capacitor ratios, which can limit the accuracy. To get good linearity the layout of the capacitors is crucial and an ADC typically requires the width of two columns and becomes several mm high. Single-slope converters have often been used for CISs partly because they only need one comparator and bits of memory per channel. This makes it easy to t one channel into one column, e.g., in [4] each column was only 5.6 m in a 0.6- m process. This is very important for smart vision sensors having a column parallel single-instruction multiple data (SIMD) processor on-chip [5]. Another reason is that it is fairly simple to get good accuracy. High linearity is realized by having a good global voltage slope generator, typically implemented as a counter and a DAC. Then, the comparators should have low temporal noise, and be offset compensated and have moderate delay variations for keeping FPN low, e.g., in [4] FPN was less than 0.1 mV. For CISs the possibility of high resolution is becoming more important due to the increased dynamic range offered by buried photodiodes. Furthermore, the single-slope ADC permits multiple thresholding, an operation important in many machine vision applications. A drawback is speed since one conversion requires clock cycles. It is, however, possible to trade accuracy or signal swing for higher speed simply by controlling the counter feeding the DAC. The clock frequency can also be much higher than for the cyclic and SA ADCs, in [5] a 33-MHz clock was used. This is because nothing needs to settle each cycle since the delay from the DAC and the comparators only adds a dc-offset which, if needed, can easily be compensated for. This brief introduces a new column parallel ADC architecture, named simultaneous multislope (SMS), suitable for, e.g., CISs. It is a further development of the single-slope ADC, but contrary to the single slope it uses several slopes simultaneously thus greatly increasing the conversion rate. Advantages of the single slope like small size, high accuracy, and multiple thresholding are kept. II. ARCHITECTURE The proposed SMS ADC architecture works like a column parallel single-slope ADC except that it has one comparison phase and one slope phase. Furthermore, several slopes are used in parallel during the slope phase, where each slope covers a part of the total signal swing. Compared to the single-slope ADC some control circuitry, thctrl in Fig. 1, and an analog multiplexer

Manuscript received October 3, 2005; revised January 11, 2006, and March 7, 2006. This paper was recommended by Associate Editor B. Zhao. The author is with Electronic Devices, Linkpings Universitet, SE-581 83 Linkping, Sweden (e-mail: lei@isy.liu.se). Digital Object Identier 10.1109/TCSII.2006.881817

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IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMSII: EXPRESS BRIEFS, VOL. 53, NO. 9, SEPTEMBER 2006

Fig. 2. Slopes for a two-slope SMS ADC (1 and 2), and two-slope SMS ADC with a CS DAC (1 and 3).

operation. If the input signal instead is lower than the DAC signal a 0 is stored in the MSB and the rst slope will be used during the slope operation. The slope operation then determines the rest of the bits. s
Fig. 1. Block diagram of the SMS architecture.

A. Using Current Steering DACs An efcient way to implement the slope generation is to use a current steering (CS) DAC. In a CS DAC there exist a number of current sources; in a thermometer coded, in a binary weighted, and something in between in the case of a segmented DAC. A voltage is generated at the output via a load resistor or by using an opamp with a resistive feedback. For good dynamic performance the current sources not connected to the output are connected to ground or to a dummy resistor. By using this dummy output a slope with the opposite sign to the original output is created at virtually no cost. Thereby, two slopes are generated by one CS DAC. This is shown by slope1 and slope3 counter in Fig. 2 where the voltage range is covered after steps. When using both outputs from a CS DAC the bits obtained from the slope operation need to be handled in a different way, since the slopes have different sign. When the negative slope is used the latched counter bits need to be transformed to their corresponding ADC output value. This is simply done by inverting these bits. For the two-slope SMS example this means that the MSB, which is obtained in the threshold operation, determines if the rest of the bits are to be inverted or not. This operation is performed using a simple XOR operation for each latched counter bit. For sensors with a column parallel SIMD processor on-chip this is easily handled in each column. For other sensors this only needs to be performed when reading out the digital data which number of XOR gates is means only one central unit with needed. Compared to a single-slope ADC using a CS DAC, this two-slope SMS ADC is almost twice as fast and only a small amount of extra circuitry is needed. B. FPC Noise in a CIS is higher for highly illuminated parts of the , where image. This is because photon shot noise grows as is the number of electrons, and because conversion gain variations among the pixels causes gain FPN. This means the requirements for low quantization noise decreases as the signal increases. This can be utilized by using larger quantization steps for the upper part of the signal range. In [6] a 10-bit pseudoconversion was realized in 397 clock cycles by using 10-bit steps

at the comparator input is added in each column. All slopes are distributed to the analog multiplexers, enabling each column to select which slope to connect to the comparator input. A conversion starts with the comparison phase where number of consecutive threshold operations are performed, where is the number of slopes used. The slopes are set to their initial value and then the analog multiplexers are set so the input signal in each column is compared to slope number 2 through respectively. The results from these threshold operations are stored in thctrl in each column, and determine which of the slopes each column is to use during the following slope phase. During the slope phase the actual slope operation is performed where the output of a global counter is fed to the slope generators and to the columns. When the comparator in a column changes state a load pulse is generated by slctrl and the counter value is latched. The digital result, in each column, is then given by a combination of the stored threshold result bits and the latched counter value. For sensors with a column parallel SIMD processor on-chip the obtained result is then moved to the processor part, while for other sensors it is moved to output registers in each column (not shown in Fig. 1) which are then scanned during the next conversion. The simplest example is the case when two slopes are used, which is depicted in Figs. 1 and 2. In Fig. 2 a traditional single-slope converter would use an extended (dotted) slope1 counter steps to cover the entire voltage range, and use while the new SMS converter uses slope1 for the lower voltage range and slope2 for the upper voltage range and needs only counter steps. For an -bit ADC using two slopes, one 2 of the slopes covers the signal range corresponding to the while the other slope covers digital values . The threshold operation is performed by comparing the input signals to the lowest value of the second slope (or the max value of the rst slope depending on implementation). If the input signal in a column is higher than the DAC signal a 1 is stored in thctrl, as the MSB of that column, and the second slope will be used during the slope

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TABLE I EXAMPLE CONFIGURATIONS FOR AN ADC USING TWO OR FOUR SLOPES

Fig. 3. Block diagram of a CS circuit for generation of four slopes.

for the lower part of the signal range and then increasing the step-size to 8-bit steps. In [5] this technique was referred to as fast pseudoconversion (FPC) and the counter step-size was doubled after reaching the value 64, resulting in 38% shorter conversion time. It is possible to build SMS ADCs that also use FPC by having different gains on different slopes. The simplest case is when two slopes are used and the second slope has, e.g., twice or four times as high gain as the rst. Having the gain of the second slope twice as high means the conversion only needs counter steps, and having it four times as high means counter steps. One way to implement this is to have a CS DAC with a load resistor with twice as high resistance for the second slope. The digital result from a column using the second slope is then obtained by inverting the latched counter bits, hard-wire . shift them one step, and then add Table I describes some possible congurations for SMS FPC converters using two or four slopes. The rst columns describe means the resolution from the different slopes where, e.g., the slope has twice as high gain as the rst slope. The last three columns describe how many clock cycles that are needed for , and one conversion. E.g., the 8th row has for the different slopes. For a 12-bit FPC converter this would clock cycles to perform the mean conversion, and the step-sizes of the four different slopes correspond to the step-sizes from a 12-, 11-, 10-, and 9-bit converter respectively. There is a wide variety of ways to implement SMS FPC converters. Fig. 3 shows an example block diagram of a CS-based circuit for the generation of four slopes. The circuit has six banks of current sources, four for ne tuning the offsets (though, this may not be needed for slope1) and two for producing the actual slopes. Each current source in the offset banks has its own latch and each source can either be on or off. The two-slope banks can share latches making each current source pair either connected to slope1 and slope3 or slope2 and slope4. All current source banks share a common digital encoder. A control block inputs the desired setting to this encoder and then clocks latches in the current source bank that is to use this new setting. The four output voltages are then produced using opamps with resistive feedback. By feeding the encoder with the output of a counter and clocking loads, slope1 and slope3 will be positive voltage slopes while slope2 and slope4 will be negative. There are many different current steering coding architectures available, e.g., binary-weighted, thermometer coded,

segmented, and decomposed. For the 12-bit FPC example a 7-bit segmented approach would mean that the 7 MSBs in the code word from the controller are thermometer coded, while the 2 LSBs are either binary coded or thermometer coded. For each bank this would mean 68 current sources set by the 7 MSBs, and these sources would be four times larger than the unit current source controlled by the LSB. Having the 2 LSBs thermometer coded would mean a total of 71 current sources per bank and a total of 355 latches for all six banks together. , and , can be used to The reference voltages move the offsets coarsely, and can simply be generated with, e.g., a resistor string and bypass capacitors. For high accuracy the size of the current sources in the offset banks should be smaller than the corresponding slope sources. To get very low differential nonlinearity (DNL) where the slopes meet the inherent delay of the slopes and comparators also needs to be taken into account, when using both positive and negative slopes. This is done by slightly increasing the starting point of a positive slope and decreasing the starting point of a negative slope, using the offset programmability, after a static ne tuning has been performed. The number of columns connected to a certain slope during the slope operation depends on the signals in the row that is currently converted. This means the actual load on a slope depends on the image content. For this trimming to work well the load dependent delay from the slopes should, therefore, be kept small. The 12-bit FPC converter in the example could be realized , and in Fig. 3. by having Another way would be to have , and and then increase the current sources in bank slopesources34 to be four times the size of the ones in the bank slopesources12. III. ADC CHARACTERIZATION An ADC suffers from both dynamic and static errors. For a CIS ADC the dynamic errors are characterized as temporal noise, while the static errors include integral nonlinearity (INL) and DNL. The static performance is often measured as max INL and max DNL. For an ADC in a CIS with active pixels these are, however, rather bad measures. This is because the requirements on the ADC decrease with increased signal due to the fact that the sensor noise increases with the signal. This means, e.g., that a high DNL peak occurring in the high part of the input signal range, like for the middle curve in Fig. 4(a), would mean a high max DNL, but it would not have any big effect on the total error since temporal noise and FPN is already quite high in this signal range. Another reason for these measures to be bad is that a very

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IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMSII: EXPRESS BRIEFS, VOL. 53, NO. 9, SEPTEMBER 2006

Fig. 4. (a) Measured DNL, (b) INL, and (c) INL with disregarded samples at the beginning and end, for positive (top), negative, and SMS (bottom) conversion.

low INL of the ADC is not needed since the charge to voltage conversion is slightly nonlinear. This is due to the voltage dependent capacitance of the photodiode, and because the gain of the source follower in the pixel is also slightly voltage dependent. This nonlinearity in the sensor signal chain means low-frequency behavior of the ADC INL vector is not a big concern. When characterizing ADCs for CISs the entire INL and DNL vectors should be studied. If the measured INL vector contains low-frequency components these could, for evaluation purposes, simply be removed by high-pass ltering the vector. Furthermore, when characterizing a multi-channel ADC each channel has its own static transfer curve. Deviations between the channels are characterized as FPN. A simple estimate of the error introduced by the ADC, as a function of input signal, is the square root of the sum of the squared ADC FPN, temporal noise, DNL (or high-passed ltered INL), and quantization noise. Calculating this makes it possible to compare the accuracy of ADCs with different resolution, a possibility desired in, e.g., [7]. The result can also be compared to the noise from the image sensor part to see to what extent the ADC adds to the total error. IV. EXPERIMENTAL TEST A. Setup and Calculations Measurements have been carried out using a custom made CIS previously presented in [5]. The sensor has 1536 512 standard three transistor active pixels with a pitch of 9.5 m, and was implemented in a 0.35- m process. The sensor has a column parallel slope ADC clocked at 33 MHz with programmable resolution, gain, and offset. Furthermore, it has a multiplexer at each comparator input making it possible to perform A/D conversion using either a positive or a negative slope. However, the slopes cannot be used simultaneously because the selection of the slopes is done globally for all columns, contrary to Fig. 1. The new SMS ADC architecture can, however, be mimicked on-chip, making it possible to measure parameters like INL, DNL, and FPN. The SMS ADC is mimicked by rst performing a threshold operation that determines which of the two slopes that should be

used by each column. To get low DNL at the midpoint during the dynamic slope operation the offset programmability is then used to compensate for the delay in the DAC and the comparators. Then a conversion with the positive slope is performed and the results are stored in the on-chip column memory. Another conversion is then performed with the negative slope. Since both slopes here covers the entire signal swing the results need to be limited. This is done by the on-chip SIMD processor by setting the results that exceeds 127 from the rst conversion to 127, and the results from the second conversion being below 128 are set to 128. The on-chip SIMD processor then uses the threshold bit obtained in each column to multiplex the results from the two conversions. It was possible to characterize the ADC due to the possibility to feed an analog value from an external 14-bit DAC to the input of the internal ADC. To reduce the temporal noise 64 of the above type of conversion are made for each input voltage level. The results are rst accumulated in each column by the SIMD processor and then sent to a PC. B. Results The internal DAC was characterized in [5] with good results. It uses 135 mW and in 8-bit mode and a swing of 1 V a DNL rms of 0.04 LSB, a DNL max of 0.12 LSB, an INL rms of 0.04 LSB, and an INL max of 0.13 LSB were measured. The ADC DNL and INL were measured individually for all 1536 columns using 8-bit mode and a swing of 1 V, and the results for all columns were very similar. Fig. 4(a) shows the measured DNL vector for the ADC in one of the columns for a single-slope conversion using the positive slope, a single-slope conversion using the negative slope, and a mimicked SMS conversion. The DNL measurements show that the very rst few steps of an A/D conversion were smaller than the rest of the steps. It is believed that this is due to the delay of the internal DAC and the comparators becoming settled after a few counter steps [5]. A simple solution would, in that case, be to have a few dummy steps in the beginning of the slope operation. In reality the smaller steps actually gives higher resolution for the rst gray levels, resulting in higher dynamic range but lower linearity.

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TABLE II MEASURED DNL/INL (AVERAGE OF ALL COLUMNS) AND FPN IN LSB FOR SINGLE SLOPE (SS) AND SMS CONVERSIONS

FPN curve in Fig. 5 it is evident that the limited resolution of the quantization greatly affects the calculated FPN. This is because the mean output value from each ADC depends on the mean input value and the temporal noise referred to the input, see [8]. It is possible to accurately refer the FPN back to the input of the ADC by modifying the method in [8]. This is done by rst rounding the digital result in each column. FPN is then calculated on these rounded results, see bottom plot of Fig. 5. As expected the peaks of the FPN curve now reaches 0.5 LSB. After rst making sure there are no gradients among the columns the distribution is assumed to be Gaussian. This makes it possible to apply the equations in [8] on the mean and rms value of the new FPN vector and, thereby, get the ADC input referred FPN. The second last row in Table II shows input referred FPN calculated using the mean value, and the last row when using the rms value. V. CONCLUSION AND DISCUSSION This brief presented a new simultaneous multislope ADC architecture suitable for array implementations in, e.g., CISs. It is a further development of the single-slope ADC and it increases the conversion rate signicantly at a low cost in extra hardware. Measurements on a custom made CIS veried the concept of the new architecture. Assuming a sensor with the HDTV resolution of 1920 1080 pixels, 2/3 optics, a pixel pitch of around 5 m, and a 0.18- m process, then, for such a process and sensor size, a 66-MHz ADC clock frequency is feasible. The example 12-bit pseudoconverter using four slopes would then realize almost 200 frames/s. The architecture also permits having two converters per column, placed at the top and bottom similar to [7], which would mean almost 400 frames/s. REFERENCES
[1] K. Chen and C. Svensson, A parallel A/D converter array structure with common reference processing unit, IEEE Trans. Circuits Syst., vol. 36, no. 8, pp. 11161119, Aug. 1989. [2] S. Decker, R. D. McGrath, K. Brehmer, and C. G. Sodini, A 256 256 CMOS imaging array with wide dynamic range pixels and columnparallel digital output, IEEE J. Solid-State Circuits, vol. 33, no. 12, pp. 20812091, Dec. 1998. [3] A. I. Krymski, N. Bock, N. Tu, D. Van Blerkom, and E. Fossum, A high-speed, 240-frames/s, 4.1-Mpixel CMOS sensor, IEEE Trans. Electron Devices, vol. 50, no. 1, pp. 130135, Jan. 2003. [4] T. Sugiki, A 60 mW 10b CMOS image sensor with column-to-column FPN reduction, in Dig. Tech. Papers IEEE ISSCC, 2000, pp. 108109. [5] L. Lindgren, J. Melander, R. Johansson, and B. Mller, A multiresolution 100-GOPS 4-Gpixels/s programmable smart vision sensor for multisense imaging, IEEE J. Solid-State Circuits, vol. 40, no. 6, pp. 13501359, Jun. 2005. [6] W. Yang, O.-B. Kwon, J.-I. Lee, and G.-T. Hwang, An integrated 800 600 CMOS imaging system, in Dig. Tech. Papers IEEE ISSCC, 1999, pp. 304305. [7] A. I. Krymski and N. Tu, A 9-V/Lux-s 5000-frames/s 512 512 CMOS sensor, IEEE Trans. Electron Devices, vol. 50, no. 1, pp. 136143, Jan. 2003. [8] L. Lindgren, Elimination of quantization effects in measured temporal noise, in Proc. IEEE Int. Symp. Circuits Syst., May 2004, vol. 4, pp. 392395.

Fig. 5. Measured FPN versus counter value for the external DAC.

The bottom curve in Fig. 4(b) shows that the SMS operation works as intended and no large DNL errors occur at the midpoint. Furthermore, Table II shows the measured DNL for the SMS conversion to be close to what was measured for the singleslope conversion, and the last two columns (SSc and SMSc) show that very good linearity is achieved when a few samples in the beginning and at the end are disregarded. Fig. 4(b) shows the measured INL vector for the ADC in one of the columns for a single-slope conversion using the positive slope, a single-slope conversion using the negative slope, and a SMS conversion. The INL vector for the SMS conversion looks as expected. These INL plots are greatly affected by the smaller ADC steps described above. Since the solution to this problem seems simple, Fig. 4(c) shows the measured INL vectors when disregarding a few samples in the beginning and at the end. INL then becomes almost as low as for the DAC, see Table II, and the SMS conversion does not degrade the linearity compared to the single-slope conversions. ADC input referred FPN should not be affected by the SMS architecture. However, any DNL errors introduced in the crossover between two slopes would affect the quantization transformation of the ADC input referred FPN. For each counter value of the external DAC, ADC FPN was measured as the standard deviation among the ADC channels for SMS conversion, see Fig. 5. From the sinus-like shape of the middle