CAD for VLSI 1 Pro ject - 8279 Display and Keyboard Controller

8279 is a programmable display and keyboard controller. Intel 8279 chips are part of many standard microprocessor kits that schools use and also of a variety of industrial applications with small amounts of data I/O. The device is well suited for driving seven or eighteen segment display units and for interfacing matrix keyboards. Dedicated peripheral for display and keyboard control will free the processors in the host machines from a variety of chores.

Reference
Refer to the material in the book Microprocessors and Interfacing : Programming and Hardware by Douglas V. Hall, Glencoe McGraw Hill, ISBN-0070257426. The material has general description about interfacing 8279 with a SDK-86 board. We are interested only in the display and keyboard subsystem and so any material concerning the board is irrelevant to us. However, all programming features are listed in the material.

Basics of Keyboard Interfacing Matrix keyboards are connected in a series of rows

and columns as shown in the material. The important tasks in interfacing a keyboard are 1) detecting a keypress, 2) debounce the keypress and 3) encode the key to some standard code. Refer to Pages 281-285 for general introduction to keyboard interfacing. Pay particular attention to the matrix keyboard layout and the flowchart in the material. Understand how the rows are selectively pulled down and how the columns are checked to detect the keys. Two definitions are important for keyboard interfacing. They pertain to detecting multi- ple simultaneous inputs. In 2-Key Lockout mechanism, one key must be released before the other key is detected. In the N-Key Rollover mode, if two keys are pressed almost simultaneously, both keypresses are detected and are placed in a queue.

Basics of Alphanumeric Displays

8279 can be used to control a variety of display units. In this project, 8279 is used to drive LED displays only. In a multi-character LED display, the data inputs are sent on a common bus, but different positions are selectively turned on in sequence. The refresh is done fast enough to hide the multiplexing. This allows the display unit to have very few data lines coming in and also reduces power consumption. For a multiplexed display, timing the character position that is displayed is very critical. 8279 takes care of this timing.

Basics of 8279 Programming

8279 has two internal addresses which are memory mapped in the host CPU. The input line A0 selects one of these two addresses. If A0=1, the control and status registers in the 8279 are chosen. If A0=0, 8279 is enabled for reading data from it or writing data to it. 1

 When control/status is chosen, the device takes in control words. The first 3 bits of the 8-bit control word identify the operation or the mode that is chosen. Rest of the bits are interpreted according to the mode. The material given has detailed descriptions on how to interpret the control word.

System Description
The basic block diagram of the system that you are designing is shown in Figure 1. The

D7D0 B3B0 RESET CLK A0 A3A0

16 CHARACTER DISPLAY

CPU

RD WR IRQ

8279

BD SL0 SL1 SL2 SL3 DECODER

RL3RL0

16KEY
MATRIX KEYBOARD

KEYBOARD CONTROL

Figure 1: Block Diagram of the 8279 Based System system consists of a 8279 device which is configured by a host CPU. The host CPU sends a series of control words and also does data I/O. The control word is passed on using the data lines D7-D0. The bus is bi-directional and is also used to read the keyboard input. The lines RD and WR are used for read/write control. Reset is active high and the CLK should run at 3 MHz.

8279 - Internal Block Diagram Internal organization of 8279 is shown in Figure 2.

The device runs internally at 100 kHz. Since the CLK input is at 3 MHz, the clock has to be divided inside to 100 kHz. For doing so, proper Program Clock Word must be sent to the device and then the device is ready for Data I/O. The block diagram shows all the internal blocks for both keyboard and display control.

1. Display is achieved using 1) the internal 168 Display RAM, 2) the Timing control unit and 3) the Scan Counter. CPU fills the display RAM with data. The data must be in seven segment format. The scan counter counts from 0000 to 1111 and places its output on the line SL3-SL0. Based on the scan count generated, the Decoder shown in Figure 1 selectively turns one of the sixteen characters in the display unit. The timing control for the display is done by the signal BD. The characters are displayed from digit 1 to 16 and then returns back to 1. The time 8279 takes between two updates to the same digit position is called the scan time. 2. The 16 character keyboard is organized as a 44 matrix keyboard. We use only the last two bits of the scan counter, namely SL1 and SL0. Keyscan is achieved by driving one row to 0 at a time and detecting for one of the columns being 0. If there is a key press, the corresponding column goes low and the column information is passed on to

Figure 2: Schematic Diagram of 8279 8279 through the lines RL3-RL0. 8279 knows the row code that is being generated and we can scan lines RL3-RL0, effectively detecting the exact key that is pressed. After detecting a keypress, 8279 waits for a debounce time and scans the key again. If keypress is still present, it produces a 8-bit keycode based on the column and the row in which the key is pressed. The keycode is then placed in the internal 8-byte FIFO RAM. If a valid keypress is found, it asserts an Interrupt Request to the CPU through the line IRQ. It is up to the CPU to read the data. Meanwhile, 8279 increments FIFO count in the internal status register.

In both cases, CPU communicates with the 8279 only when there is a character that needs to be displayed or if a keypress is detected. For more details, consult the material given in the class.

Timing Diagram
Please refer to Figure 3 for the control signals that 8279 generates. The display unit is timed such that driving a digit requires 490 s and blanking requires 150 s for a total of 640 s, after which next character must be placed out. BD signal goes low to indicate that the blank character is sent out on ports A and B and is followed by the character. We have a 16-character display and hence we will cycle through the same digit every 16*640 = 10.3ms. The keyboard is probed for 160 s every row. During the first 80 s, the scan is latched from that row. The key is again checked after 40 s. Now, if the character is a valid keybounce, the FIFO RAM is updated.

Constraints
1. The CPU, 8279, Display unit and Keyboard unit must all be separate design entities. 2. You must design the 8279 device and all the associated peripheral components to satisfy the timing constraints specified. The design must be synthesizable. 3. The host CPU must be a simple processor capable of configuring your 8279 device and processing of interrupts from the device. The CPU must send the commands in particular order and should generate RD, WR, A0 signals etc in correct order. Use 3

S0

640 us = 64 tCLK

S1

A0A3

BLANK CODE

A(0) 490

BLANK CODE

A(1)

BLANK CODE

B0B3 80 BD 70

B(0)

B(1)

160

RL0RL3
120 80

RL0

RL1

RL2

RL3

RL0

RL1

RL2

RL3

Conditional Write to FIFO RL0 Latched

Figure 3: Timing Diagram for Display and Keyboard Scans the material provided as reference for the programming model. You dont have to design an instruction set machine to do this. You can use waveforms to generate the signals. The CPU need not be synthesizable. 4. Perform simulation with characters 0000 to 1111 input through the keyboard in 2-key lockout mode. The CPU must read in the data, find the equivalent 7-segment code and write it to the 8279s display RAM. 8279 must be configured for displaying elements in left entry. 5. Perform another simulation with the same set of characters, but with N key rollover mode for the keyboard and right entry for the display. 6. Synthesize your design for both Flex family and using Magma. Optimize your design for area and delay. Detailed synthesis requirements will follow.

Pro ject Report

Turn in a neatly typed report stating the goals of the project in brief. Describe your design clearly starting with the machine design, how you have modeled various subsystems and how you handled the timing requirements. The report will be graded as follows : 1. Introduction [5 Points] Abstract Table of Contents Basic summary of your design and results 2. Hardware Design [50 Points] Basic hardware description Functional block diagram Design of 8279, Keyboard and Display Well annotated Verilog code

 Detailed Simulation Results 3. Synthesis and Analysis [20 Points] Synthesize your design for both the FPGA and ASIC flow. More detailed requirements for synthesis will follow. 4. Testbench [10 Points] Test Strategy CPU Design - In many ways, CPU will itself be the testbench Well annotated testbench code 5. Report Format and Style [5 Points] 6. Discussion [5 Points] Talk to another group whose project was different from yours. Find out details about their project and explain briefly how they designed their project. Also, give details of their test strategy. Write a one-page report about the other groups work. Clearly describe how you divided your tasks among your group members. Each of you must write a brief evaluation of the other members work. Be honest. Hand them in individually. Do not attach it with your project report. The review that you give about your partners will be held confidential.

7. Progress Report [5 Points] Turn in a 2-page progress report that describes your preliminary studies and your hardware design strategy. The progress report is due on Apr 13 2007 in class.