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6, JUNE 2007

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RNS-to-Binary Converters for Two Four-Moduli Sets 2n 1; 2n; 2n + 1; 2n+1 1 and

1 2 2 + 1 2 +1 + 1
;
n

P. V. Ananda Mohan, Fellow, IEEE, and A. B. Premkumar, Senior Member, IEEE

AbstractIn this paper, reverse converters for two recently pro1 2 2 + 1 2 +1 1 and posed four-moduli sets 2 2 1 2 2 + 1 2 +1 + 1 are described. The reverse conversion in the three-moduli set 2 1 2 2 + 1 has been optimized in literature. Hence, the proposed converters are based on 1)) 2 +1 1 and (2 (22 two new moduli sets (2 (22 1)) 2 +1 + 1 and use mixed radix conversion. The resulting designs do not require any ROM. Both are similar in their architec1 2 2 + ture except that the converter for the moduli set 2 1 2 +1 + 1 is slightly complicated due to the difculty in performing reduction modulo (2 +1 + 1) as compared with modulo 1). The proposed conversion techniques are compared (2 +1 with earlier realizations described in literature with regard to conversion time as well as area requirements. Index TermsDigital signal processing, mixed radix conversion (MRC), powers of two related moduli set, residue number system (RNS)-to-binary conversion, reverse converters, VLSI architectures.

I. INTRODUCTION HE advantages of using the residue number system (RNS) over the conventional binary number system are well documented [1][4]. Early researchers considered using mutually prime integers as moduli in the chosen RNS, and the solutions for realizing all arithmetic operations were based on ROMs in order to speed up execution. However, it was later realized that by using powers-of-two related moduli sets, the need for ROMs to build RNS-based processors can generally be eliminated, and the basic building blocks needed such as adders, multipliers, binary-to-RNS converters, and RNS-to-binary converters can be easily realized using logic gates. An extensively investigated three-moduli set belonging to this class is [5][23]. Subsequently, another powers-of-two related three[24][26], was also moduli set, viz., proposed and studied. Two somewhat related three-modulo sets, [27], [28] and viz., [29][31], were also proposed. Much attention was on the problem of RNS-to-binary conversion since many operations

such as scaling, comparison, division, and sign detection invariably need conversion from RNS to binary and to some extent on binary-to-RNS conversion. Recently, it was suggested that four-moduli sets will be of interest since the dynamic range achievable with three-moduli bits with each modulus using -bit sets is on the order of word length. Some of the four-moduli sets suggested were [34], [33], [32], and [35]. Among these, the moduli set is valid for even whereas the moduli set is valid for odd. The moduli sets , and have no such restrictions. However, the moduli set has one modulus of -bit word length whereas two moduli -bit word length. The moduli have -bit and one has has two moduli of word set length bits and two moduli have -bit word length. The RNS-to-binary conversion problem has been addressed sepa[34] rately for the moduli sets [33]. In this paper, we inand vestigate the RNS-to-binary conversion problem for these two moduli sets. We consider these two moduli sets as extensions of so that the RNS-to-bithe three-moduli set nary converters of the four-moduli set can utilize the best converter available for the three-moduli set from the point of view of speed as well as area and augment it to realize the converter for the four-moduli sets. In Section II, we present the necessary background material. In Section III, we describe the RNS-to-binary converters for the moduli sets and in a unied manner. In Section IV, the area and conversion times of the proposed converters are presented. In Section V, we compare the proposed converters with those available in literature, and, in Section VI, we make some concluding remarks. II. BACKGROUND MATERIAL using mutually prime integers as moduli, the dynamic range is . The the product of the moduli, numbers between 0 and can be uniquely represented by the residues. A large number can thus be represented by several smaller numbers, thereby facilitating big word-length operations to be realized as several small word-length operations. The addition, subtraction, and multiplication operations can thus be performed quite efciently. The division, sign In an RNS,

Manuscript received April 11, 2005; revised May 18, 2006 and August 24, 2006. This paper was recommended by Associate Editor S.-G. Chen. P. V. Ananda Mohan is with the Electronics Corporation of India Ltd., Bangalore 560 052, India . A. B. Premkumar is with the Division of Computing Systems, School of Computer Engineering, Nanyang Technological University, Singapore 639778 (e-mail: asannamalai@ntu.edu.sg). Digital Object Identier 10.1109/TCSI.2007.895515

1549-8328/$25.00 2007 IEEE

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detection, and comparison are of course time consuming in RNSs. The input binary number needs to be converted to residues using a front-end binary to residue converter. On the other hand, the results of the computation of several residue processors need to be combined to form a large single word using an RNS-to-binary converter. There are two basic approaches to converting a number from RNS to binary form. These are the Chinese remainder theorem (CRT) and mixed radix conversion (MRC). The binary number corresponding to given residues in the can be derived using CRT as RNS

Fig. 1. MRC technique for the moduli sets

f2 0 1 2 2 + 1 2
; ; ;

6 1g.

(1) where for . The quantities are known as the multiplicative inverses of . The summation in (1) can be much larger than and the reduction to obtain is a cumbersome process. The advantage of the CRT is that the weighting of the residues can be done in . parallel and results summed, followed by reduction The MRC, on the other hand, is sequential and involves modulo subtractions and modulo multiplication by multiplicative inverses of one modulus with respect to the remaining moduli. In MRC, the decoded number is expressed as

(2) In each step, one mixed radix digit as well as several interare determined. However, mediate results the MRC algorithm can be pipelined. At the end, the MRC digits are weighted following (2) to obtain the nal decoded number. There is no need for nal modulo reduction. The MRC is used extensively in this paper. III. RNS-TO-BINARY CONVERTERS FOR MODULI SET
AND

The rst moduli set using even, evidently, uses two -bit word-length moduli and two -bit word length. Its dynamic range is moduli of . We denote the residues corresponding to this as . On the other moduli set hand, the second moduli set (with odd), uses two -bit word length moduli and one mod-bit word length and one modulus of -bit ulus of word length and has a dynamic range of . We denote the residues corresponding to this moduli set as . The conversion procedure is rst described for both sets of moduli. This consists of four steps. Step 1) Perform the RNS-to-binary conversion of the subset corresponding to of these residues, viz., by using techniques due the moduli to Dhurkadass modication of Piestraks method [15] and Wang et al. [20], [22]. These need mapping

of the bits of the residues , and and adding the resulting three -bit words with end-aroundto obtain the most sigcarry modulo nicant bits of the decoded word . Appending to this -bit word as least signicant bits (LSBs) yields the complete decoded word . The conver, where sion time is about and are the delay of a full adder and inverter, respectively. The area requirement is about and , where and are the areas of a full-adder and inverter, respectively. The next three steps perform the RNS-to-binary conor correversion of the residues sponding to the respective moduli sets and . We suggest the use of MRC for this purpose. The MRC technique applicable for both the moduli are sets is illustrated in Fig. 1. Since only and different in these two moduli sets, for the purpose of to denote and . illustration we use Step 2) Evaluate . Note -bit that is -bit wide whereas is only -bit wide in the case of the rst moduli set and wide in the case of second moduli set. The residue can be easily found using the of periodic properties of residues of various powers of two [7], [36][40], as will be explained later. The next step is to evaluate using a subtractor modulo . , the multiplicative inStep 3) With the knowledge of with respect to verse of , the mixed radix digit can be computed as . can be obtained as Step 4) Finally, the decoded number . Note that, here, we make use of the fact that the LSBs of the decoded word ,viz., in the are available as the residue corresponding to data itself. The decoded word the given residue set can be obtained noting that the -bit word can be written as , where as

(3) Thus, needs to be determined.

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We next consider the evaluation of , , , and for both the moduli sets in order to compute (3). : This needs to be considered sepaEvaluation of rately for the two moduli sets since the operations pertain to different moduli in the two cases. In the evaluation of , rst needs to be evaluated. For this purpose, can be divided (for ) as three -bit elds , , and , where . These three words need to be added using a carry save adder (CSA) with end around needs carry (EAC). Note, however, since the residue of to be subtracted from , instead of adding -bit elds and then subtracting from , the three , the three -bit since the operation is need to be ones complemented and added to elds of using a CSA with EAC. This can be seen to be correct, since or ones complement of -bit words need to be added using an EAC a. Thus, four CSA followed by a carry propagate adder (CPA) with EAC to . realize reduction modulo On the other hand, in the evaluation of , rst needs to be can be found determined. The residue of using the periodic properties of the residues of various powers of two [7], [36][40]. It is known that the residues of the exhibit perivarious powers of two, i.e., and odic behavior. Specically, . As an illustration, consider . It can be for , 1, 2, 3, 4, 5, and seen that for , 1, 2, 3, 4, 5. Hence, can be -bit elds , , such that divided as three (4) can be seen to be . Note, however, that since the residue of needs to be subtracted from to obtain , the operation needs to be performed. We note here that addition of can be realized as addition of where , and are ones complements and with respect to (i.e., and are of -bit words with a MSB appended as zero). considered as This can be explained as follows: for all and the value

with the value 6 mentioned above, means an overall addition of either 4 (in the case of one carry being one) or 2 (in the case of two carries being one) and 6 in the case of both the carries being or 4 or 2 needs to be added to the four zero. Thus, either . A modulo reduction operands , , , which needs at is needed to evaluate the result -bit word, since the most three subtractions to yield a result is less than . of Evaluation of : The multiplicative inverse with respect to can be found as (6) and for . Note that has Next, the multiplicative inverse of can be found for spect to bits which are 1. with reas (7) where the terms other than the last two, i.e., and 2, exist till . Note that for , . Evaluation of : We rst note that needs to be computed to obtain the mixed radix digit . The can be seen to be addition evaluation words obtained by circularly rotating left the bits of , of since is obtained by circular left shift of by bits. The computation of thus levels followed by a CPA stage with needs a CSA of EAC to nally obtain the mixed radix digit . In the case of the second moduli set, needs to be computed to obis somewhat tain the mixed radix digit. The evaluation of involved. Once again, we employ the periodic properties of powers of two to perform this computation. Here all the positive terms in result in left shifted values bits which, evidently have two elds of of at most bits. All the lower -bit words can be added together whereas for the higher -bit words, ones needs to be complements of those with respect to added together with a correction term of corresponding to as explained before. each positive term in On the other hand, in the case of the term in the expression [see (7)], the LSB word ( -bit length) of the 1-bit leftfor value needs to be ones complemented with respect shifted and added with a correction term of 3 whereas the to MSB word can be added straightaway. The correction term over . As before, these words can be added all is -bit CSA of levels with each carry bit using a at each level necessitating a further correction term to be added. All the correction terms can be added as a single word at the last level of the CSA in another level. A modulo subtraction, at most thrice, needs to be carried out at the end to evaluate . : We next consider computing using Evaluation of (3) where separately for both the moduli sets due to the minor differences. We observe that can be realized as the two terms and ones complement of and 1.

(5a) and

(5b) is -bit wide, whereas is only -bit Note that -bit words since wide. Hence, the calculation is done as can some times be , a -bit word. This four operand addition can be performed by a CSA comprising of two levels. It may be noted that two carry bits may arise from the two levels of carry save addition, each of which corresponds to an . Thus, adding these addition of

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Expressing and as , , the three -bit and words to be added (excluding 1 to be added) are as shown in the rst equation at the bottom of the page, where the primes indicate inverted bits. However, noting that there are zeroes in and together, only all the bit positions considering -bit words need to be added with a carry-in bit 1 two (needed due to the twos complement operation of ). The resulting words are as shown in the second equation at the bottom of the page. bits of one of the operands are 1. We note further that Note that since MRC is used, there is no need for any modulo reduction. in the case of the second moduli The computation of is a -bit word. set is slightly different since Note that can be realized as the two terms and ones complement of and 1. Expressing as , the three words to be added (excluding 1 to be added) are as shown in the third equation at the bottom of the page. Noting that there are zeroes in all the bit positions, considand together, only two -bit words need ering to be added with a carry-in bit 1 (needed due to the twos complement operation of ), as shown in the last equation at the bottom of the page. bits of one of the operands are one. Since Note further that MRC is used, there is no need for any modulo reduction. We consider next two examples to illustrate the proposed conversion techniques.

and given Example 1: Consider the RNS . The decoded number shall be 10257. residues Step 1) Using Piestrak/Dhurkadas conversion technique on corresponding to residue set the RNS , we obtain the binary number . . This in binary form is Step 2) MRC is used for the moduli set and residue set . Note that . In order to nd , , ones complements add to , viz., , of the three 5-bit elds of , , using CSA with EAC to obtain . The sufx 2 indicates that they are binary numbers. with . Step 3) We need to multiply According to (6), this value is realized as . is realTherefore, appropriately to obtain the ized by rotating and and adding them two words to obtain as the mixed radix digit. Step 4) In this step, we multiply the mixed radix digit 2 oband add to the 8-bit tained with of , viz., , MSB word yielding the MSBs of the decoded word . It may be veried that the deas decoded word is sired. Example 2: Consider the moduli system and given residues . The decoded number shall

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be

. Step 1) Using Piestrak/Dhurkadas conversion techcorresponding to nique on the RNS residue set , we obtain the binary . This in binary form is number . Therefore, , , and . Step 2) MRC is used for the moduli set and (since ). residue set , we have to In order to nd . compute The bit level implementation is as follows:

Step 4) In this step, we multiply the mixed radix digit obtained with and add to the MSBs of excluding the 5 LSBs i.e 320, yielding the MSBs of the decoded word as . This means that the decoded number as desired. is IV. ESTIMATION OF AREA AND DELAY REQUIREMENTS OF THE PROPOSED CONVERTERS The architectures of the two converters for the two moduli sets are presented in Figs. 2 and 3, respectively. The area and delay requirements of both these architectures are evaluated in this section. We rst consider the converter shown in Fig. 2 for the rst moduli set. The RNS to binary converter block shown at the top . The modulo corresponds to the moduli set subtractor evaluating needing four -bit operand addition requires 3n inverters, -bit CSAs, CSA1 and CSA2 followed by a two levels of CPA with EAC, CPA1. Next, the multiplication of the result with to obtain needs addition of words formed by rotating the bits of , using a -bit CSA chain with end-around carry CSA3 followed by a CPA, CPA2, to obtain . The last CPA, CPA3, computes . Simplication of this adder is possible because there are 1 bits in one of the words to be added. The total area requirement and conversion time of this converter are presented in row 1 of Table I and the details of each block in the converter of Fig. 2 are shown in Table II. The area and delay requirements of the architecture in Fig. 3 are next evaluated. The area and conversion time requirements for the RNS to binary converter corresponding to the moduli set are as before in the case of the converter for subtractor evaluating the rst moduli set. The modulo needing ve -bit operand inverters, three levels of -bit addition requires carry-save-adder CSA4, CSA5 and CSA6 followed by a CPA, 2:1 Multiplexers to perform CPA4. This CPA needs the modulo addition. Next, the multiplication of the with needs addition of result words including the correction term, thus needing n levels of -bit CSA chain CSA7 followed by a CPA, CPA5 to obtain . The value of is computed next by using CPA6. This can be simplied because there are 1 bits in one of the words to be added. The total area requirement and conversion time of this converter are presented in row 3 of Table I and the details of each block in the converter of Fig. 3 are shown in Table III. V. COMPARISON WITH EARLIER DESIGNS OF CONVERTERS FOR BOTH THE MODULI SETS It is relevant to compare the area and delay requirements of the proposed converters with those proposed in literature.

Step 3) Step 3: We need to multiply with . The value according to (7). Thus, . The bit level implementation is as follows:

The underlined words need to be added (with one MSB zero appended) to the ones complements of the remaining with respect to 127 (with one MSB appended appropriately when the word length is bits only)

These are added next as follows:

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Fig. 2. Architecture of RNS to binary converter for the moduli set ; ; . ;

1 2 2 +1 2

0 1g

f2 0

A. Comparison with Vinod et al. Converter for the Moduli Set The converter for the four moduli set when n is even, due to Vinod et al. [34] is considered for comparison rst. The conversion algorithm proposed , and therein is based on CRT. Denoting , , dening and , the multiplicative inverses, viz., and are easily evalu, and are ated whereas involved. This is mainly because of division by a constant, 3.

1 2 2 +1 2

Fig. 3. Architecture of RNS to binary converter for the moduli set ; ; ; .

+ 1g

f2 0

The evaluation of the integer as

to be decoded can be expressed

(8)

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TABLE I AREA AND CONVERSION TIME COMPARISON OF VARIOUS CONVERTERS FOR FOUR MODULI SETS

The two major steps are the determination of and . In this evaluation, one encounters division by 2 and this can pose a problem when the dividend is odd. This is over come by using a technique called fraction compensation. In the implerequires mentation of the converter, the computation of 3 adder stages (see[34, Fig. 1]), adder 1 ( -bit), adder 4 -bit), and the subtractor 1 ( -bit) all operate in parallel. ( -bit), adder 3 The second stage comprises of adder 2 ( -bit) and subtractor 2 ( -bit) which operate in par( -bit modulo adder. The evaluation allel. The last stage is a needs a -bit subtractor, a -bit subtractor, a of -bit adder and a -bit modulo subtractor. It is clear that and can be computed in parallel. The delay both needed for the computation of is and for is . In the computation the computation of , a -bit binary comparator is needed to compare of with . Division by 3 is performed using XOR circuits and bit masking. The nal evaluation of from and needs a -bit adder and a -bit subtractor. The total area requirement and conversion time of this converter are given in row 2 of Table I. The calculation of Vinod et al. [34] assumed that -bit modulo adders are realized using n full-adders. Evidently, for the new design proposed for this moduli set in Section III, the conversion time is smaller for all than Vinod et al. design. n and the area is smaller for B. Comparison with Bhardwaj et al. Converter for the Moduli Set We next consider the converter due to Bhardwaj et al. [33] in which the RNS to binary conversion is performed in two and steps. The rst step consists of evaluating the residues of the desired binary word E corresponding to the moduli set using the following expressions reproduced here for convenience: (9a) (9b) needs 4-input CSA of -bit words with The evaluation of full-adders folend-around carry thus needing two levels of full-adders which needs to perform lowed by another row of

reduction also, amounting totally to . modulo We are assuming that no specialized modulo adders as in [41] are employed but conventional binary adder designs are employed. Note that Bhardwaj et al. [33] assumed that there is no need for a CPA to perform modulo reduction and the delay to . Next, the evaluation of needs two input -bit be . The delay for calculation modulo adder needing is much more than that of and is , of since end-around-carry amounts to two cascaded -bit addimost tions [12]. The second step of evaluating the nal signicant bits is recommended by Bhardwaj et al. [33] to be carried out using CRT on these two residues which involved ROM table look ups and a modied division algorithm (MDA). Bharadwaj et al. suggested evaluation of to take advantage of and minimum powers of two terms in (three bits and two bits respectively), where and . Note, however that, the correct expressions for and , are as follows:

which were interchanged therein. Moreover, and need to be computed. Instead, we suggest a direct calculation of . Evidently, the calculation needs addition of ve weighted terms of of and four weighted terms of , thus needing seven levels -bit of CSA followed by a CPA yielding at most a word. This can be veried by substituting the maximum posand , viz., and . Since many sible values for bits in these nine terms are zero, the hardware needed to perform the carry save addition can be reduced roughly to from . This includes the requirement of the nal . Division of this CPA. The delay of this block is value by 3 yields . This array divider needs one 2-bit sublevels and needs cycles to tractor in obtain the quotient and hence is slow due to its ripple-like structure [42], [43]. where The next step is the reduction . Bhardwaj et al. sug-

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TABLE II AREA AND TIME REQUIREMENTS OF VARIOUS MODULES IN THE CONVERTER FOR MODULI SET

f2 0 1 2 2 + 1 2
; ; ;

0 1g

TABLE III AREA AND TIME REQUIREMENTS OF VARIOUS MODULES IN THE CONVERTER FOR MODULI SET

f2 0 1 2 2 + 1 2
; ; ;

+ 1g

gested using the modied division algorithm which needs com) followed by putation of and then evaluation of ( bits. Note that the estimation of needs a ROM needing bits obaddition of four numbers of maximum length tained by truncation of . The area needed is where two levels of CSA are followed by a CPA. There can be some possible reduction since some operands have less than bits. The computation time of is . The weighting of L which has only four non-zero bits (two of which are negative), with yields four partial products which need to using a CSA followed by a CPA. Howbe subtracted from ever, many bits in these partial products are zero thus facilitating . area reduction. The area needed at most is thus . The delay of this block is needs a nal adder of area Finally, the addition of and delay of . Our estimates are reasonable and based on the various building blocks used in the architecture of Bhardwaj et al. where the authors have given in terms of height and width in terms of the virtual grid. The total area requirement and conversion time of this con-

verter are given in row 4 of Table I. Note that Bhardwaj et al. , since they have not concalculated the delay as and the delay sidered the CPAs needed to compute , needed to perform the division by 3. It is thus seen that the new design proposed for this moduli set in Section III is better in . both the area as well as conversion time for Modications of Bhardwaj et al. Technique: We suggest a and . modication for computing the nal result from This is based on MRC. Note that in the method described in Section III, we have considered the new moduli set for MRC whereas here we consider the moduli . The desired number corresponding to set the residues and can be written as

(10) Thus, of ones complement of can be obtained by the addition in an adder with end-around

with

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carry. The area needed is and the delay is . Next, can be expressed in the multiplicative inverse closed form avoiding division by 3. This will have bits which are one

The multiplication of the multiplicative inverse with needs the addition of n partial products which need to be added in a CSA with EAC followed by a carry adder. Thus, the area needed is propagate modulo . The delay is . The next step needs the weighting of this result by and addition which needs a two-operand adder needing with and an addition time of . Thus, the whereas the area total delay of the converter is needed is . Thus, the area needed for the modied Bhardwaj et al. design is less for while the conversion time is always less than Bhardwaj et al. design [33]. It is possible to reduce the area of full-adders needed by re-bit modulo multiplier in the case of the rst alizing the -bit modulo multiplier in the second moduli set and case (shown within dotted lines in Figs. 2 and 3) with ROMs bits and bits respectively. This of results in the reduction of the reverse conversion time as well. These cases are also included in Tables I and II and III. (The components indicated with Asterisks in Tables II and III need to be replaced by the ROMs). Evidently, the hardware needed and conversion times are much less than the corresponding designs available in literature [33], [34]. VI. CONCLUSION In this paper, two converters for the two recently proposed and moduli sets have been proposed. These have been derived based on MRC in the two moduli set comprising of and respectively. This choice was because of the fact that several optimized conare availverters for the three moduli set able in literature. The division-by-three operation occurring in the conversion procedures described in the previous works has been overcome by using closed form expressions for the various multiplicative inverses. This, of course, appears to lead to several powers of two terms in the multiplicand, hence involving more hardware with quadratic dependence on for performing the multiplication operations. Nevertheless, the hardware turns out to be economical than in previous methods. The conversion time also could be reduced. Designs which use ROM in place of the multipliers for both the proposed converters are also described which need much less combinational logic and less conversion time. We have also described a technique based on MRC to simplify the computations in Bhardwaj et al. technique. REFERENCES
[1] N. S. Szabo and R. I. Tanaka, Residue Arithmetic and Its Applications to Computer Technology. New-York: Mc-Graw Hill, 1967. [2] P. V. Ananda Mohan, Residue Number Systems: Algorithms and Architectures. New York: Kluwer Academic, 2002.

[3] M. A. Soderstrand, W. K. Jenkins, G. A. Jullien, and F. J. Taylor, Residue Number System Arithmetic: Modern Applications in Digital Signal Processing. New York: IEEE Press, 1986. [4] F. J. Taylor, Residue arithmetic: A tutorial with examples, IEEE Comput. Mag., vol. 17, pp. 5062, May 1984. [5] P. Bernardson, Fast memory-less over 64-bit, residue to binary converter, IEEE Trans. Circuits Syst., vol. CAS-32, no. 3, pp. 298300, Mar. 1985. [6] K. M. Ibrahim and S. N. Saloum, An efcient residue to binary converter design, IEEE Trans. Circuits Syst., vol. 35, no. 9, pp. 11561158, Sep. 1988. [7] G. Bi and E. V. Jones, Fast conversion between binary and residue numbers, Electron. Lett., vol. 24, pp. 11951197, Sep. 1988. [8] S. Andraros and H. Ahmad, A new efcient memory-less residue to binary converter, IEEE Trans. Circuits Syst., vol. 35, no. 11, pp. 14411444, Nov. 1988. [9] A. Dhurkadas, Comments on An efcient residue to binary converter design, IEEE Trans. Circuits Syst., vol. 37, no. 6, pp. 849850, Jun. 1990. [10] P. V. Ananda Mohan and D. V. Poornaiah, Novel RNS to binary converters, in Proc. Int. Symp. Circuits Syst., Singapore, 1991, pp. 15411544. [11] B. Vinnakota and V. V. B. Rao, Fast conversion techniques for binary to RNS, IEEE Trans. Circuits Syst. I, Fundam. Theory Appl., vol. 41, no. 9, pp. 927929, Sep. 1994. [12] S. J. Piestrak, A high- speed realisation of residue to binary system conversion, IEEE Trans. Circuits Syst. II, Analog Digit. Signal Process., vol. 42, no. 6, pp. 661663, Jun. 1995. [13] D. Gallaher, F. E. Petry, and P. Srinivasan, The digit parallel method for fast RNS to weighted number system conversion for specic moduli (2 1; 2 ; 2 + 1), IEEE Trans. Circuits Syst. II, Analog Digit. Signal Process., vol. 44, no. 1, pp. 5357, Jan. 1997. [14] P. V. Ananda Mohan, Evaluation of fast conversion techniques for binary-residue number systems, IEEE Trans. Circuits Syst. I, Fundam. Theory Appl., vol. 45, no. 11, pp. 11071109, Nov. 1998. [15] A. Dhurkadas, Comments on A high speed realisation of a residue to binary number system converter, IEEE Trans. Circuits Syst. II, Analog Digit. Signal Process., vol. 45, no. 4, pp. 446447, Apr. 1998. [16] M. Bhardwaj, A. B. Premkumar, and T. Srikanthan, Breaking the 2n-bit carry propagation barrier in residue to binary conversion for the [2 1; 2 ; 2 +1] moduli set, IEEE Trans. Circuits Syst. I, Fundam. Theory Appl., vol. 45, no. 9, pp. 9981002, Sep 1998. [17] R. Conway and J. Nelson, Fast converter for 3 moduli RNS using new property of CRT, IEEE Trans. Comput., vol. 48, pp. 852860, 1999. [18] Y. Wang, M. N. S. Swamy, and M. O. Ahmad, Residue to binary number converters for three moduli sets, IEEE Trans. Circuits Syst. II, Analog Digit. Signal Process., vol. 46, no. 2, pp. 180183, Feb. 1999. [19] P. V. Ananda Mohan, On the digit parallel method for fast RNS to weighted number system conversion for specic moduli 1; 2 ; 2 + 1), IEEE Trans. Circuits Syst. II, Analog Digit. (2 Signal Process., vol. 47, no. 9, pp. 972974, Sep. 2000. [20] Z. Wang, G. A. Jullien, and W. C. Miller, An improved residue to binary converter, IEEE Trans. Circuits Syst. I, Fundam. Theory Appl., vol. 47, no. 10, pp. 14371440, Oct. 2000. [21] P. V. Ananda Mohan, Comments on Breaking the 2n-bit carry prop1; 2 ; 2 + agation barrier in residue to binary conversion for the [2 1] moduli set, IEEE Trans. Circuits Syst. II, Analog Digit. Signal Process., vol. 48, no. 10, p. 1031, Oct. 2001. [22] Y. Wang, X. Song, M. Aboulhamid, and H. Shen, Adder based residue 1; 2 ; 2 + 1), IEEE Trans. to binary number converters for (2 Signal Process., vol. 50, no. 9, pp. 17721779, Sep. 2002. [23] W. Wang, M. N. S. Swamy, M. O. Ahmad, and Y. Wang, A study of the residue-to-binary converters for the three moduli sets, IEEE Trans. Circuits Syst. I, Fundam. Theory Appl., vol. 50, no. 2, pp. 235243, Feb. 2003. [24] A. A. Hiasat and H. S. Abdel-Aty-Zohdy, Residue to binary arithmetic 1; 2 1), IEEE Trans. Circonverter for the moduli set (2 ; 2 cuits Syst. II, Analog Digit. Signal Process., vol. 45, no. 2, pp. 204209, Feb. 1998. [25] W. Wang, M. N. S. Swamy, M. O. Ahmad, and Y. Wang, A high-speed 1; 2 1 residue-to-binary converter for thee moduli 2 ; 2 RNS and a scheme for its VLSI implementation, IEEE Trans. Circuits Syst. II, Analog Digit. Signal Process., vol. 47, no. 11, pp. 15761581, Nov. 2000. [26] W. Wang, M. N. S. Swamy, M. O. Ahmad, and Y. Wang, A note on A high-speed residue-to-binary converter for thee moduli 2 ; 2 1 RNS and a scheme for its VLSI implementation, IEEE 1; 2 Trans. Circuits Syst. II, Analog Digit. Signal Process., vol. 49, no. 3, p. 230, Mar. 2002.

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[27] A. B. Premkumar, An RNS to binary converter in 2n 1 , 2n , 2n + 1 moduli set, IEEE Trans. Circuits Syst. II, Analog Digit. Signal Process., vol. 39, no. 5, pp. 480482, May 1992. [28] A. B. Premkumar, M. Bhardwaj, and T. Srikanthan, High-speed and low-cost reverse converters for the ( 2n 1, 2n, 2n + 1) moduli set, IEEE Trans. Circuits Syst. II, Analog Digit. Signal Process., vol. 45, pp. 903908, 1998. [29] A. B. Premkumar, An RNS to binary converter in a three moduli set with common factors, IEEE Trans. Circuits Syst. II, Analog Digit. Signal Process., vol. 42, no. 3, pp. 298301, Mar. 1995. [30] Y. Wang, M. N. S. Swamy, and M. O. Ahmad, Residue to binary converters for three moduli sets, IEEE Trans. Circuits Syst. II, Analog Digit. Signal Process., vol. 46, no. 2, pp. 180183, Feb. 1999. [31] A. B. Premkumar, Corrections to An RNS to binary converter in a three moduli set with common factors, IEEE Trans. Circuits Syst. II, Exp. Briefs, vol. 51, no. 1, pp. 4347, Jan. 2004. [32] B. Cao, C. H. Chang, and T. Srikanthan, An efcient reverse converter 1; 2 ; 2 + 1; 2 + 1 base on the new for the 4-moduli set 2 Chinese Remainder Theorem, IEEE Trans. Circuits Syst. I, Fundam. Theory Appl., vol. 50, no. 7, pp. 12961303, Jul. 2003. [33] M. Bhardwaj, T. Srikanthan, and C. T. Clarke, A reverse converter for the 4 moduli super set 2 1; 2 ; 2 + 1 ; 2 + 1 , in IEEE Conf. Computer Arithmetic, Apr. 1999. [34] A. P. Vinod and A. B. Premkumar, A residue to binary converter for 1; 2 ; 2 + 1 ; 2 1 , J. Circuits the 4-moduli superset 2 Syst. Comput., vol. 10, pp. 8599, 2000. [35] M. H. Sheu, S. H. Lin, C. Chen, and S. W. Yang, An efcient VLSI design for a residue to binary converter for general balance moduli (2 3; 2 + 1 ; 2 1; 2 + 3), IEEE Trans. Circuits Syst. II, Exp. Briefs, vol. 51, no. 2, pp. 152155, Feb. 2004. [36] P. V. Ananda Mohan, Novel design for binary to RNS converters, in Proc. Int. Symp. Circuits Syst., London, U.K., 1994, pp. 357360. [37] , Efcient design of binary to RNS converters, J. Circuits Syst. Comput., vol. 9, pp. 145154, 1999. [38] S. J. Piestrak, Design of residue generators and multi-operand modulo adders using carry save adders, in Proc. 10th Symp. Comput. Arithmetic, Jun. 1991, pp. 100107. [39] A. B. Premkumar, A formal framework for conversion from binary to residue numbers, IEEE Trans. Circuits Syst. II, Analog Digit. Signal Process., vol. 49, no. 2, pp. 135144, Feb. 2002. [40] A. B. Premkumar, E. L. Ang, and E. M.-K. Lai, Improved memoryless RNS forward converter based on periodicity of residues, IEEE Trans. Circuits Syst. II, Exp. Briefs, vol. 53, no. 2, pp. 133137, Feb. 2006. [41] C. Efstathiou, D. Nikolos, and J. Kalanmatianos, Area-time efcient modulo 2 1 adder design, IEEE Trans. Circuits Syst. I, Fundam. Theory Appl., vol. 41, no. 4, pp. 463467, Apr. 1994. [42] Q. Tong and N. K. Jha, Design of C-testable DCVS binary array dividers, IEEE J. Solid-State Circuits, vol. 26, no. 2, pp. 134141, Apr. 1991. [43] T. Kutsuwa, M. Mun, and K. Ebata, Conguration and evaluation of 2s complement multiplication-division arrays, IEEE Trans. Circuits Syst., vol. CAS-34, no. 3, pp. 304308, Mar. 1987.

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P. V. Ananda Mohan (SM84F05) received the B.Sc and M.Sc (Tech.) degrees from Andhra University, Waltair. India, in 1965 and 1968, respectively, and the Ph.D degree in electrical communication engineering from Indian Institute of Science, Bangalore, in 1975. From 1973 till December 2003, he was with I.T.I. Limited working in R&D . From January 2004, he was with Electronics Corporation of India Limited, Bangalore as Advisor (Telecom) and in November 2004, he was appointed Executive Director (Technical). His research interests are in the area of Analog VLSI design, VLSI architectures, Cryptography. He has published in these areas in refereed international journals and conferences. He has co-authored the book Switched Capacitor Filters: Theory, Analysis and Design with Dr. M. N. S. Swamy and Dr. V. Ramachandran (Prentice-Hall, 1995), authored two more books Residue Number Systems: Algorithms and Architectures (Kluwer Academic, 2002) and CurrentMode VLSI Analog Filters: Design and Applications (Birkhauser, 2003). Dr. Mohan is a Fellow of IETE. He is the Chair of IEEE CAS Chapter, Bangalore. He was the Associate Editor of IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMSI: REGULAR PAPERS during 20002003. He is an Honorary Editor of IETE Technical Review (India). He taught Mixed Signal Design for few semesters at the Indian Institute of Science, Bangalore. He has received the Ram Lal Wadhwa Gold Medal Award from the Institution of Electronics and communication engineers (India) in 2003 and Indira Priyadarshini Award in 2004.

A. B. Premkumar (SM99) received the M. S. degree from North Dakota State University, Fargo, in 1985, and the Ph.D. degree from the University of Idaho, Moscow, in 1991, both in digital signal processing (DSP). He worked as a Senior Design Engineer in a large communication industry in India and was responsible for the design of low-speed data circuits, order wire and multiplexing equipments. In 1991, he joined the school of computer engineering, Nanyang Technological University (NTU), Singapore as a lecturer. From 1994 to 1995, he worked as a consultant to Garcia Enterprises, Sioux Falls, SD, where he was involved in the design of digital lters and digital communication systems. From 1995 to 1999, he worked as an Assistant Professor in the School of Computer Engineering, NTU, Singapore, where he is presently an Associate Professor. From 2001 to 2002, he was an Associate Professor in the department of Electrical and Computer Engineering, South Dakota School of Mines and Technology. His research interests include lter bank design and applications of DSP to wireless communications. He also works in the area of number theoretic transform for efcient implementation of DSP algorithms in VLSI designs.