DATAFLOW MODELLING library ieee; use ieee.std_logic_1164.

all; entity andgate is port (x,y:in bit; z:out bit); end andgate; architecture arch of andgate is begin z <= x and y; end arch; COMPARATOR library ieee; use ieee.std_logic_1164.all;

BINARY TO GREY CODE CONVERTOR library ieee; use ieee.std_logic_1164.all; entity b2g is port( b : in std_logic_vector(2 downto 0); g : out std_logic_vector(2 downto 0)); end b2g; architecture arch of b2g is begin g(2) <= b(2); g(1) <= b(2) xor b(1); g(0) <= b(1) xor b(0); end arch; CONDITIONAL SIGNAL ASSIGNMENT STATEMENT

entity Comparator is library ieee; generic(n: natural :=2); use ieee.std_logic_1164.all; port(A:in std_logic_vector(n-1 downto 0); B:in std_logic_vector(n-1 downto 0); entity mux is less : out std_logic; port (I : in bit_vector (3 downto 0); equal : out std_logic; S : in bit_vector (1 downto 0); greater : out std_logic Z : out bit); ); end mux; end Comparator; architecture arch of mux is architecture arch of Comparator is begin begin Z <= i(0) when s="00" else process(A,B) i(1) when s="01" else begin i(2) when s="10" else if (A<B) then i(3) when s="11" ; less <= '1'; end arch; equal <= '0'; greater <= '0'; SELECTED SIGNAL ASSIGNMENT STATEMENT elsif (A=B) then library ieee; less <= '0'; use ieee.std_logic_1164.all; equal <= '1'; entity mux is greater <= '0'; port (I : in bit_vector (3 downto 0); else S : in bit_vector (1 downto 0); less <= '0'; Z : out std_logic); equal <= '0'; end mux; greater <= '1'; end if; architecture arch of mux is end process; begin end arch; with s select Z <= i(0) when "00", i(1) when "01", i(2) when "10", i(3) when "11", unaffected when others ; end arch;

CASE STATEMENTS library ieee; use ieee.std_logic_1164.all; entity mux is port (I : in bit_vector (3 downto 0); S : in bit_vector (1 downto 0); Z : out bit); end mux; architecture arch of mux begin process(s,i) begin case s is when "00" => when "01" => when "10" => when "11" => end case; end process; end arch; TRANSPORT DELAY library ieee; use ieee.std_logic_1164.all; entity delay is port ( x:in bit; y:out bit); end delay; architecture arch of delay is constant pd:time:=5 ns; begin y <= transport x after pd; end arch; INERTIAL DELAY library ieee; use ieee.std_logic_1164.all; entity delay is port ( x:in bit; y:out bit); end delay; architecture arch of delay is begin y <= x after 10 ns; end arch; is

DECODER USING STRUCTURAL MODELLING library ieee; use ieee.std_logic_1164.all; entity decoder is port( en:in bit; a:in bit_vector(1 downto 0); z:out bit_vector(3 downto 0)); end decoder; architecture arch of decoder is component nand3 port(n1,n2,n3:in bit; nz:out bit); end component; component inv port(x1:in bit; xz:out bit); end component; signal abar,bbar:bit; begin i1:inv port map(a(1),abar); i2:inv port map(a(0),bbar); i3:nand3 port map (en,abar,bbar,z(3)); i4:nand3 port map (en,abar,a(0),z(2)); i5:nand3 port map (en,a(1),bbar,z(1)); i6:nand3 port map (en,a(1),a(0),z(0)); end arch; library ieee; use ieee.std_logic_1164.all; entity inv is port (x1 : in bit; xz : out bit); end inv; architecture arch of inv is begin xz<= not x1; end arch; library ieee; use ieee.std_logic_1164.all; entity nand3 is port(n1,n2,n3:in bit; nz:out bit); end nand3; architecture arch of nand3 is begin nz<= not(n1 and n2 and n3); end arch;

z<=i(0); z<=i(1); z<=i(2); z<=i(3);

INERTIAL DELAY library ieee; use ieee.std_logic_1164.all; entity delay is port ( x:in bit; y:out bit); end delay;

BLOCK STATEMENTS library ieee; use ieee.std_logic_1164.all; entity fadder is port( a,b,cin : in bit; sum,cout : out bit ); end fadder;

architecture arch of delay is architecture arch of fadder is begin signal s1,c1,c2:bit; y <= reject 4 ns inertial x after 10 ns ; end arch; begin FA1 : block D FLIP FLOP port (a1,b1 : in bit; fs1,fc1 : out bit); library ieee; port map( a1=> a,b1=>b,fs1=> use ieee.std_logic_1164.all; s1,fc1=> c1 ); begin entity dff is fs1<= a1 xor b1; port fc1 <= a1 and b1; ( d_in,clk : in bit; end block; d_out : out bit); end dff; FA2 : block port (a2,b2: in bit; architecture arch of dff is fs2,fc2: out bit); begin port map( a2=> s1,b2=>cin, fs2=> process (clk,d_in) sum,fc2 => c2 ); begin begin if (clk='1' and clk'event) then fs2<= a2 xor b2; d_out<=d_in after 1 fs; fc2 <= a2 and b2; end if; end block; end process; end arch; or2 : block port (r1,r2: in bit; BLOCK STATEMENTS rz: out bit); port map( r1=> c2,r2=>c1, rz=> library ieee; cout ); use ieee.std_logic_1164.all; begin rz <= r1 or r2; entity dff is end block; port( d,clk : in bit; end arch; q : out bit ); end dff; architecture arch of dff is begin b0:block (clk='1' and clk'event) begin q<= guarded d; end block ; end arch;

DIRECT INSTANTIATION library ieee; use ieee.std_logic_1164.all; entity hadder is port(a,b:in bit; s,c:out bit); end hadder; architecture struct of hadder is begin x1:entity work.xor2 port map(x1=>a,x2=>b,xz=>s); x2:entity work.and2 port map(a,b,c); end struct; library ieee; use ieee.std_logic_1164.all; entity and2 is port(l,m:in bit; n: out bit); end and2; architecture arch of and2 is begin n <= l and m; end arch; library ieee; use ieee.std_logic_1164.all; entity xor2 is port (x1,x2:in bit; xz:out bit); end xor2; architecture arch1 of xor2 is begin xz <= x1 xor x2; end arch1;

INCREMENTAL BINDING library ieee; use ieee.std_logic_1164.all; entity hadder is port(a,b : in bit; s,c : out bit); end hadder; architecture struct of hadder is component xor2 is port(p,q : in bit; r : out bit); end component; component and2 is port(a1,a2 : in bit; az : out bit); end component; --configuration specification for x1:xor2 use entity work.xorgate generic map(delay => 1 ns) port map(x1=>p,x2=>q,xz=> open) ; for a1:and2 use entity work.andgate port map(l => a1,m=> a2,n=> az); begin x1:xor2 port map(a,b,s); a1:and2 port map(a,b,c); end struct; configuration config of hadder is for struct for x1:xor2 generic map (delay =>2 ns) port map(xz => r); end for; end for; end config; GREY CODE TO BINARY library ieee; use ieee.std_logic_1164.all; entity g2b is port( g:in std_logic_vector(2 downto 0); b:out std_logic_vector(2 downto 0)); end g2b; architecture arch of g2b is begin b(2) <= g(2); b(1) <= g(2) xor g(1); b(0) <= g(2) xor g(1) xor g(0); end arch;

FACTORIAL USING LOOP STATEMENTS library ieee; use ieee.std_logic_1164.all; entity fact is port( x : in integer; y : out integer); end fact; architecture arch of fact is begin process (x) variable temp:integer:=1; begin for i in 1 to x loop temp := temp*i; end loop; y<=temp; end process; end arch; FULL ADDER USING MULTIPLE PROCESS library ieee; use ieee.std_logic_1164.all; entity fadder is port(a,b,cin : in std_logic; s,cout : out std_logic); end fadder; architecture arch of fadder is signal s1,s2,s3 : std_logic; begin process (a,b) begin s1 <= a xor b; s2 <= a and b; end process ; process (s1,cin) begin s <= s1 xor cin; s3 <= s1 and cin; end process; process (s2,s3) begin cout <= s3 or s2; end process; end arch;

JK FLIP FLOP library ieee; use ieee.std_logic_1164.all; entity jkff port (clk J, K reset Q end jkff; is : in std_logic; : in std_logic; : in std_logic; : inout std_logic );

architecture arch of jkff is signal input : std_logic_vector(1 downto 0); begin input <= J & K; p0: process(clk, reset) is begin if (reset='1') then q <= '0'; elsif (clk='1' and clk'event) then case input is when "11" => q <= not q; when "10" => q <= '1'; when "01" => q <= '0'; when others => null; end case; end if; end process; end arch;

N-INPUT ANDGATE USING GENERICS library ieee; use ieee.std_logic_1164.all; entity andgate is generic(n:integer:=5); port (x : in bit_vector(n-1 downto 0); z : out bit); end andgate; architecture arch of andgate is begin process (x) variable temp: bit ; begin temp := '1'; for k in 0 to n-1 loop temp := temp and x(k); exit when temp = '0'; end loop; z <= temp; end process; end arch; OPERATOR OVERLOADING library ieee; use ieee.std_logic_1164.all; entity andgate is port (x,y:in integer; z:out integer); end andgate; architecture arch of andgate is function "and" (signal s1,s2 : integer) return integer is begin return s1 + s2; end "and"; begin z <= x and y; end arch;

SR FLIP FLOP library ieee; use ieee.std_logic_1164.all; entity srff is port ( s,r, clk : in bit; q : out bit); end srff; architecture arch of srff is begin process (s,r,clk) begin if (clk='1' ) then assert not (s='1' and r ='1') report "invalid inputs" severity warning; if (s='0' and r='1') then q <= '0'; elsif (s='1' and r='0') then q <= '1'; else null; end if; end if; end process; end arch; FUNCTION library ieee; use ieee.std_logic_1164.all; entity pargen is port ( x : in std_logic_vector(3 downto 0); y : out std_logic); end pargen; architecture arch of pargen is function parity ( signal a : std_logic_vector(3 downto 0)) return std_logic is variable temp : std_logic := '0'; begin for i in 3 downto 0 loop temp := temp xor a(i); end loop; return temp;

RIPPLE CARRY ADDER USING GENERATE STATEMENTS library ieee; use ieee.std_logic_1164.all; entity radder4 is port( a,b : in bit_vector(3 downto 0); cin : in bit; cout : out bit; sum : out bit_vector(3 downto 0) ); end radder4; architecture arch of radder4 is component fadder is port ( p,q,r : in bit; t,s : out bit); end component; signal car : bit_vector(4 downto 0); begin car (0) <= cin; f1:for k in 3 downto 0 generate fa1: fadder port map (a(k),b(k),car(k),car(k+1),sum(k)); end generate; cout<= car(4); end arch; library ieee; use ieee.std_logic_1164.all; entity fadder is port( p,q,r : in bit; s,t : out bit); end fadder; architecture arch of fadder is begin s <= p xor q xor r ; t <= (p and q) or (r and (p xor q)) ; end arch;

end parity; begin y <= parity (x); end arch; PROCEDURE library ieee; use ieee.std_logic_1164.all; entity pargen is port ( x : in std_logic_vector(3 downto 0); y : out std_logic); end pargen; architecture arch of pargen is procedure parity ( signal a : in std_logic_vector(3 downto 0); signal b : out std_logic) is variable temp : std_logic := '0'; begin for i in 3 downto 0 loop temp := temp xor a(i); end loop; b <= temp; end parity; begin parity (x,y); end arch; CONFIGURATION HADDER.VHDL library ieee; use ieee.std_logic_1164.all; entity hadder is port(a,b : in bit; s,c : out bit); end hadder; architecture struct of hadder is component xorgate is port(x1,x2 : in bit; xz : out bit); end component; component andgate is port(l,m : in bit; n : out bit); end component;

RESOLUTION FUNCTION library ieee; use ieee.std_logic_1164.all; entity resolve is port ( a,b,c,d : in std_logic; z : out std_logic); end resolve; architecture arch of resolve is function wired_and (inputs: std_logic_vector ) return std_logic is variable temp : std_logic:='1'; begin for k in inputs'range loop temp := temp and inputs(k); end loop; return temp; end wired_and; signal rs : wired_and std_logic ; begin rs <= a and b; rs <= c and d; z <= not rs; end arch; CONFIGURATION SPECIFICATION library ieee; library work; use ieee.std_logic_1164.all; entity hadder is port(a,b:in bit; s,c:out bit); end hadder; architecture struct of hadder is component xor2 is port(x1,x2 : in bit; xz : out bit); end component; component and2 is port(a1,a2 : in bit; az : out bit); end component; --configuration specification

begin x1:xorgate port map(a,b,s); a1:andgate port map(a,b,c); end struct; configuration config of hadder is for struct for x1:xorgate use configuration work.xorconf; end for; for a1:andgate use entity work.andgate ; end for; end for; end config; ANDGATE.VHDL library ieee; use ieee.std_logic_1164.all; entity andgate is port(l,m:in bit; n: out bit); end andgate; architecture arch of andgate is begin n <= l and m; end arch; configuration andconf of andgate is for arch end for; end andconf; XORGATE.VHDL library ieee; use ieee.std_logic_1164.all; entity xorgate is port (x1,x2:in bit; xz:out bit); end xorgate; architecture arch1 of xorgate is begin xz <= x1 xor x2; end arch1; configuration xorconf of xorgate is for arch1 end for; end xorconf;

for x1:xor2 use entity work.xorgate; for a1:and2 use entity work.andgate port map(l => a1,m=> a2,n=> az); begin x1:xor2 port map(a,b,s); a1:and2 port map(a,b,c); end struct; library ieee; use ieee.std_logic_1164.all; entity andgate is port(l,m:in bit; n: out bit); end andgate; architecture arch of andgate is begin n <= l and m; end arch; library ieee; use ieee.std_logic_1164.all; entity xorgate is port (x1,x2:in bit; xz:out bit); end xorgate; architecture arch1 of xorgate is begin xz <= x1 xor x2; end arch1; 8*3 DECODER USING CASE STATEMENTS library ieee; use ieee.std_logic_1164.all; entity encoder is port(x: in std_logic_vector(7 downto 0); y: out std_logic_vector(2 downto 0)); end encoder; architecture arch of encoder is begin process(x) begin case x is when when when when

library ieee; use ieee.std_logic_1164.all; entity hadder_tb is end entity; architecture arch_tb of hadder_tb is component hadder is port (a,b: in bit; s,c:out bit); end component; signal tb_a,tb_b,tb_s,tb_c:bit; begin b1:hadder port map(tb_a,tb_b,tb_s,tb_c); tb_a <= '1' , '0' after 10 ns , '1' after 15 ns; tb_b <= '0' , '1' after 5 ns , '0' after 12 ns; end arch_tb; T FLIP FLOP library ieee; use ieee.std_logic_1164.all; entity tff is port ( pre,clr,clk,t : in std_logic; q : inout std_logic:='0'); end tff; architecture arch of tff is begin process (pre,clr,clk,t) begin if (pre='0' and clr='1') then q<='1'; elsif (pre='1' and clr='0') then q<='0'; elsif (pre='1' and clr='1') then if (clk ='1' and clk'event) then if (t='1') then q <= not q; else q <= q; end if; end if; end if;

"00000001" "00000010" "00000100" "00001000"

=> => => =>

y y y y

<= <= <= <=

"001"; "010"; "011"; "100";

end process; end arch;

when "00010000" => y <= "101"; when "00100000" => y <= "110"; when "01000000" => y <= "111"; when others => y <= "ZZZ"; end case; end process; end arch; TEST BENCH FOR 8*3 DECODER library ieee; use ieee.std_logic_1164.all; entity encoder_tb is end encoder_tb; architecture arch_tb of encoder_tb is

TEST BENCH FOR T FLIP FLOP library ieee; use ieee.std_logic_1164.all; entity tff_tb is end tff_tb; architecture arch_tb of tff_tb is signal tb_pre,tb_clr,tb_clk,tb_t : std_logic; signal tb_q : std_logic; component tff is port ( pre,clr,clk,t : in std_logic; q : inout std_logic); end component;

component encoder begin port(x:in std_logic_vector(7 downto 0); t0:tff port y:out std_logic_vector(2 downto 0)); map(tb_pre,tb_clr,tb_clk,tb_t,tb_q ); end component; tb_pre<='1' ,'0' after 9 ns ,'1' after signal tb_x:std_logic_vector(7 downto 0); 10 ns ; signal tb_y:std_logic_vector(2 downto 0); tb_clr <= '1'; begin e1: encoder port map (tb_x, tb_y); tb_clk <= '0' ,'1' after 5 ns , '0' after 10 ns ,'1' after 15 ns , '0' tb_x <= "00000000" , "00000001" after 5 after 20 ns ,'1' after 25 ns , '0' ns, "00000010" after 10 ns, "00000100" after 30 ns; after 15 ns, "00001000" after 20 ns, "00010000" after 25 ns, "00100000" after tb_t <= '0' ,'1' after 4 ns , '0' after 30 ns, "01000000" after 35 ns; 8 ns ,'1' after 12 ns , '0' after 16 ns ,'1' after 20 ns , '0' after 24 ns; end arch_tb; end arch_tb;