Vlsi A & B - 2011

VLSI Lab Manual
PART - A DIGITAL DESIGN ASIC-DIGITAL DESIGN FLOW

1. Write Verilog Code for the following circuits and their Test Bench for verification,
observe the waveform and synthesis the code with technological library with given Constraints*. Do the initial timing verification with gate level simulation. i. An inverter ii. A Buffer iii. Transmission Gate iv. Basic/universal gates v. Flip flop -RS, D, JK, MS, T vi. Serial & Parallel adder vii. 4-bit counter [Synchronous and Asynchronous counter] viii. Successive approximation register [SAR] * An appropriate constraint should be given
Dept. of ECE,Dr.SMCE,Nelamangala
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VLSI Lab Manual
(i) INVERTER
Logic Diagram input_i output_o Truth Table input_i 0 1 Program module inverter( input_i, output_o); input input_i; output reg output_o; always @ (input_i) begin if(input_i) output_o=1'b0; else output_o=1'b1; end endmodule Test Bench module inverter_tb; reg input_i; wire output_o; inverter dut (input_i, output_o); initial input_i=1'b0; always #5 input_i= ~ input_i; initial begin $monitor( $time, " input_i=%b and output_o=%b ", input_i,output_o); end endmodule output_o 1 0
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VLSI Lab Manual
(ii) BUFFER
Logic Diagram input_i output_o Truth Table input_i 0 1 Program module buffer( input_i, output_o); input input_i; output reg output_o; always @ (input_i) begin if(input_i) output_o=1'b1; else output_o=1'b0; end endmodule Test Bench module buffer_tb; reg input_i; wire output_o; buffer dut (input_i, output_o); initial input_i=1'b0; always #5 input_i=~ input_i; initial begin $monitor( $time, " input_i=%b and output_o=%b ", input_i,output_o); end endmodule output_o 0 1
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VLSI Lab Manual (iii) Transmission Gate control Truth Table control in out 0 1 1 in 1 0 1 out 0 0 1
control Program module transmission_gate (in, control, out); input in, control; output reg out; always @ (in) begin if(control) out=in; else out=1'b0; end endmodule Test Bench module transmission_gate_tb; reg in, control; wire out; transmission_gate u1(in, control, out); initial in=1'b1; always #5 in= ~in; initial begin #20 control=1'b1; #20 control=1'b0; end endmodule
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VLSI Lab Manual (iv) Basic/ Universal Gates. Logic gates

a
a
7 4 0 4 c = ~ a
7 4 0 8
d = a & b
a b 7 4 3 2
a
e = a ! b
7 4 0 0
f = ~ ( a & b )
a b 7 4 0 2
g = ~ ( a ! b )
7 4 8 6
h = a ^ b
Truth Table
Input a
0 0 1 1
NOT
AND
OR
NAND
NOR
XOR
b
0 1 0 1
c=~a d=a&b e=a|b f=~(a&b) g=~(a|b)

1 1 0 0 0 0 0 1 0 1 1 1 1 1 1 0 1 0 0 0
h=a^b
0 1 1 0
Program module basic_gates (a, b, c, d, e, f, g, h); input a, b; output c, d, e, f, g, h; assign c=~a; assign d=a&b;
Dept. of ECE,Dr.SMCE,Nelamangala Page 5
VLSI Lab Manual assign assign assign assign endmodule e=a|b; f=~(a&b); g=~(a|b); h=a^b;
Test Bench module basic_gates_tb; reg a, b; wire c, d, e, f, g, h; basic_gates uut (a, b, c, d, e, f, g, h); initial begin a=1'b0; b=1'b0; #20 a=1'b1; b=1'b0; #20 a=1'b0; b=1'b1; #20 a=1'b1; b=1'b1; end initial begin $monitor ($time, " a=%b b=%b (not_gate)c=%b (and_gate)d=%b (or_gate)e=%b (nand_gate)f=%b (nor_gate)g=%b (xor_gate)h=%b" ,a,b,c,d,e,f,g,h); end endmodule
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VLSI Lab Manual
(v) Flip Flop (a) RS-FF Block diagram Truth Table

clock r 0 0 s 0 1 0 1 x 1 0 z Hold q Hold 0 1 z qb
clock r
RS_ FF
qb
0
1 x
Program module rs_ff(rs, clock, q, qb); input [1:0] rs; input clock; output reg q, qb; always @ (posedge clock) begin case (rs) 2'b00 : q = q ; 2'b01 : q = 1'b1 ; 2'b10 : q = 1'b0 ; 2'b11 : q = 1'dZ ; endcase qb =~ q; end endmodule Test Bench
VLSI Lab Manual module rs_ff_tb; reg [1:0] sr; reg clock; wire q, qb; rs_ff uut(rs, clock, q, qb); initial clock=1'b1; always #5 clock=~clock; initial begin rs=2'b00; #20; rs =2'b01; #20; rs =2'b10; #20; rs =2'b11; #50; end initial $monitor ($time, "rs=%b q=%b qb=%b ", rs, q, qb); endmodule
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clock
d 1 0
q 1 0 X
qb 0 1 Hold
(b) D-FF Block diagram d q clock reset

D_ FF
Truth Table
qb
Program module dff (reset, clock, d, q, qb); input reset, clock, d; output q, qb; reg q; wire qb; always @ (posedge clock) begin if (reset) q<=1'b0; else q<=d; end assign qb=~q; endmodule Test Bench module dff_tb; reg clock, reset, d; wire q, qb;
VLSI Lab Manual dff uut (reset, clock, d, q, qb); initial begin clock=1'b1; reset=1'b0; end always #5 clock=~clock; always #40 reset=~reset; initial begin #20 d =1'b1; #20 d =1'b0; #30 d =1'b1; #30 d =1'b0; end initial begin $monitor ($time, "reset=%b clock=%b d=%b q=%b qb=%b", reset, clock, d, q, qb); end endmodule
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(c) JK-FF Block diagram J q Clock K

J K FF
Truth Table
Clk
J 0 0 1 1
K 0 1 0 1
q Hold 0 1
qb
qb
1 0 Toggle
Program module JK_FF (JK, clock, q, qb); input [1:0] JK; input clock; output reg q, qb; always @ (posedge clock) begin case (JK) 2'b00 : q = q; 2'b01 : q = 1'b0; 2'b10 : q = 1'b1; 2'b11 : q =~ q; endcase qb =~ q; end endmodule Test Bench module JK_ff_tb;
VLSI Lab Manual reg [1:0] JK; reg clock; wire q, qb; JK_FF uut(JK, clock, q, qb); initial clock=1'b1; always #5 clock=~clock; initial begin JK=2'b00; #20; JK=2'b01; #20; JK=2'b10; #20; JK=2'b11; #50; end initial $monitor ($time, "JK=%b q=%b qb=%b ", JK, q, qb); endmodule
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(d) Master Slave-FF {using D flip flop} Block diagram
Master
slave
d
d q
q w1
d q (d_ff) clock qb
clock
clock qb
(d_ff)
qb
Program (i) d_flip flop module d_ff (reset, clock, d, q, qb); input reset, clock, d; output q, qb; reg q; wire qb; always @ (posedge clock) begin if (reset) q<=1'b0; else q<=d; end assign qb=~q; endmodule
VLSI Lab Manual (ii) Master slave_flip flop module msflipflop (reset, clock, d,q, qb); input reset, clock, d; output q,qb; wire q; wire qb; wire w1,w2; d_ff master(.reset(reset), .clock(clock), .d(d), .q(w1), .qb(w2)); d_ff slave (.reset(reset), .clock(~clock),.d(w1),.q(q), .qb(qb)); endmodule Test Bench module ms_ff_tb; reg reset,clock,d; wire q,qb; msflipflop dut(reset,clock,d,q,qb); initial clock=1'b1; always #5 clock=~clock; initial begin reset=1'b1; d=1'b0; #40; reset=1'b1; d=1'b1; #40; reset=1'b0; d=1'b0; #40; reset=1'b0; d=1'b1; #40; reset=1'b0; d=0'b0; #40; reset=1'b0; d=1'b1; #40; end initial $monitor($time,"reset=%b d=%b q=%b qb=%b", reset, d, q, qb); endmodule
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(e) T-FF Block diagram T q clock

T_ FF cloc k T 0
Truth Table
qn-1 0 1 0 1 q 0 1 1 0 qb 1 0 0 1
qb
0 1 1
reset Program module t_ff (clock, reset, T, q); input clock, reset, T; output reg q; always @ (posedge clock) begin if(reset) q<=1'b0; else if (T) q<=~q; else q<=q; end endmodule Test Bench module t_ff_tb; reg clock, reset, T; wire q; t_ff dut(clock, reset, T, q); initial clock=1'b1; always #5 clock=~clock; initial begin
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VLSI Lab Manual reset=1'b1; T=1'b0; #20; reset=1'b1; T=1'b1; #20; reset=1'b0; T=1'b0; #20; reset=1'b0; T=1'b1; #20; end initial $monitor($time,"reset=%b T=%b q=%b",reset,T,q); endmodule (vi) Serial & Parallel Adder a) Parallel Adder i) Ripple Carry Adder [4bit] Block Diagram cout sum[3] sum[2] sum[1]
sum sum fa cin 3 carry w3 sum cin fa 2 carry w2 cin carry fa 1 w1 sum cin fa 0carry
sum[0]
cin
a b a b
b a b
a[3]
b[3]
a[2]
b[2]
a[1]
b[1]
a[0]
b[0]
Program (i) full_adder module full_adder (a, b, cin, sum, carry); input a, b, cin; output sum, carry; assign sum=a ^ b^ cin; assign carry= (a & b)| (b & cin) | (cin & a); endmodule (ii) 4bit_serial_full_adder module fa_serial_4bit (a, b, cin, sum, carry); input [3:0] a,b; input cin;
VLSI Lab Manual output [3:0] sum; output carry; wire [3:1] w; full_adder fa0(.a(a[0]),.b(b[0]),.cin(cin),.sum(sum[0]),.carry(w[1])); full_adder fa1(.a(a[1]),.b(b[1]),.cin(w[1]),.sum(sum[1]),.carry(w[2])); full_adder fa2(.a(a[2]),.b(b[2]),.cin(w[2]),.sum(sum[2]),.carry(w[3])); full_adder fa3(.a(a[3]),.b(b[3]),.cin(w[3]),.sum(sum[3]),.carry(carry)); endmodule Test Bench module fa_serial_4bit_tb; reg [3:0] a,b; reg cin; wire [3:0] sum; wire carry; fa_serial_4bit uu1 (a, b, cin, sum, carry); initial begin a=4'b0111; b=4'b0100; #10; a=4'b1011; b=4'b0110; end initial $monitor ($time, "a=%b b=%b cin=%b sum=%b carry=%b", a, b, cin, sum, carry); endmodule
cin=1'b0; cin=1'b1;
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ii) Carry Look-ahead Adder
Block diagram
Carry Generator
P(2) sum(2) g(2) P(1) sum(1) g(1) P(0) sum(0) g(0)
cout c(1) 1-Bit Adder 1-Bit Adder c(0) 1-Bit Adder cin
x(2)
y(2)
x(1)
y(1)
x(0)
y(0)
Program module paraller_adder (x, y,cin, sum, cout); input [2:0] x,y; input cin; output [2:0] sum; output cout; wire c0, c1; wire [2:0] p, g; assign g[0]= x[0] & y[0]; assign g[1]= x[1] & y[1]; assign g[2]= x[2] & y[2]; assign p[0]= x[0] | y[0]; assign p[1]= x[1] | y[1]; assign p[0]= x[2] | y[2]; assign c0= g[0] | (p[0] & cin); assign c1= g[1] | (p[1] & g[0]) | (p[1] & p[0] & cin);
VLSI Lab Manual
assign cout= g[2] | (p[2] & g[1]) | (p[2] & p[1] & g[0]) | (p[2] & p[1] & p[0] & cin); assign sum[0]= x[0] ^ y[0] ^ cin; assign sum[1]= x[1] ^ y[1] ^ (g[0] | (p[0] & cin)); assign sum[2]= x[2] ^ y[2] ^ (g[1] | (p[1] & g[0]) | (p[1] & p[0] & cin)); endmodule Test Bench module paraller_adder_tb; reg [2:0] x,y; reg cin; wire [2:0] sum; wire cout; paraller_adder uut (x, y,cin, sum, cout); initial begin x=3'b111; y=3'b100; cin=1'b0; #10; x=3'b101; y=3'b110; cin=1'b1; end initial $monitor ($time, " x=%b y=%b cin=%b sum=%b cout=%b" , x, y, cin, sum, cout); endmodule
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b.
Serial Adder A
qa[o]
sum
1 bit full adder B qb[o]
Initially=0
cout
Program for shift Register module shift_reg(data,load,E,w,clock,q); parameter n=8; input [n-1:0] data; input load,E,w,clock; output [n-1:0] q; reg [n-1:0] q; integer k; always @(posedge clock) if (load) q <= data; else if (E) begin for (k=n-1;k>0;k=k-1) q[k-1] <= q[k]; q[n-1] <= w; end endmodule Program for Serial Adder[8 bit] module serial_adder ( A, B, reset, clock, sum, cout); input [7:0] A, B;
VLSI Lab Manual input reset, clock; output [7:0] sum; output cout; reg [3:0] count; reg s,y,Y; wire [7:0] qa, qb, sum; wire run; parameter G=0, H=1; shift_reg shift_A (.data(A), .load(reset), .E(1'b1), .w(1'b0), .clock(clock), .q( qa)); shift_reg shift_B (.data(B), .load(reset), .E(1'b1), .w(1'b0), .clock(clock), .q( qb)); shift_reg shift_sum (.data(8'd0), .load(reset), .E( run),.w(s), .clock)clock),.q( sum)); //adder fsm //output and next state combinational circuit always @(qa or qb or y) case (y) G: begin s = qa[0]^qb[0]; if (qa[0] & qb[0]) Y = H; else Y = G; end H: begin s = qa[0] ~^qb[0]; if (~qa[0] & ~qb[0]) Y =G; else Y = H; end default : Y = G; endcase //sequential block always @(posedge clock) if (reset) y <= G; else y <= Y; assign cout=y; //control the shifting process always @(posedge clock) if (reset) count = 8; else if (run) count = count - 1; assign run=|count;
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Test Bench module serial_adder_tb ; reg [7:0] A,B; reg reset,clock; wire [7:0] sum ; serial_adder s1 (A, B, reset, clock, sum); initial clock = 1'b1; always #5 clock =~clock; initial begin reset = 1'b0;A = 8'b10101010; B = 8'b11111111; #20 reset = 1'b1; #20 reset = 1'b0; #80 $finish; end initial $monitor ($time, " SUM = %d cout=%b", sum, cout); endmodule
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VLSI Lab Manual
(vii) 4-bit counters [ Synchronous & Asynchronous] a) Synchronous counter. count[3] count[2] count[1] count[0]
clock
Synchronous Counter
clock
reset 1 0
current state xxx 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111
Next state 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 0000
Reset
up down Truth Table
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
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VLSI Lab Manual
Program module counter ( clock, reset, up, down, count); input clock, reset, up, down; output[3:0] count; reg [3:0] count; always @ (posedge clock) begin if(reset) count=4'b0000; else if (up && ~down) count= count+1'b1; else if (down && ~up) count= count-1'b1; else count=count; end endmodule Test Bench module counter_tb; reg clock, reset, up, down; wire [3:0]count; counter dut (clock, reset, up, down, count); initial clock=1'b0; always #5 clock=~clock; initial begin reset=1'b1; up=1'b0; down=1'b1;#50; reset=1'b0; up=1'b1; down=1'b0; #500; up=1'b0; down=1'b1; #500; up=1'b1; down=1'b1; #50; end
VLSI Lab Manual initial $monitor( $time, " reset=%b up=%b down=%b count=%b" ,reset, up, down, count); endmodule
b)
ASynchronous counter.
c o u n t [ 3 ]
c o u n t [ 2 ]
c o u n t [ 1 ]
c o u n t [ 0 ]
1
c l o c k
2
1
c l o c k
2
1
c l o c k
2
1
c l o c k
T4
T3
r e s e t
T2
T1
r e s e t
r e s e t
1
r e s e t
1 1
r e s e t
Program (i) T_Flip Flop module t_ff (clock, reset, T, q); input clock, reset, T; output reg q; always @ (posedge clock) begin if(reset) q<=1'b0; else if (T) q<=~q; else q<=q; end endmodule (ii) 4bit-counter module asyn_counter (clock, reset, count); input clock, reset; output [3:0] count; t_ff T1(.clock(clock), .reset(reset),.T(1'b1),.q( count[0])); t_ff T2(.clock(~count[0]), .reset(reset),.T(1'b1),.q( count[1]));
VLSI Lab Manual t_ff T3(.clock(~count[1]), .reset(reset),.T(1'b1),.q( count[2])); t_ff T4(.clock(~count[2]), .reset(reset),.T(1'b1),.q( count[3])); endmodule
Test Bench module asyn_counter_tb; reg clock, reset; wire [3:0] count; asyn_counter uut(clock, reset, count); initial clock=1'b0; always #10 clock=~clock; initial begin #20; reset=1'b1; #20; reset=1'b0; end initial $monitor( $time, " reset=%b count = %b" ,reset, count); endmodule
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Program module shift_reg(data,load,E,w,clock,q); parameter n=8; input [n-1:0] data; input load,E,w,clock; output [n-1:0] q; reg [n-1:0] q; integer k; always @(posedge clock) if (load) q <= data; else if (E) begin for (k=n-1;k>0;k=k-1) q[k-1] <= q[k]; q[n-1] <= w; end endmodule Test Bench module shift_reg_tb; reg [7:0] data; reg load; reg E; reg w; reg clock; wire [7:0] q; shift_reg dut(.data(data),.load(load),.E(E),.w(w),.clock(clock),.q(q)); initial clock=1'b1; always #5 clock = ~clock; initial begin load = 1'b1; w = 1'b0; E = 1'b0; #5 data = 8'b11110000;
VLSI Lab Manual #10 load = 1'b0; E = 1'b1; w = 1'b0; #10 w = 1'b0; #10 w = 1'b0; #10 w = 1'b0; #10 w = 1'b1; #10 w = 1'b1; #10 w = 1'b1; #10 w = 1'b1; end endmodule
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(vii) Successive approximation register [SAR] Flow chart Start
Enter the inputs
load =1?
Yes q=data
E= 1?
No
q(k1)=q(k) w=q(n-1)
end
Shifting operation w
MSB
LSB
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Program module sar (data,load,E,w,clock,q); parameter n=8; input [n-1:0] data; input load, E, w, clock; output [n-1:0] q; reg [n-1:0] q; integer k; always @(posedge clock) if (load) q <= data; else if (E) begin for (k=n-1;k>0;k=k-1) q[k-1] <= q[k]; q[n-1] <= w; end endmodule Test Bench module sar_tb; reg [7:0] data; reg load; reg E; reg w; reg clock; wire [7:0] q; sar dut(.data(data),.load(load),.E(E),.w(w),.clock(clock),.q(q)); initial clock=1'b1; always #5 clock = ~clock; initial begin load = 1'b1; w = 1'b0;
VLSI Lab Manual E = 1'b0; #5 data = 8'b11110000; #10 load = 1'b0; E = 1'b1; w = 1'b0; #10 w = 1'b0; #10 w = 1'b0; #10 w = 1'b0; #10 w = 1'b1; #10 w = 1'b1; #10 w = 1'b1; #10 w = 1'b1; end endmodule
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STEPS FOR SYNTHESIS Step 1. Open a terminal and type the following commands: [root@localhost ~]# csh [root@localhost ~]# source .cshrc Welcome to mentor graphics Tool brought to you by Tridents Tech Labs Pvt Ltd [root@localhost ~]# spectrum Messages will be logged to file '/root/leospec.log'... LeonardoSpectrum Level 3 - 2010a.7 (Release Production Release, compiled Jun 30 2010 at 15:05:46) Copyright 1990-2010 Mentor Graphics. All rights reserved. Portions copyright 1991-2010 Compuware Corporation Checking Security ... ** Welcome to Interactive Leonardo Spectrum Level 3 Version 2010a.7 *** News : * Enter "help" to get an overview of all commands * Enter <command> -help to get usage of each command Session history will be logged to file '/root/leospec.his' This will open the Leonardo Spectrum synthesis tool. Step 2. Loading the library: LEONARDO{1}: load_library /mgc_tree/design_data/libraries/tsmc018_typ.syn Reading library file `/mgc_tree/design_data/libraries/tsmc018_typ.syn`... Library version = v3.1 Release : Patch (a) : (Aug 26, 2005) Delays assume: Process=typical Temp= 0.0 C Voltage=1.80 V Info: setting encoding to auto Info, Command 'load_library' finished successfully Step 3. Reading the Verilog file to be synthesized: LEONARDO{2}: read -format verilog /root/prp/and_gate/rtl/and_gate.v -- Reading file '/root/prp/and_gate/rtl/and_gate.v'... -- Loading module 'and_gate' -- Compiling root module 'and_gate' Info, Command 'read' finished successfully
VLSI Lab Manual
Step 4. Using elaborate and optimize commands: LEONARDO{3}: elaborate -- Compiling root module 'and_gate' -- Info, replacing and_gate(INTERFACE) Info, Command 'elaborate' finished successfully LEONARDO{4}: optimize Info: The target technology was not selected, tsmc018_typ was automatically selected for you. NO wire table is found -- Optimizing netlist .work.and_gate.INTERFACE -- Automatic IO buffer insertion... WARNING: cannot do IO mapping. Library has no plain input IO buffer -- Matching combinational logic.. -- Matching non-combinational logic.. -- Covering.. -- CPU Time used : 00:00 Mapping -- Final Design Rule Check.. Info, Command 'optimize' finished successfully
Step 5. Viewing the reports( area & delay):
LEONARDO{5}: report_area ******************************************************* Cell: and_gate View: INTERFACE Library: work
******************************************************* Number of ports : 3 Number of nets : 3 Number of instances : 1 Number of references to this view :
Total accumulated area : Number of gates : 1 Number of accumulated instances : 1 Info, Command 'report_area' finished successfully
VLSI Lab Manual
LEONARDO{6}: report_delay NO wire table is found Critical Path Report Critical path #1, (unconstrained path) NAME GATE ARRIVAL LOAD -----------------------------------------------------------------------------a/ 0.00 0.00 dn 0.01 ix1/Y and02 0.06 0.06 dn 0.00 c/ 0.00 0.06 dn 0.00 data arrival time 0.06 data required time not specified -----------------------------------------------------------------------------data required time not specified data arrival time 0.06 ---------unconstrained path -----------------------------------------------------------------------------Critical path #2, (unconstrained path) NAME GATE ARRIVAL LOAD -----------------------------------------------------------------------------b/ 0.00 0.00 up 0.01 ix1/Y and02 0.05 0.05 dn 0.00 c/ 0.00 0.05 dn 0.00 data arrival time 0.05 data required time not specified -----------------------------------------------------------------------------data required time not specified data arrival time 0.05 ---------unconstrained path ----------------------------------------------------------------------------Info, Command 'report_delay' finished successfully
Step 6. Writing the synthesized file to the desired location: LEONARDO{7}: write -format verilog /root/prp/and_gate/syn/and_gate_syn.v -- Writing file /root/prp/and_gate/syn/and_gate_syn.v Info, Command 'write' finished successfully
VLSI Lab Manual LEONARDO{8}: exit
PART - B ANALOG DESIGN Analog Design Flow 1. Design an Inverter with given specifications*, completing the design flow mentioned below: a. Draw the schematic and verify the following i) DC Analysis ii) Transient Analysis b. Draw the Layout and verify the DRC, ERC c. Check for LVS d. Extract RC and back annotate the same and verify the Design e. Verify & Optimize for Time, Power and Area to the given constraint*** 2. Design the following circuits with given specifications*, completing the design flow mentioned below: a. Draw the schematic and verify the following i) DC Analysis ii) AC Analysis iii) Transient Analysis b. Draw the Layout and verify the DRC, ERC c. Check for LVS d. Extract RC and back annotate the same and verify the Design. i) A Single Stage differential amplifier ii) Common source and Common Drain amplifier 3. Design an op-amp with given specification* using given differential amplifier Common source and Common Drain amplifier in library** and completing the design flow mentioned below: a. Draw the schematic and verify the following i) DC Analysis ii). AC Analysis iii) Transient Analysis b. Draw the Layout and verify the DRC, ERC c. Check for LVS d. Extract RC and back annotate the same and verify the Design.
VLSI Lab Manual 4. Design a 4 bit R-2R based DAC for the given specification and completing the design flow mentioned using given op-amp in the library**. a. Draw the schematic and verify the following i) DC Analysis ii) AC Analysis iii) Transient Analysis b. Draw the Layout and verify the DRC, ERC c. Check for LVS d. Extract RC and back annotate the same and verify the Design.
5. For the SAR based ADC mentioned in the figure below draw the mixed signal schematic and verify the functionality by completing ASIC Design FLOW.
[Specifications to GDS-II] * Appropriate specification should be given.
** Applicable Library should be added & information should be given to the Designer. *** An appropriate constraint should be given
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Step 1: Invoking icstudio Open a terminal and type the following commands: csh (press enter) source .cshrc (press enter) welcome to mentor graphics message will be displayed, then type icstudio (press enter) this will open the icstudio interface.
Fig 1:Opening a terminal
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VLSI Lab Manual
Fig 2: icstudio Interface
Step 2:
Creating a new project
Click on File>New >Project from the menu bar. The new project setup wizard will open. Press Next to proceed with the wizard.
Enter the project name & choose its location & click on Next.
Click on Open library list editor tab to set the location map.
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VLSI Lab Manual Select Edit menu >Add MGC Design Kit. Browse for the my_kit installation directory in the specified location (/mgc_tree/design_data/cicd_spt_051007/cicd/data) Similarly select edit menu & then select Add Standard MGC Libraries. (The standard MCG Libraries will be automatically be added to the project once my kit has been added i.e. if the previous step is successfully completed )
After that press OK. This will return you back to the main menu wizard. Press Next to proceed. This will move to you on the Technology Settings. Press Open Setting Editor to set the technology setting.
Browse for the paths of the Process file, DRC, LVS, SDL and PEX rule files. For Process file the path is, /mgc_tree/design_data/cicd_spt_051007/my_kit/process For DRC the path is, /mgc_tree/design_data/cicd_spt_051007/my_kit/rule_deck/DRC For LVS the path is, /mgc_tree/design_data/cicd_spt_051007/my_kit/rule_deck/LVS For SDL the path is, /mgc_tree/design_data/cicd_spt_051007/my_kit/process/sdl_process_rules For PEX the path is, /mgc_tree/design_data/cicd_spt_051007/my_kit/rule_deck/PEX
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Press OK to return back to the main wizard. On pressing next a summary of all the previous steps will be shown.
Press finish to finalize. The icstudio interface will look like as shown below after creating the new project.
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Step 3:
Creating a Library
To create a library right click in the library area and select the New Library option. A window will pop-up asking for the library name.
Enter the library name and click on OK. The library will be added in the library area.
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Step 4:
Creating a Schematic Cell View
Select the library created and then right click in the cell area, and select the New Cell View option. Enter the cell name and the view type as Schematic.
On clicking on Finish the Schematic Editor window will open up. The schematic of the required circuit has to be created. For example, let us consider an inverter using CMOS technology.
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VLSI Lab Manual From the palette select Add Instance icon or hot key i can be used. Browse through the libraries added while creating the project, and select the required devices. An example of selecting nmos device is show below.
Palette
Workspace
Once the device has been selected move to the workspace and click to place the device. Press Esc once the device has placed. Similarly all the required devices including vdd, ground and ports are placed in the same manner.
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VLSI Lab Manual Selecting vdd is shown below.
Once all the devices have been placed they have to be connected using wires. A wire can be selected using the Wire Icon on the palette or hot key w. Click once to start drawing a wire and double click to end it.
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VLSI Lab Manual The connections are made as shown below. (Make sure the body terminal connections are also made).
To change the name of a particular net(wire), select the particular net and in the Object Editor change the Net Name to the desired name. Then click on Apply.
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The completed inverter design with the desired net names is shown below.
Next click on check/save option on the menu bar to check for any errors and also save the circuit design.
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A symbol for the design has to be created. Click on Tools> Generate Symbol. A window will pop-up as shown below. The name & Shape of the symbol can be selected as desired.
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VLSI Lab Manual On clicking on Ok the Symbol will be generated as shown below.
Step 5: Creating a Test Bench Under the library created in step 3 create a new cell. ( make sure the cell name is {module name}_tb.
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VLSI Lab Manual The required voltage sources, ports & connections are made as shown below. Make sure the cell under test is chosen correctly i.e. the cell created in step 4 has to be chosen.
Click on Check/Save & make sure there are no errors in the error report.
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VLSI Lab Manual Step 6. Simulating the Test Bench In the palette area click on the icon Enter Simulation Mode.
This will open up the simulation setup window as shown below.
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VLSI Lab Manual In the schematic sim palette click on Lib/Temp/Inc & select Libraries.The setup simulation window will open up as shown below. A new scenario has to be created. A scenario Name is chosen which is entered in the space provided and is added to the scenario list by clicking on the Add Scenario To List
To the scenario added a library file (lib.eldo) has to be included.To do this first highlight the scenario & click on browse tab & locate the lib.eldo file. ( /mgc_tree/design_data/cicd_spt_051007/cicd/data/my_kit/models/lib.eldo )
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Select TT (Typical Type) option under the lib.eldo library.
In
the schematic sim palette click on Lib/Temp/Inc & select Include Files option and delete the include_all file & click on Ok.
In the palette area click on Setup Sim session & select the Environment option. The Setup Simulation Environment window will open up. Select Netlist, Run Simulation and Display Waveforms & click on Ok.
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In the palette area click on Setup Analysis. The Setup Simulation window will popup. The desired analysis type (AC, DC, Transient) is selected.
For each of the analysis selected the corresponding parameters have to be set in the analysis set up window.
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VLSI Lab Manual An example of Transient & DC setup parameters are shown below.
In the palette area click on click on Wave Outputs icon. From the test bench schematic select the nets (wire) were the waveforms to be observed & add these nets to the object list.
Click on Run Simulator icon & observe the waveforms in EZwave tool. Waveform for Transient analysis of the Inverter is shown below.
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VLSI Lab Manual
Waveform for DC analysis of the Inverter is shown below.
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VLSI Lab Manual
COMMON SOURCE AMPLIFIER CS amplifier Schematic
CS amplifier Testbench schematic
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VLSI Lab Manual
Waveforms Transient analysis
AC analysis
VLSI Lab Manual
DC analysis
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VLSI Lab Manual
COMMON DRAIN AMPLIFIER CD amplifier schematic
CD amplifier testbench schematic

VLSI Lab Manual
AC analysis
VLSI Lab Manual
DC analysis
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VLSI Lab Manual
SINGLE STAGE DIFFERENTIAL AMPLIFIER Schematic
Testbench Schematic
VLSI Lab Manual
AC analysis
VLSI Lab Manual
DC analysis
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VLSI Lab Manual
OP-AMP Schematic
Testbench Schematic
VLSI Lab Manual
Waveforms
Transient analysis
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VLSI Lab Manual
AC analysis
DC analysis
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4 BIT R-2R BASED DAC
Schematic
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Testbench Schematic
Waveform
Transient analysis
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VLSI Lab Manual

PART - A DIGITAL DESIGN ASIC-DIGITAL DESIGN FLOW

VLSI Lab Manual

VLSI Lab Manual

VLSI Lab Manual (iv) Basic/ Universal Gates. Logic gates

c=~a d=a&b e=a|b f=~(a&b) g=~(a|b)

VLSI Lab Manual

(v) Flip Flop (a) RS-FF Block diagram Truth Table

VLSI Lab Manual

(b) D-FF Block diagram d q clock reset

VLSI Lab Manual

(c) JK-FF Block diagram J q Clock K

VLSI Lab Manual

(d) Master Slave-FF {using D flip flop} Block diagram

VLSI Lab Manual

(e) T-FF Block diagram T q clock

VLSI Lab Manual

ii) Carry Look-ahead Adder

VLSI Lab Manual

VLSI Lab Manual

1 bit full adder B qb[o]

VLSI Lab Manual

VLSI Lab Manual

up down Truth Table

VLSI Lab Manual

VLSI Lab Manual

VLSI Lab Manual

(vii) Successive approximation register [SAR] Flow chart Start

Enter the inputs

VLSI Lab Manual

VLSI Lab Manual

VLSI Lab Manual

Step 5. Viewing the reports( area & delay):

LEONARDO{5}: report_area ******************************************************* Cell: and_gate View: INTERFACE Library: work

VLSI Lab Manual

VLSI Lab Manual LEONARDO{8}: exit

[Specifications to GDS-II] * Appropriate specification should be given.

VLSI Lab Manual

Fig 1:Opening a terminal

VLSI Lab Manual

Fig 2: icstudio Interface

Creating a new project

VLSI Lab Manual

VLSI Lab Manual

VLSI Lab Manual

Creating a Schematic Cell View

VLSI Lab Manual Selecting vdd is shown below.

VLSI Lab Manual

VLSI Lab Manual

This will open up the simulation setup window as shown below.

VLSI Lab Manual

Select TT (Typical Type) option under the lib.eldo library.

VLSI Lab Manual

VLSI Lab Manual

Waveform for DC analysis of the Inverter is shown below.

VLSI Lab Manual

COMMON SOURCE AMPLIFIER CS amplifier Schematic

CS amplifier Testbench schematic

VLSI Lab Manual

Waveforms Transient analysis

VLSI Lab Manual

VLSI Lab Manual