Motorola: 24-Bit Digital Signal Processor

MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Order this document by: DSP56002/D, Rev. 3
DSP56002
24-BIT DIGITAL SIGNAL PROCESSOR
The DSP56002 is a MPU-style general purpose Digital Signal Processor (DSP) composed of an efficient 24-bit DSP core, program and data memories, various peripherals, and support circuitry. The DSP56000 core is fed by on-chip Program RAM, and two independent data RAMs. The DSP56002 contains a Serial Communication Interface (SCI), Synchronous Serial Interface (SSI), parallel Host Interface (HI), Timer/Event Counter, Phase Lock Loop (PLL), and an On-Chip Emulation (OnCE) port. This combination of features, illustrated in Figure 1, makes the DSP56002 a cost-effective, high-performance solution for high-precision general purpose digital signal processing.
15
16-bit Bus 24-bit Bus

Program Memory 512 24 RAM 64 24 ROM (boot) X Data Memory 256 24 RAM 256 24 ROM (A-law/ -law) Y Data Memory 256 24 RAM 256 24 ROM (sine)
24-bit Timer/ Event Counter
Sync. Serial (SSI) or I/O
Serial Comm. (SCI) or I/O
Host Interface (HI) or I/O
24-bit 56000 DSP Core

Internal Data Bus Switch OnCE Port PLL Clock Gen. 7 4
Address Generation Unit
PAB XAB YAB GDB PDB XDB YDB
External Address Bus Switch
Address 16
External Data Bus Switch
Data 24
Interrupt Control
Program Decode Controller
Program Address Generator
Data ALU 24 24 + 56 56-bit MAC Two 56-bit Accumulators
Bus Control
Control 10
Program Control Unit 3 IRQ AA0604
Figure 1 DSP56002 Block Diagram
1996 MOTOROLA, INC.
SECTION 1 SECTION 2 SECTION 3 SECTION 4 SECTION 5
PIN DESCRIPTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1 SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1 PACKAGING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1 DESIGN CONSIDERATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1 ORDERING INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1
FOR TECHNICAL ASSISTANCE:

Telephone: Email: Internet:
1 (800) 521-6274 dsphelp@dsp.sps.mot.com http://www.motorola-dsp.com
Data Sheet Conventions

This data sheet uses the following conventions:
OVERBAR asserted deasserted Examples: Used to indicate a signal that is active when pulled low (For example, the RESET pin is active when low.) Means that a high true (active high) signal is high or that a low true (active low) signal is low Means that a high true (active high) signal is low or that a low true (active low) signal is high Signal/Symbol PIN PIN PIN PIN
Note:
Logic State True False True False
Signal State Asserted Deasserted Asserted Deasserted
Voltage1 VIL/VOL VIH/VOH VIH/VOH VIL/VOL
Values for VIL, VOL, VIH, and VOH are defined by individual product specifications.
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DSP56002 Features
FEATURES
Digital Signal Processing Core

Efficient 24-bit DSP56000 core Up to 40 Million Instructions Per Second (MIPS), 25 ns instruction cycle at 80 MHz; up to 33 MIPS, 30.3 ns instruction cycle at 66 MHz Up to 240 Million Operations Per Second (MOPS) at 80 MHz; up to 198 MOPS at 66 MHz Performs a 1024-point complex Fast Fourier Transform (FFT) in 59,898 clocks Highly parallel instruction set with unique DSP addressing modes Two 56-bit accumulators including extension bits Parallel 24 24-bit multiply-accumulate in 1 instruction cycle (2 clock cycles) Double precision 48 48-bit multiply with 96-bit result in 6 instruction cycles 56-bit addition/subtraction in 1 instruction cycle Fractional and integer arithmetic with support for multiprecision arithmetic Hardware support for block-floating point FFT Hardware nested DO loops Zero-overhead fast interrupts (2 instruction cycles) Four 24-bit internal data buses and three 16-bit internal address buses for maximum information transfer on-chip
Memory
On-chip Harvard architecture permitting simultaneous accesses to program and two data memories 512 24-bit on-chip Program RAM and 64 24-bit bootstrap ROM Two 256 24-bit on-chip data RAMs Two 256 24-bit on-chip data ROMs containing sine, A-law, and -law tables External memory expansion with 16-bit address and 24-bit data buses Bootstrap loading from external data bus, Host Interface, or Serial Communications Interface
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DSP56002/D, Rev. 3
iii
Features
Peripheral and Support Circuits

Byte-wide host interface (HI) with Direct Memory Access (DMA) support (or fifteen Port B GPIO lines) SSI support: Supports serial devices with one or more industry-standard codecs, other DSPs, microprocessors, and Motorola-SPI-compliant peripherals Asynchronous or synchronous transmit and receive sections with separate or shared internal/external clocks and frame syncs Network mode using frame sync and up to 32 software-selectable time slots 8-bit, 12-bit, 16-bit, and 24-bit data word lengths
SCI for full duplex asynchronous communications (or three additional Port C GPIO lines) One 24-bit timer/event counter (or one additional GPIO line) Double-buffered peripherals Up to twenty-five General Purpose Input/Output (GPIO) pins One non-maskable and two maskable external interrupt/mode control pins On-Chip Emulation (OnCE) port for unobtrusive, processor speedindependent debugging Software-programmable, Phase Lock Loop-based (PLL) frequency synthesizer for the DSP core clock with a wide input frequency range (12.2 KHz to 80 MHz)
Miscellaneous Features
Power-saving Wait and Stop modes Fully static, HCMOS design for specified operating frequency down to dc Three packages available: 132-pin Plastic Quad Flat Pack (PQFP); 1.1 1.1 0.19 inches 144-pin Thin Quad Flat Pack (TQFP); 20 20 1.5 mm 132-pin Ceramic Pin Grid Array (PGA); 1.36 1.35 0.125 inches
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DSP56002 Product Documentation
PRODUCT DOCUMENTATION
The three documents listed in the following table are required for a complete description of the DSP56002 and are necessary to design properly with the part. Documentation is available from one of the following locations (see back cover for detailed information): A local Motorola distributor A Motorola semiconductor sales office A Motorola Literature Distribution Center The World Wide Web (WWW)
Table 1 DSP56002 Documentation

Name DSP56000 Family Manual DSP56002 Users Manual DSP56002 Technical Data Description Detailed description of the DSP56000 family processor core and instruction set Detailed functional description of the DSP56002 memory configuration, operation, and register programming DSP56002 features list and physical, electrical, timing, and package specifications Order Number DSP56KFAMUM/AD DSP56002UM/AD
DSP56002/D
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DSP56002/D, Rev. 3
Product Documentation
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SECTION
SIGNAL/PIN DESCRIPTIONS
INTRODUCTION
DSP56002 signals are organized into twelve functional groups, as summarized in Table 1-1. Table 1-1 Signal Functional Group Allocations
Functional Group Power (VCCX) Ground (GNDX) PLL and Clock Address Bus Data Bus Bus Control Interrupt and Mode Control Host Interface (HI) Port Serial Communications Interface (SCI) Port Synchronous Serial Interface (SSI) Port Timer/Event Counter or General Purpose Input/Output (GPIO) On-Chip Emulation (OnCE) Port
Note: 1. 2. 3.
Number of Signals 16 24 7 16 Port A1 24 10 4 Port B2 Port C3 15 3 6 1 4
Detailed Description Table 1-2 Table 1-3 Table 1-4 Table 1-5 Table 1-6 Table 1-7 Table 1-8 Table 1-9 Table 1-10 Table 1-11 Table 1-12 Table 1-13
Port A signals define the External Memory Interface port. Port B signals are the HI signals multiplexed on the external pins with the GPIO signals. Port C signals are the SCI and SSI signals multiplexed on the external pins with the GPIO signals.
Figure 1-1 is a diagram of DSP56002 signals by functional group.
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DSP56002/D, Rev. 3
1-1
Signal/Pin Descriptions Introduction
DSP56002
VCCP VCCCK VCCQ VCCA VCCD VCCC VCCH VCCS GNDP GNDCK GNDQ GNDA GNDD GNDC GNDH GNDS EXTAL XTAL CKOUT CKP PCAP PINIT PLOCK
4 3 3 2
Power Inputs: PLL Clock Output Internal Logic Address Bus Data Bus Bus Control HI SSI/SCI Grounds: PLL Clock Internal Logic Address Bus Data Bus Bus Control HI SSI/SCI
Interrupt Interrupt/ Mode Control MODA MODB MODC RESET IRQA IRQB NMI
Port B Host Interface (HI) Port1 8 3 H0H7 HA0HA2 HR/W HEN HREQ HACK PB0PB7 PB8PB10 PB11 PB12 PB13 PB14 Port C Serial Communications Interface (SCI) Port2 RXD TXD SCLK PC0 PC1 PC2
4 5 6 4 2
PLL and Clock
Synchronous Serial Interface (SSI) Port2 16 24 External Address Bus External Data Bus Timer/ Event Counter
SC0SC2 SCK SRD STD
PC3PC5 PC6 PC7 PC8
A0A15 D0D23 PS DS X/Y BS BR BG BN WT RD WR Note:
TIO
External Bus Control
Status OnCE Port DSCK DSI DSO DR OS1 OS0
1. The Host Interface port signals are multiplexed with the Port B GPIO signals (PB0PB15). 2. The SCI and SSI signals are multiplexed with the Port C GPIO signals (PC0PC8). 3. Power and Ground lines are indicated for the 144-pin TQFP package. AA1081G
Figure 1-1 Signals Identified by Functional Group
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DSP56002/D, Rev. 3
MOTOROLA
Signal/Pin Descriptions Power
POWER
Table 1-2 Power
Power Names VCCP Description Analog PLL Circuit PowerThis line is dedicated to the analog PLL circuits and must remain noise-free to ensure stable PLL frequency and performance. Ensure that the input voltage to this line is well-regulated and uses an extremely low impedance path to tie to the VCC power rail. Use a 0.1 F capacitor and a 0.01 F capacitor located as close as possible to the chip package to connect between the VCCP line and the GNDP line. Clock Output PowerThis line supplies a quiet power source for the CKOUT output. Ensure that the input voltage to this line is well-regulated and uses an extremely low impedance path to tie to the VCC power rail. Use a 0.1 F bypass capacitor located as close as possible to the chip package to connect between the VCCCK line and the GNDCK line. Oscillator PowerThese lines supply a quiet power source to the oscillator circuits and the mode control and interrupt lines. Ensure that the input voltage to this line is well-regulated and uses an extremely low impedance path to tie to the VCC power rail. Use a 0.1 F bypass capacitor located as close as possible to the chip package to connect between the VCCQ lines and the GNDQ lines. Address Bus PowerThese lines supply power to the address bus. Data Bus PowerThese lines supply power to the data bus. Bus Control PowerThis line supplies power to the bus control logic. Host Interface PowerThese lines supply power to the Host Interface logic. Serial Interface PowerThis line supplies power to the serial interface logic (SCI and SSI).
VCCCK
VCCQ (4)
VCCA (3) VCCD (3) VCCC VCCH (2) VCCS
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DSP56002/D, Rev. 3
1-3
Signal/Pin Descriptions Ground
GROUND
Table 1-3 Ground
Ground Names GNDP Description Analog PLL Circuit GroundThis line supplies a dedicated quiet ground connection for the analog PLL circuits and must remain relatively noise-free to ensure stable PLL frequency and performance. Ensure that this line connects through an extremely low impedance path to ground. Use a 0.1 F capacitor and a 0.01 F capacitor located as close as possible to the chip package to connect between the VCCP line and the GNDP line. Clock Output GroundThis line supplies a quiet ground connection for the CKOUT output. Ensure that this line connects through an extremely low impedance path to ground. Use a 0.1 F bypass capacitor located as close as possible to the chip package to connect between the VCCCK line and the GNDCK line. Oscillator GroundThese lines supply a quiet ground connection for the oscillator circuits and the mode control and interrupt lines. Ensure that this line connects through an extremely low impedance path to ground. Use a 0.1 F bypass capacitor located as close as possible to the chip package to connect between the VCCQ line and the GNDQ line. Address Bus GroundThese lines connect system ground to the address bus. Data Bus GroundThese lines connect system ground to the data bus. Bus Control GroundThis line connects ground to the bus control logic. Host Interface GroundThese lines supply ground connections for the Host Interface logic. Serial Interface GroundThese lines supply ground connections for the serial interface logic (SCI and SSI).
GNDCK
GNDQ (4)
GNDA (5) GNDD (6) GNDC GND (4) GNDS (2)
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DSP56002/D, Rev. 3
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Signal/Pin Descriptions PLL and Clock
PLL AND CLOCK

Table 1-4 PLL and Clock Signals
Signal Name EXTAL XTAL Signal Type Input Output State during Reset Input Chipdriven Chipdriven Signal Description External Clock/Crystal InputThis input connects the internal oscillator input to an external crystal or to an external oscillator. Crystal OutputThis output connects the internal crystal oscillator output to an external crystal. If an external oscillator is used, XTAL should be left unconnected. PLL Output ClockWhen the PLL is enabled and locked, this signal provides a 50% duty cycle output clock signal synchronized to the internal processor clock. When the PLL is enabled and the Multiplication Factor is less than or equal to 4, then CKOUT is synchronized to EXTAL. When the PLL is disabled, the output clock at CKOUT is derived from, and has the same frequency and duty cycle as, EXTAL. Note: CKP Input Input For information about using the PLL Multiplication Factor, see the DSP56002 Users Manual.
CKOUT
Output
PLL Output Clock Polarity ControlThe value of this signal at reset defines the polarity of the CKOUT output relative to EXTAL. If CKP is pulled low by connecting through a resistor to ground, CKOUT and EXTAL have the same polarity. Pulling CKP high by connecting it through a resistor to VCC causes CKOUT and EXTAL to be inverse polarities. The polarity of CKOUT is latched at the end of reset; therefore, any changes to CKP after deassertion of RESET do not affect CKOUT polarity. PLL CapacitorThis signal is used to connect the required external filter capacitor to the PLL filter. Connect one end of the capacitor to PCAP and the other to VCCP. The value of the capacitor is specified in Section 2 of this data sheet.
PCAP
Input/ Output
Indeterminate
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DSP56002/D, Rev. 3
1-5
Signal/Pin Descriptions PLL and Clock
Table 1-4 PLL and Clock Signals (Continued)

Signal Name PINIT Signal Type Input State during Reset Input Signal Description PLL Initialization SourceThe value of this signal at reset defines the value written into the PLL Enable (PEN) bit in the PLL control register. If PINIT is pulled high during reset, the PEN bit is written as a 1, enabling the PLL and causing the DSP internal clocks to be derived from the PLL VCO. If PINIT is pulled low during reset, the PEN bit is written as a 0, disabling the PLL and causing DSP internal clocks to be derived from the clock connected to EXTAL. PEN is written only at the deassertion of RESET and; therefore, the value of PINIT is ignored after that time. PLOCK Output Indeterminate Phase and Frequency LockThis output is generated by an internal Phase Detector circuit. This circuit drives the output high when: the PLL is disabled (the output clock is EXTAL and is therefore in phase with itself), or the PLL is enabled and is locked onto the proper phase (based on the CKP value) and frequency of EXTAL. The circuit drives the output low (deasserted) whenever the PLL is enabled, but has not locked onto the proper phase and frequency. Note: PLOCK is a reliable indicator of the PLL lock state only after the chip has exited the Reset state. During hardware reset, the PLOCK state is determined by PINIT and the current PLL lock condition.
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Signal/Pin Descriptions Address Bus
ADDRESS BUS
Table 1-5 Address Bus Signals
Signal Names A0A15 Signal Type Output State during Reset Signal Description
Tri-stated Address BusThese signals specify the address for external program and data memory accesses. If there is no external bus activity, A0A15 remain at their previous values to reduce power consumption. A0A15 are tri-stated when the bus grant signal is asserted.
DATA BUS
Table 1-6 Data Bus Signals
Signal Names D0D23 Signal Type Input/ Output State during Reset Signal Description
Tri-stated Data BusThese signals provide the bidirectional data bus for external program and data memory accesses. D0D23 are tristated when the BG or RESET signal is asserted.
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DSP56002/D, Rev. 3
1-7
Signal/Pin Descriptions Bus Control
BUS CONTROL
Table 1-7 Bus Control Signals
Signal Name PS Signal Type State during Reset Signal Description Program Memory SelectPS is asserted low for external program memory access. PS is tri-stated when the BG or RESET signal is asserted. Data Memory SelectDS is asserted low for external data memory access. DS is tri-stated when the BG or RESET signal is asserted. X/Y External Memory SelectThis output is driven low during external Y data memory accesses. It is also driven low during external exception vector fetches when operating in the Development mode. X/Y is tri-stated when the BG or RESET signal is asserted. Bus SelectBS is asserted when the DSP accesses the external bus, and it acts as an early indication of imminent external bus access by the DSP56002. It may also be used with the bus wait input WT to generate wait states. BS is pulled high when the BG or RESET signal is asserted. Bus RequestWhen the Bus Request input (BR) is asserted, it allows an external device, such as another processor or DMA controller, to become the master of the external address and data buses. While the bus is released, the DSP may continue internal operations using internal memory spaces. When BR is deasserted, the DSP56002 is the bus master.When BR is asserted, the DSP56002 will release Port A, including A0A15, D0D23, and the bus control signals (PS, DS, X/Y, RD, WR, and BS) by placing them in the high-impedance state after execution of the current instruction has been completed. Note: BG Output Pulled high To prevent erroneous operation, pull up the BR signal when it is not in use.
Output Tri-stated
DS X/Y
Output Tri-stated Output Tri-stated
BS
Output Pulled high
BR
Input
Input
Bus GrantWhen this output is asserted, it grants an external devices request for access to the external bus. This output is deasserted during hardware reset.
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Signal/Pin Descriptions Bus Control
Table 1-7 Bus Control Signals (Continued)

Signal Name BN Signal Type State during Reset Signal Description Bus Not RequiredThe BN signal is asserted whenever the chip requires mastership of the external bus. During instruction cycles where the external bus is not required, BN is deasserted. If the BN signal is asserted when the DSP is not the bus master, processing has stopped and the chip is waiting to acquire bus ownership. An external arbiter may use this signal to help determine when to return bus ownership to the DSP. Note: The BN signal cannot be used as an early indication of imminent external bus access because it is valid later than the other bus control signals BS and WT.
Output Pulled low
WT
Input
Input
Bus WaitAn external device may insert wait states by asserting WT during external bus cycles. Note: To prevent erroneous operation, pull up the WT signal when it is not in use.
WR RD
Output Tri-stated Output Tri-stated
Write EnableWR is asserted low during external memory write cycles. WR is tri-stated when the BG or RESET signal is asserted. Read EnableRD is asserted low during external memory read cycles. RD is tri-stated when the BG or RESET signal is asserted.
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DSP56002/D, Rev. 3
1-9
Signal/Pin Descriptions Interrupt and Mode Control
INTERRUPT AND MODE CONTROL

Table 1-8 Interrupt and Mode Control Signals
Signal Name MODA/IRQA Signal Type Input State during Reset Input Signal Description Mode Select A/External Interrupt Request AThis input has two functions: 1. to select the initial chip operating mode, and 2. after synchronization, to allow an external device to request a DSP interrupt.
MODA is read and internally latched in the DSP when the processor exits the Reset state. MODA, MODB, and MODC select the initial chip operating mode. Several clock cycles (depending on PLL stabilization time) after leaving the Reset state, the MODA signal changes to external interrupt request IRQA. The chip operating mode can be changed by software after reset. The IRQA input is a synchronized external interrupt request that indicates that an external device is requesting service. It may be programmed to be level-sensitive or negative-edge-sensitive. If level-sensitive triggering is selected, an external pull up resistor is required for wired-OR operation. If the processor is in the Stop state and IRQA is asserted, the processor will exit the Stop state. MODB/IRQB Input Input Mode Select B/External Interrupt Request BThis input has two functions: 1. to select the initial chip operating mode, and 2. after internal synchronization, to allow an external device to request a DSP interrupt.
MODB is read and internally latched in the DSP when the processor exits the Reset state. MODA, MODB, and MODC select the initial chip operating mode. Several clock cycles (depending on PLL stabilization time) after leaving the Reset state, the MODB signal changes to external interrupt request IRQB. After reset, the chip operating mode can be changed by software. The IRQB input is an external interrupt request that indicates that an external device is requesting service. It may be programmed to be level-sensitive or negative-edgetriggered. If level-sensitive triggering is selected, an external pull up resistor is required for wired-OR operation.
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Signal/Pin Descriptions Interrupt and Mode Control
Table 1-8 Interrupt and Mode Control Signals (Continued)

Signal Name MODC/NMI Signal Type Input State during Reset Input Signal Description Mode Select C/Non-maskable Interrupt RequestThis input has two functions: 1. to select the initial chip operating mode, and 2. after internal synchronization, to allow an external device to request a non-maskable DSP interrupt.
MODC is read and internally latched in the DSP when the processor exits the Reset state. MODA, MODB, and MODC select the initial chip operating mode. Several clock cycles (depending on PLL stabilization time) after leaving the Reset state, the MODC signal changes to the nonmaskable external interrupt request NMI. After reset, the chip operating mode can be changed by software. The NMI input is an external interrupt request that indicates that an external device is requesting service. It may be programmed to be level-sensitive or negative-edge-triggered. If level-sensitive triggering is selected, an external pull up resistor is required for wired-OR operation. RESET Input Input ResetThis input is a direct hardware reset on the processor. When RESET is asserted low, the DSP is initialized and placed in the Reset state. A Schmitt trigger input is used for noise immunity. When the RESET signal is deasserted, the initial chip operating mode is latched from the MODA, MODB, and MODC signals. The internal reset signal is deasserted synchronous with the internal clocks. In addition, the PINIT pin is sampled and written into the PEN bit of the PLL Control Register and the CKP pin is sampled to determine the polarity of the CKOUT signal.
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DSP56002/D, Rev. 3
1-11
Signal/Pin Descriptions Host Interface (HI) Port
HOST INTERFACE (HI) PORT

Table 1-9 HI Signals
Signal Name H0H7 Signal Type State during Reset Signal Description
Input Tri-stated Host Data Bus (H0H7)This data bus transfers data between or the host processor and the DSP56002. Output When configured as a Host Interface port, the H0H7signals are tri-stated as long as HEN is deasserted. The signals are inputs unless HR/W is high and HEN is asserted, in which case H0H7 become outputs, allowing the host processor to read the DSP56002 data. H0H7 become outputs when HACK is asserted during HREQ assertion. Port B GPIO 07 (PB0PB7)These signals are General Purpose I/O signals (PB0PB7) when the Host Interface is not selected. After reset, the default state for these signals is GPIO input.
PB0PB7
HA0HA2
Input
Tri-stated Host Address 0Host Address 2 (HA0HA2)These inputs provide the address selection for each Host Interface register. Port B GPIO 810 (PB8PB10)These signals are General Purpose I/O signals (PB8PB10) when the Host Interface is not selected. After reset, the default state for these signals is GPIO input.
PB8PB10
Input or Output
HR/W
Input
Tri-stated Host Read/WriteThis input selects the direction of data transfer for each host processor access. If HR/W is high and HEN is asserted, H0H7 are outputs and DSP data is transferred to the host processor. If HR/W is low and HEN is asserted, H0H7 are inputs and host data is transferred to the DSP. HR/W must be stable when HEN is asserted. Port B GPIO 11 (PB11)This signal is a General Purpose I/O signal called PB11 when the Host Interface is not being used. After reset, the default state for this signal is GPIO input.
PB11
Input or Output
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DSP56002/D, Rev. 3
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Signal/Pin Descriptions Host Interface (HI) Port
Table 1-9 HI Signals (Continued)

Signal Name HEN Signal Type Input State during Reset Signal Description
Tri-stated Host EnableThis input enables a data transfer on the host data bus. When HEN is asserted and HR/W is high, H0H7 become outputs and the host processor may read DSP56002/L002 data. When HEN is asserted and HR/W is low, H0H7 become inputs. Host data is latched inside the DSP on the rising edge of HEN. Normally, a chip select signal derived from host address decoding and an enable strobe are used to generate HEN. Port B GPIO 12 (PB12)This signal is a General Purpose I/O signal called PB12 when the Host Interface is not being used. After reset, the default state for this signal is GPIO input.
PB12
Input or Output
HREQ
Open Tri-stated Host RequestThis signal is used by the Host Interface to drain request service from the host processor, DMA controller, or a Output simple external controller. Note: HREQ should always be pulled high when it is not in use.
PB13
Input or Output
Port B GPIO 13 (PB13)This signal is a General Purpose (not open-drain) I/O signal (PB13) when the Host Interface is not selected. After reset, the default state for this signal is GPIO input.
HACK
Input
Tri-stated Host AcknowledgeThis input has two functions. It provides a host acknowledge handshake signal for DMA transfers and it receives a host interrupt acknowledge compatible with MC68000 family processors. Note: HACK should always be pulled high when it is not in use.
PB14
Input or Output
Port B GPIO 14 (PB14)This signal is a General Purpose I/O signal (PB14) when the Host Interface is not selected. After reset, the default state for this signal is GPIO input.
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DSP56002/D, Rev. 3
1-13
Signal/Pin Descriptions Serial Communications Interface Port
SERIAL COMMUNICATIONS INTERFACE PORT

Table 1-10 Serial Communications Interface (SCI+) Signals
Signal Name RXD Signal Type Input State during Reset Signal Description
Tri-stated Receive Data (RXD)This input receives byte-oriented data and transfers the data to the SCI receive shift register. Input data can be sampled on either the positive edge or on the negative edge of the receive clock, depending on how the SCI control register is programmed. Port C GPIO 0 (PC0)This signal is a GPIO signal called PC0 when the SCI RXD function is not being used. After reset, the default state is GPIO input.
PC0
Input or Output
TXD
Output Tri-stated Transmit Data (TXD)This output transmits serial data from the SCI transmit shift register. In the default configuration, the data changes on the positive clock edge and is valid on the negative clock edge. The user can reverse this clock polarity by programming the SCI control register appropriately. Input or Output Port C GPIO 1 (PC1)This signal is a GPIO signal called PC1 when the SCI TXD function is not being used. After reset, the default state is GPIO input.
PC1
SCLK
Input Tri-stated SCI Clock (SCLK)This signal provides an input or output or clock from which the receive or transmit baud rate is derived in Output the Asynchronous mode, and from which data is transferred in the Synchronous mode. The direction and function of the signal is defined by the RCM bit in the SCI+ Clock Control Register (SCCR). Port C GPIO 2 (PC2)This signal is a GPIO signal called PC2 when the SCI SCLK function is not being used. After reset, the default state is GPIO input.
PC2
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DSP56002/D, Rev. 3
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Signal/Pin Descriptions Synchronous Serial Interface Port
SYNCHRONOUS SERIAL INTERFACE PORT

Table 1-11 Synchronous Serial Interface (SSI) Signals
Signal Name SC0 Signal Type State during Reset Signal Description Serial Clock 0 (SC0)This signals function is determined by whether the SCLK is in Synchronous or Asynchronous mode. PC3 In Synchronous mode, this signal is used as a serial I/O flag. In Asynchronous mode, this signal receives clock I/O.
Input Trior stated Output
Port C GPIO 3 (PC3)This signal is a GPIO signal called PC3 when the SSI SC0 function is not being used. After reset, the default state is GPIO input.
SC1
Serial Clock 1 (SC1)The SSI uses this bidirectional signal to control flag or frame synchronization. This signals function is determined by whether the SCLK is in Synchronous or Asynchronous mode. In Asynchronous mode, this signal is frame sync I/O. For Synchronous mode with continuous clock, this signal is a serial I/O flag and operates like the SC0.
SC0 and SC1 are independent serial I/O flags but may be used together for multiple serial device selection. PC4 Port C GPIO 4 (PC4)This signal is a GPIO signal called PC4 when the SSI SC1 function is not being used. After reset, the default state is GPIO input. SC2 Input Trior stated Output Serial Clock 2 (SC2)The SSI uses this bidirectional signal to control frame synchronization only. As with SC0 and SC1, its function is defined by the SSI operating mode. Port C GPIO 5 (PC5)This signal is a GPIO signal called PC5 when the SSI SC1 function is not being used. After reset, the default state is GPIO input.
PC5
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Signal/Pin Descriptions Synchronous Serial Interface Port
Table 1-11 Synchronous Serial Interface (SSI) Signals (Continued)

Signal Name SCK Signal Type State during Reset Signal Description SSI Serial Receive ClockThis bidirectional signal provides the serial bit rate clock for the SSI when only one clock is being used. Port C GPIO 6 (PC6)This signal is a GPIO signal called PC6 when the SSI function is not being used. After reset, the default state is GPIO input. SRD Input Tristated SSI Receive DataThis input signal receives serial data and transfers the data to the SSI Receive Shift Register. Port C GPIO 7 (PC7)This signal is a GPIO signal called PC7 when the SSI SRD function is not being used. After reset, the default state is GPIO input. STD Output Tristated Input or Output SSI Transmit Data (STD)This output signal transmits serial data from the SSI Transmitter Shift Register. Port C GPIO 8 (PC8)This signal is a GPIO signal called PC8 when the SSI STD function is not being used. After reset, the default state is GPIO input.
PC6
PC7
Input or Output
PC8
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Signal/Pin Descriptions Timers
TIMERS
Table 1-12 Timer Signals
Signal Name TIO Signal Type State during Reset Signal Description Timer Input/OutputThe TIO signal provides an interface to the timer/event counter module. When the module functions as an external event counter or is used to measure external pulse width/ signal period, the TIO is an input. When the module functions as a timer, the TIO is an output, and the signal on the TIO signal is the timer pulse. When not used by the timer module, the TIO can be programmed through the Timer Control/Status Register (TCSR) to be a General Purpose I/O signal. TIO is effectively disconnected upon leaving reset.
MOTOROLA
DSP56002/D, Rev. 3
1-17
Signal/Pin Descriptions On-Chip Emulation Port
On-CHIP EMULATION PORT

Table 1-13 On-Chip Emulation (OnCE) Signals
Signal Name DSI/OS0 Signal Type Input or Output State during Reset Signal Description
Low Debug Serial Input/Chip Status 0Serial data or commands Output are provided to the OnCE controller through the DSI/OS0 signal when it is an input. The data received on the DSI signal will be recognized only when the DSP has entered the Debug mode of operation. Data is latched on the falling edge of the DSCK serial clock. Data is always shifted into the OnCE serial port Most Significant Bit (MSB) first. When the DSI/OS0 signal is an output, it works in conjunction with the OS1 signal to provide chip status information. The DSI/OS0 signal is an output when the processor is not in Debug mode. When switching from output to input, the signal is tri-stated. Note: Connect an external pull-down resistor to this signal.
DSCK/OS1
Input or Output
Low Debug Serial Clock/Chip Status 1The DSCK/OS1 signal Output supplies the serial clock to the OnCE when it is an input. The serial clock provides pulses required to shift data into and out of the OnCE serial port. (Data is clocked into the OnCE on the falling edge and is clocked out of the OnCE serial port on the rising edge.) The debug serial clock frequency must be no greater than 1/8 of the processor clock frequency. When switching from input to output, the signal is tri-stated. When it is an output, this signal works with the OS0 signal to provide information about the chip status. The DSCK/OS1 signal is an output when the chip is not in Debug mode. Note: Connect an external pull-down resistor to this signal.
1-18
DSP56002/D, Rev. 3
MOTOROLA
Table 1-13 On-Chip Emulation (OnCE) Signals (Continued)

Signal Name DSO Signal Type Output State during Reset Pulled high Signal Description Debug Serial OutputData contained in one of the OnCE controller registers is provided through the DSO output signal, as specified by the last command received from the external command controller. Data is always shifted out the OnCE serial port Most Significant Bit (MSB) first. Data is clocked out of the OnCE serial port on the rising edge of DSCK. The DSO signal also provides acknowledge pulses to the external command controller. When the chip enters the Debug mode, the DSO signal will be pulsed low to indicate (acknowledge) that the OnCE is waiting for commands. After the OnCE receives a read command, the DSO signal will be pulsed low to indicate that the requested data is available and the OnCE serial port is ready to receive clocks in order to deliver the data. After the OnCE receives a write command, the DSO signal will be pulsed low to indicate that the OnCE serial port is ready to receive the data to be written; after the data is written, another acknowledge pulse will be provided. Note: DR Input Input Connect an external pull-up resistor to this signal.
Debug RequestThe debug request input (DR) allows the user to enter the Debug mode of operation from the external command controller. When DR is asserted, it causes the DSP to finish the current instruction being executed, save the instruction pipeline information, enter the Debug mode, and wait for commands to be entered from the DSI line. While in Debug mode, the DR signal lets the user reset the OnCE controller by asserting it and deasserting it after receiving acknowledge. It may be necessary to reset the OnCE controller in cases where synchronization between the OnCE controller and external circuitry is lost. DR must be deasserted after the OnCE responds with an acknowledge on the DSO signal and before sending the first OnCE command. Asserting DR will cause the chip to exit the Stop or Wait state. Having DR asserted during the deassertion of RESET will cause the DSP to enter Debug mode. Note: Connect an external pull-up resistor to this signal.
MOTOROLA
DSP56002/D, Rev. 3
1-19
1-20
DSP56002/D, Rev. 3
MOTOROLA
SECTION
SPECIFICATIONS
GENERAL CHARACTERISTICS
The DSP56002 is fabricated in high-density HCMOS with TTL compatible inputs and outputs.
MAXIMUM RATINGS
CAUTION
This device contains circuitry protecting against damage due to high static voltage or electrical fields; however, normal precautions should be taken to avoid exceeding maximum voltage ratings. Reliability is enhanced if unused inputs are tied to an appropriate logic voltage level (e.g., either GND or VCC).
Note: In the calculation of timing requirements, adding a maximum value of one specification to a minimum value of another specification does not yield a reasonable sum. A maximum specification is calculated using a worst case variation of process parameter values in one direction. The minimum specification is calculated using the worst case for the same parameters in the opposite direction. Therefore, a maximum value for a specification will never occur in the same device that has a minimum value for another specification; adding a maximum to a minimum represents a condition that can never exist.
MOTOROLA
DSP56002/D, Rev. 3
2-1
Specifications Thermal characteristics
Table 2-1 Absolute Maximum Ratings (GND = 0 V)

Rating Supply Voltage All Input Voltages Current Drain per Pin excluding VCC and GND Operating Temperature Range Storage Temperature Symbol VCC VIN I TJ Tstg Value 0.3 to +7.0 (GND 0.5) to (VCC + 0.5) 10 40 to +105 55 to +150 Unit V V mA C C
THERMAL CHARACTERISTICS
Table 2-2 Thermal Characteristics
Characteristic Junction-to-ambient thermal resistance1 Junction-to-case thermal resistance2 Thermal characterization parameter
Notes: 1.
Symbol RJA or JA RJC or JC JT
PQFP Value3 50 12.4 4.0
TQFP Value3 48 10.8 0.16
TQFP Value4 40.6
PGA Value3 22 6.5 N/A
Unit
C/W C/W C/W
2. 3. 4.
Junction-to-ambient thermal resistance is based on measurements on a horizontal-single-sided Printed Circuit Board per SEMI G38-87 in natural convection.(SEMI is Semiconductor Equipment and Materials International, 805 East Middlefield Rd., Mountain View, CA 94043, (415) 964-5111) Measurements were made with the parts installed on thermal test boards meeting the specification EIA/JEDECSI-3. Junction-to-case thermal resistance is based on measurements using a cold plate per SEMI G30-88, with the exception that the cold plate temperature is used for the case temperature. These are measured values. See note 1 for test board conditions. These are measured values; testing is not complete. Values were measured on a non-standard fourlayer thermal test board (two internal planes) at one watt in a horizontal configuration.
2-2
DSP56002/D, Rev. 3
MOTOROLA
Specifications DC Electrical Characteristics
DC ELECTRICAL CHARACTERISTICS
Table 2-3 DC Electrical Characteristics
Characteristics Supply Voltage Input High Voltage EXTAL RESET MODA, MODB, MODC All other inputs Input Low Voltage EXTAL MODA, MODB, MODC All other inputs Input Leakage Current EXTAL, RESET, MODA/IRQA, MODB/IRQB, MODC/NMI, DR, BR, WT, CKP, PINIT, MCBG, MCBCLR, MCCLK, D20IN Tri-state (Offstate) Input Current (@ 2.4 V/0.4 V) Output High Voltage (IOH = 0.4 mA) Output Low Voltage (IOL = 3.0 mA) HREQ IOL = 6.7 mA, TXD IOL = 6.7 mA Internal Supply Current at 40 MHz1 In Wait mode2 In Stop mode2 Internal Supply Current at 66 MHz1 In Wait mode2 In Stop mode2 Internal Supply Current at 80 MHz1 In Wait mode2 In Stop mode2 PLL Supply Current3 40 MHz 66 MHz 80 MHz CKOUT Supply Current4 40 MHz 66 MHz 80 MHz Input Capacitance5
Notes: 1. 2. 3. 4. 5.
Symbol VCC VIHC VIHR VIHM VIH VILC VILM VIL IIN
Min 4.5 4.0 2.5 3.5 2.0 0.5 0.5 0.5 1
Typ 5.0
Max 5.5 VCC VCC VCC VCC 0.6 2.0 0.8 1
Units V V V V V V V V A
ITSI VOH VOL ICCI ICCW ICCS ICCI ICCW ICCS ICCI ICCW ICCS
10 2.4
90 12 2 95 15 2 115 18 2 1.0 1.1 1.2 14 28 34 10
10 0.4 105 20 95 130 25 95 160 30 95 1.5 1.5 1.8 20 35 42
A V V mA mA A mA mA A mA mA A mA mA mA mA mA mA pF
CIN
Section 4 Design Considerations describes how to calculate the external supply current.
In order to obtain these results all inputs must be terminated (i.e., not allowed to float). Values are given for PLL enabled. Values are given for CKOUT enabled. Periodically sampled and not 100% tested
MOTOROLA
DSP56002/D, Rev. 3
2-3
Specifications AC Electrical Characteristics
AC ELECTRICAL CHARACTERISTICS
The timing waveforms in the AC Electrical Characteristics are tested with a VIL maximum of 0.5 V and a VIH minimum of 2.4 V for all pins, except EXTAL, RESET, MODA, MODB, and MODC. These pins are tested using the input levels set forth in the DC Electrical Characteristics. AC timing specifications that are referenced to a device input signal are measured in production with respect to the 50% point of the respective input signals transition. DSP56002 output levels are measured with the production test machine VOL and VOH reference levels set at 0.8 V and 2.0 V, respectively.
Pulse Width VIH Input Signal Midpoint1 Fall Time Note: The midpoint is VIL + (VIH VIL)/2. VIL Rise Time Low High
90% 50% 10%
AA0179
Figure 2-1 Signal Measurement Reference
2-4
DSP56002/D, Rev. 3
MOTOROLA
Specifications Internal Clocks
INTERNAL CLOCKS
For each occurrence of TH, TL, TC or ICYC, substitute with the numbers in Table 2-4. DF and MF are PLL division and multiplication factors set in registers. Table 2-4 Internal Clocks
Characteristics Internal Operation Frequency Internal Clock High Period With PLL disabled With PLL enabled and MF 4 With PLL enabled and MF > 4 Internal Clock Low Period With PLL disabled With PLL enabled and MF 4 With PLL enabled and MF > 4 Internal Clock Cycle Time Instruction Cycle Time TC ICYC TL Symbol f TH ETH (Min) 0.48 TC (Max) 0.52 TC (Min) 0.467 TC (Max) 0.533 TC ETL (Min) 0.48 TC (Max) 0.52 TC (Min) 0.467 TC (Max) 0.533 TC ETC DF/MF 2 TC Expression
MOTOROLA
DSP56002/D, Rev. 3
2-5
Specifications External Clock (EXTAL Pin)
EXTERNAL CLOCK (EXTAL PIN)

The DSP56002 system clock may be derived from the on-chip crystal oscillator as shown in Figure 2-2, or it may be externally supplied. An externally supplied square wave voltage source should be connected to EXTAL, leaving XTAL physically unconnected to the board or socket. The rise and fall times of this external clock should be 4 ns maximum.
XTAL EXTAL R C1 XTAL1 C C L1 C2 XTAL1* C3 EXTAL R1 XTAL R2
Fundamental Frequency Crystal Oscillator Suggested Component Values R = 680 k 10% C = 20 pf 20%
3rd Overtone Crystal Oscillator Suggested Component Values R1 = 470 k 10% R2 = 330 10% C1 = 0.1 f 20% C2 = 26 pf 20% C3 = 20 pf 10% L1 = 2.37 H 10% XTAL = 40 MHz, AT cut, 20 pf load, 50 max series resistance Note: 1. *3rd overtone crystal. 2. The suggested crystal source is ICM, # 471163 - 40.00 (40 MHz 3rd overtone, 20 pf load). 3. R2 limits crystal current. 4. Reference Benjamin Parzen, The Design of Crystal and Other Harmonic Oscillators, John Wiley & Sons, 1983.
Note:
1. The suggested crystal source is ICM, # 433163 - 4.00 (4 MHz fundamental, 20 pf load) or # 436163 - 30.00 (30 MHz fundamental, 20 pf load). 2. To reduce system cost, a ceramic resonator may be used instead of the crystal. Suggested source: Murata-Erie #CST4.00MGW040 (4 MHz with built-in load capacitors)
AA0211
Figure 2-2 Crystal Oscillator Circuits
2-6
DSP56002/D, Rev. 3
MOTOROLA
Specifications External Clock (EXTAL Pin)
VIHC EXTAL ETH 1 3 ETC 4 NOTE: The midpoint is VILC + 0.5 (VIHC VILC).
AA0360
Midpoint VILC ETL 2
Figure 2-3 External Clock Timing
Table 2-5 Clock Operation

40 MHz Num Characteristics Frequency of Operation (EXTAL Pin) 1 Clock Input High With PLL disabled (46.7% 53.3% duty cycle) With PLL enabled (42.5% 57.5% duty cycle) Clock Input Low With PLL disabled (46.7% 53.3% duty cycle) With PLL enabled (42.5% 57.5% duty cycle) Clock Cycle Time With PLL disabled With PLL enabled Instruction Cycle Time = ICYC = 2TC With PLL disabled With PLL enabled Symbol Min Ef ETH 0 Max 40 Min 0 Max 66 Min 0 Max 80 MHz 66 MHz 80 MHz Unit
11.7
7.09
5.8 5.3
235.5 s ns
10.5 235.5 s 6.36 235.5 s
11.7 ETL
7.09
5.8 5.3
235.5 s ns
10.5 235.5 s 6.36 235.5 s
ETC
25 25
15.15 12.5 409.6 s 15.15 409.6 s 12.5 409.6 s
ns
ICYC
50 50
30.3 819.2 s 30.3 819.2 s
25 25
819.2 s
ns
Note:
External Clock Input High and External Clock Input Low are measured at 50% of the input transition.
MOTOROLA
DSP56002/D, Rev. 3
2-7
Specifications Phase Lock Loop (PLL) Characteristics
PHASE LOCK LOOP (PLL) CHARACTERISTICS

Table 2-6 Phase Lock Loop (PLL) Characteristics
Characteristics VCO frequency when PLL PLL external capacitor4 (PCAP pin to VCCP)
Notes: 1. 2. 3. 4.
Expression MF Ef MF Cpcap @ MF 4 @ MF > 4
Min 10 MF 340 MF 380
Max f MF 480 MF 970
Unit MHz pF pF
enabled1,2,3
The E in ETH, ETL, and ETC means external. MF is the PCTL Multiplication Factor bits (MF0MF11). The maximum VCO frequency is limited to the internal operation frequency. Cpcap is the value of the PLL capacitor (connected between PCAP pin and VCCP) for MF = 1. The recommended value for Cpcap is: 400 pF for MF 4 and 540 pF for MF > 4.
RESET, STOP, MODE SELECT, AND INTERRUPT TIMING

CL = 50 pF + 2 TTL loads WS = number of Wait States (015) programmed into the external bus access using BCR 1 Wait State = TC Table 2-7 Reset, Stop, Mode Select, and Interrupt Timing (All Frequencies)
Num 9 10 Characteristics Delay from RESET Assertion to Address High Impedance (periodically sampled and not 100% tested). Minimum Stabilization Duration Internal Oscillator PLL Disabled1 External clock PLL Disabled2 External clock PLL Enabled2 Delay from Asynchronous RESET Deassertion to First External Address Output (Internal Reset Deassertion) Synchronous Reset Setup Time from RESET Deassertion to first CKOUT transition Synchronous Reset Delay Time from the first CKOUT transition to the First External Address Output Mode Select Setup Time Mode Select Hold Time Minimum Edge-Triggered Interrupt Request Assertion Width Min 75000TC 25TC 2500TC 8TC 8.5 8TC 21 0 13 Max 26 9TC + 20 TC 8TC + 6 Unit ns ns ns ns ns ns ns ns ns ns
11 12 13 14 15 16
2-8
DSP56002/D, Rev. 3
MOTOROLA
Specifications RESET, Stop, Mode Select, and Interrupt Timing
Table 2-7 Reset, Stop, Mode Select, and Interrupt Timing (All Frequencies) (Continued)
Num Characteristics Min 13 Max Unit ns
16a Minimum Edge-Triggered Interrupt Request Deassertion Width 17 Delay from IRQA, IRQB, NMI Assertion to External Memory Access Address Out Valid Caused by First Interrupt Instruction Fetch Caused by First Interrupt Instruction Execution Delay from IRQA, IRQB, NMI Assertion to General Purpose Transfer Output Valid caused by First Interrupt Instruction Execution Delay from Address Output Valid caused by First Interrupt Instruction Execute to Interrupt Request Deassertion for Level Sensitive Fast Interrupts3 Delay from RD Assertion to Interrupt Request Deassertion for Level Sensitive Fast Interrupts3 Delay from WR Assertion to Interrupt Request Deassertion for Level Sensitive Fast Interrupts3 WS = 0 WS > 0 Delay from General-Purpose Output Valid to Interrupt Request Deassertion for Level Sensitive Fast Interrupts3 If Second Interrupt Instruction is: Single Cycle Two Cycles Synchronous Interrupt Setup Time from IRQA, IRQB, NMI Assertion to the second CKOUT transition Synchronous Interrupt Delay Time from the second CKOUT transition to the First External Address Output Valid caused by the First Instruction Fetch after coming out of Wait State Duration for IRQA Assertion to Recover from Stop State Delay from IRQA Assertion to Fetch of First Interrupt Instruction (when exiting Stop)1 Internal Crystal Oscillator Clock, OMR bit 6 = 0 Stable External Clock, OMR Bit 6 = 1 Stable External Clock, PCTL Bit 17 = 1 Duration of Level Sensitive IRQA Assertion to ensure interrupt service (when exiting Stop)1 Internal Crystal Oscillator Clock, OMR bit 6 = 0 Stable External Clock, OMR Bit 6 = 1 Stable External Clock, PCTL Bit 17 = 1
5TC + TH 9TC + TH
ns ns
18
11TC + TH
2 TC + TL + (TC WS) 23 2TC + (TC WS) 21
ns ns ns
19
20 21
2TC 21 TC + TL + (TC WS) 21
ns ns
22
10
TL 31 2TC + TL 31 TC
ns ns ns
23 24
13TC + TH 12
13TC + TH + 6
ns ns
25 26
65548TC 20TC 13TC
ns ns ns
27
65534TC + TL 6TC + TL 12
ns ns ns
MOTOROLA
DSP56002/D, Rev. 3
2-9
Table 2-7 Reset, Stop, Mode Select, and Interrupt Timing (All Frequencies) (Continued)
Num 28 Characteristics Delay from Level Sensitive IRQA Assertion to Fetch of First Interrupt Instruction (when exiting Stop) 1 Internal Crystal Oscillator Clock, OMR bit 6 = 0 Stable External Clock, OMR bit 6 = 1 Stable External Clock, PCTL bit 17= 1
1.
Min
Max
Unit
65548TC 20TC 13TC
ns ns ns
Notes:
2.
3.
A clock stabilization delay is required when using the on-chip crystal oscillator in two cases: after power-on reset, and when recovering from Stop mode. During this stabilization period, TC, TH, and TL will not be constant. Since this stabilization period varies, a delay of 75,000 TC is typically allowed to assure that the oscillator is stable before executing programs. Circuit stabilization delay is required during reset when using an external clock in two cases: after power-on reset, and when recovering from Stop mode. When using fast interrupts and IRQA and IRQB are defined as level-sensitive, then timings 19 through 22 apply to prevent multiple interrupt service. To avoid these timing restrictions, the deasserted Edgetriggered mode is recommended when using fast interrupt. Long interrupts are recommended when using Level-sensitive mode.
VIHR
RESET
10 9 A0A15
11
First Fetch
AA0356
Figure 2-4 Reset Timing
CKOUT 12 RESET 13 A0-A15, DS, PS X/Y

AA0357
Figure 2-5 Synchronous Reset Timing
2-10
DSP56002/D, Rev. 3
MOTOROLA
VIHR RESET 14 VIHM MODA, MODB MODC VILM 15
VIH VIL IRQA, IRQB, NMI

AA0358
Figure 2-6 Operating Mode Select Timing
A0A15
First Interrupt Instruction Execution/Fetch
RD 20 WR 21 IRQA IRQB NMI 17 19
a) First Interrupt Instruction Execution
General Purpose I/O 18 IRQA IRQB NMI b) General Purpose I/O

AA0359
22
Figure 2-7 External Level-Sensitive Fast Interrupt Timing
MOTOROLA
DSP56002/D, Rev. 3
2-11
IRQA, IRQB NMI 16 IRQA, IRQB NMI 16A

AA0361
Figure 2-8 External Interrupt Timing (Negative Edge-Triggered)

CKOUT T0, T2 23 IRQA, IRQB NMI 24 A0A15, DS, PS X/Y
AA0362
T1, T3
Figure 2-9 Synchronous Interrupt from Wait State Timing
25 IRQA 26 A0A15, DS, PS X/Y First Instruction Fetch

AA0363
Figure 2-10 Recovery from Stop State Using IRQA

27 IRQA 28 A0A15, DS, PS X/Y
First IRQA Interrupt Instruction Fetch AA0364
Figure 2-11 Recovery from Stop State Using IRQA Interrupt Service
2-12
DSP56002/D, Rev. 3
MOTOROLA
Specifications Host I/O (HI) Timing
HOST I/O (HI) TIMING

CL = 50 pF + 2 TTL loads Note: Active low lines should be pulled up in a manner consistent with the ac and dc specifications. Table 2-8 Host I/O Timing (All Frequencies)
Num 31 Characteristics HEN/HACK Assertion Width1 CVR, ICR, ISR, RXL Read IVR, RXH/M Read Write HEN/HACK Deassertion Width1 Between Two TXL Writes2 Between Two CVR, ICR, ISR, RXL Reads3 Host Data Input Setup Time Before HEN/HACK Deassertion Host Data Input Hold Time After HEN/HACK Deassertion HEN/HACK Assertion to Output Data Active from High Impedance HEN/HACK Assertion to Output Data Valid HEN/HACK Deassertion to Output Data High Impedance5 Output Data Hold Time After HEN/HACK Deassertion6 HR/W Low Setup Time Before HEN Assertion HR/W Low Hold Time After HEN Deassertion HR/W High Setup Time to HEN Assertion HR/W High Hold Time After HEN/HACK Deassertion HA0HA2 Setup Time Before HEN Assertion HA0HA2 Hold Time After HEN Deassertion DMA HACK Assertion to HREQ Deassertion4 DMA HACK Deassertion to HREQ Assertion4,5 For DMA RXL Read For DMA TXL Write All other cases Min TC + 31 26 13 13 2TC + 31 2TC + 31 4 3 0 2.5 0 3 0 3 0 3 3 TL + TC + TH TL + TC 0 Max 26 18 45 Unit ns
32
ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
33 34 35 36 37 38 39 40 41 42 43 44 45 46
MOTOROLA
DSP56002/D, Rev. 3
2-13
Table 2-8 Host I/O Timing (Continued)(All Frequencies) (Continued)

Num 47 48 49
Notes:
Characteristics Delay from HEN Deassertion to HREQ Assertion for RXL Read4,5 Delay from HEN Deassertion to HREQ Assertion for TXL Write4,5 Delay from HEN Assertion to HREQ Deassertion for RXL Read, TXL Write 4,5
1. 2. 3. 4. 5. 6.
Min TL + TC + TH TL + TC
Max
Unit ns ns
58
ns
See Host Port Considerations in Section 4. This timing must be adhered to only if two consecutive writes to the TXL are executed without polling TXDE or HREQ. This timing must be adhered to only if two consecutive reads from one of these registers are executed without polling the corresponding status bits or HREQ HREQ is pulled up by a 1 k resistor. Specifications are periodically sampled and not 100% tested. May decrease to 0 ns for future versions.
HREQ (Output) 31 HACK (Input) 41 HR/W (Input) 36 35 H0H7 (Output) 38 Data Valid
AA1084
32
42
37
Figure 2-12 Host Interrupt Vector Register (IVR) Read
2-14
DSP56002/D, Rev. 3
MOTOROLA
HREQ (Output) 49 HEN (Input) 43 HA2HA0 (Input) Address Valid 41 HR/W (Input) 36 35 H0H7 (Output) Data Valid 38 Data Valid Data Valid
AA1113
47 RXL Read
RXH Read 31 32 44
RXM Read
Address Valid 42
Address Valid
37
Figure 2-13 Host Read Cycle (Non-DMA Mode)

HREQ (Output) 49 HEN (Input) 43 HA2HA0 (Input) Address Valid 39 HR/W (Input) 34 33 H0H7 (Output) Data Valid Data Valid Data Valid
AA1114
48 TXL Write
TXH Write 31 32 44
TXM Write
Address Valid 40
Address Valid
Figure 2-14 Host Write Cycle (Non-DMA Mode)
MOTOROLA
DSP56002/D, Rev. 3
2-15
HREQ (Output) 45 31 HACK (Input) 36 35 H0H7 (Output) Data Valid 38 Data Valid Data Valid
AA1115
46 46 32 RXM Read 37 RXL Read 46
RXH Read
Figure 2-15 Host DMA Read Cycle

HREQ (Output) 45 31 HACK (Input) 33 H0H7 (Output) Data Valid TXH Write 34 Data Valid Data Valid
AA1116
46 46 32 TXM Write TXL Write 46
Figure 2-16 Host DMA Write Cycle
2-16
DSP56002/D, Rev. 3
MOTOROLA
Specifications Serial Communication Interface (SCI) Timing
SERIAL COMMUNICATION INTERFACE (SCI) TIMING

CL = 50 pF + 2 TTL loads tSCC = Synchronous Clock Cycle Time (For internal clock, tSCC is determined by the SCI Clock Control Register and TC.) The minimum tSCC value is 8 TC. Table 2-9 SCI Synchronous Mode Timing (All Frequencies)
Num 55 56 57 58 59 60 61 62 63 64 65 66 Characteristics Synchronous Clock CycletSCC Clock Low Period Clock High Period < intentionally blank > Output Data Setup to Clock Falling Edge (Internal Clock) Output Data Hold After Clock Rising Edge (Internal Clock) Input Data Setup Time Before Clock Rising Edge (Internal Clock) Input Data Not Valid Before Clock Rising Edge (Internal Clock) Clock Falling Edge to Output Data Valid (External Clock) Output Data Hold After Clock Rising Edge (External Clock) Input Data Setup Time Before Clock Rising Edge (External Clock) Input Data Hold Time After Clock Rising Edge (External Clock) Min 8TC tSCC/2 10.5 tSCC/2 10.5 tSCC/4 + TL 26 tSCC/4 TL 8 tSCC/4 + TL + 23 TC + 3 16 21 Max tSCC/4 + TL 5.5 32.5 Unit ns ns ns ns ns ns ns ns ns ns ns
Table 2-10 SCI Asynchronous Mode Timing1X Clock

Num 67 68 69 70 71 72 Characteristics Asynchronous Clock CycletACC Clock Low Period Clock High Period < intentionally blank > Output Data Setup to Clock Rising Edge (Internal Clock) Output Data Hold After Clock Rising Edge (Internal Clock) Min 64TC tACC/2 11 tACC/2 11 tACC/2 51 tACC/2 51 Max Unit ns ns ns ns ns
MOTOROLA
DSP56002/D, Rev. 3
2-17
Specifications Serial Communication Interface (SCI) Timing
55 56 RCLK TCLK (Output) 59 TXD

Data Valid
57
60
61 62 RXD
Data Valid
a) Internal Clock
55 RCLK TCLK (Input) 63 TXD 65 RXD

Data Valid Data Valid
56
57
64
66
b) External Clock
AA0388
Figure 2-17 SCI Synchronous Mode Timing
67 68 1X TCLK (Output) 71 TXD Note: Data Valid

AA0389
69
72
In the wire-OR mode, TXD can be pulled up by 1 k.
Figure 2-18 SCI Asynchronous Mode Timing
2-18
DSP56002/D, Rev. 3
MOTOROLA
Specifications Synchronous Serial Interface (SSI) Timing
SYNCHRONOUS SERIAL INTERFACE (SSI) TIMING

CL = 50 pF + 2 TTL loads tSSICC = SSI clock cycle time TXC (SCK Pin) = Transmit Clock RXC (SC0 or SCK Pin) = Receive Clock FST (SC2 Pin) = Transmit Frame Sync FSR (SC1 or SC2 Pin) = Receive Frame Sync i ck = Internal Clock x ck = External Clock g ck = Gated Clock i ck a = Internal Clock, Asynchronous Mode (Asynchronous implies that STD and SRD are two different clocks) i ck s = Internal Clock, Synchronous Mode (Synchronous implies that STD and SRD are the same clock) bl = bit length wl = word length Table 2-11 SSI Timing
40 MHZ or 66 MHz Num 80 81 82 84 85 86 87 88 Characteristics Min Clock CycletSSICC1 Clock High Period Clock Low Period RXC Rising Edge to FSR Out (bl) High RXC Rising Edge to FSR Out (bl) Low RXC Rising Edge to FSR Out (wl) High RXC Rising Edge to FSR Out (wl) Low Data In Setup Time Before RXC (SCK in Synchronous Mode) Falling Edge 4TC 3TC tSSICC/2 10.8 TC + TL tSSICC/2 10.8 TC + TL 3.3 15.8 13 Max 40.8 25.8 35.8 25.8 35.8 20.8 35.8 20.8 Min 4TC 3TC TC + 5 TC + 5 TC + 5 TC + 5 3.3 15.8 13 Max 30 25.8 30 25.8 30 20.8 30 20.8 i ck x ck i ck x ck i ck x ck x ck i ck a x ck i ck a x ck i ck a x ck i ck a x ck i ck a i ck s ns ns ns ns ns ns ns ns 80 MHz Case Unit
MOTOROLA
DSP56002/D, Rev. 3
2-19
Table 2-11 SSI Timing (Continued)

40 MHZ or 66 MHz Num 89 Characteristics Min Data In Hold Time After RXC Falling Edge FSR Input (bl) High Before RXC Falling Edge FSR Input (wl) High Before RXC Falling Edge FSR Input Hold Time After RXC Falling Edge Flags Input Setup Before RXC Falling Edge Flags Input Hold Time After RXC Falling Edge TXC Rising Edge to FST Out (bl) High TXC Rising Edge to FST Out (bl) Low TXC Rising Edge to FST Out (wl) High TXC Rising Edge to FST Out (wl) Low TXC Rising Edge to Data Out Enable from High Impedance TXC Rising Edge to Data Out Valid TXC Rising Edge to Data Out High Impedance 2 18 3.3 0.8 17.4 3.3 18.3 18.3 3.3 0.8 16.7 18.3 3.3 101 Max 31.6 15.8 33.3 18.3 30.8 18.3 33.3 18.3 33.3 + TH 20.8 33.3 + TH 22.4 35.8 20.8 Min 18 3.3 0.8 17.4 3.3 18.3 18.3 3.3 0.8 16.7 18.3 3.3 Max 30 15.8 30 18.3 30 18.3 30 18.3 30 20.8 30 22.4 30 20.8 x ck i ck x ck i ck a x ck i ck a x ck i ck x ck i ck s x ck i ck s x ck i ck x ck i ck x ck i ck x ck i ck x ck i ck x ck i ck x ck i ck ns ns ns 80 MHz Case Unit
90
ns
91
ns
92
ns
93
ns
94
ns
95 96 97 98 99
ns ns ns ns ns
100
2-20
DSP56002/D, Rev. 3
MOTOROLA
Table 2-11 SSI Timing (Continued)

40 MHZ or 66 MHz Num 101A Characteristics Min TXC Falling Edge to Data Out High Impedance 2 FST Input (bl) Setup Time Before TXC Falling Edge FST Input (wl) to Data Out Enable from High Impedance FST Input (wl) Setup Time Before TXC Falling Edge FST Input Hold Time After TXC Falling Edge Flag Output Valid After TXC Rising Edge
1. 2.
80 MHz Case Unit ns Min Max TC + TH g ck
Max TC + TH
102
0.8 18.3
30.8
0.8 18.3
30.8
x ck i ck
ns
103
ns
104
0.8 20.0 18.3 3.3
32.5 20.8
0.8 20.0 18.3 3.3
30 20.8
x ck i ck x ck i ck x ck i ck
ns
105
ns
106
ns
Notes:
For internal clock, External Clock Cycle is defined by Icyc and SSI control register. Periodically sampled and not 100% tested
MOTOROLA
DSP56002/D, Rev. 3
2-21
80 TXC (Input/ Output) 81 82
95 FST (Bit) Out
96
97 FST (Word) Out 100 99 Data Out 102 105 FST (Bit) In 103 104 FST (Word) In 106 Flags Out Note: See Note 105 First Bit Last Bit 100 101A
98
101
In the Network mode, output flag transitions can occur at the start of each time slot within the frame. In the Normal mode, the output flag state is asserted for the entire frame period.
AA0390
Figure 2-19 SSI Transmitter Timing
2-22
DSP56002/D, Rev. 3
MOTOROLA
80 81 RXC (Input/Output) 84 FSR (Bit) Out 86 FSR (Word) Out 88 Data In 90 92 FSR (Bit) In 91 FSR (Word) In 93 Flags In 94 92
First Bit
82
85
87
89
Last Bit
AA0391
Figure 2-20 SSI Receiver Timing
MOTOROLA
DSP56002/D, Rev. 3
2-23
Specifications External Bus Asynchronous Timing
EXTERNAL BUS ASYNCHRONOUS TIMING

CL = 50 pF + 2 TTL loads WS = Number of Wait States (0 to 15), as determined by BCR register Capacitance Derating: The DSP56002 External Bus Timing Specifications are designed and tested at the maximum capacitive load of 50 pF, including stray capacitance. Typically, the drive capability of the External Bus pins (A0A15, D0D23, PS, DS, RD, WR, X/Y, EXTP) derates linearly at 1 ns per 12 pF of additional capacitance from 50 pF to 250 pF of loading. Port B and C pins (HI, SCI, SSI, and Timer) derate linearly at 1 ns per 5 pF of additional capacitance from 50 pF to 250 pF of loading. Active low lines should be pulled up in a manner consistent with the AC and DC specifications. Table 2-12 External Bus Asynchronous Timing
40 MHz No. Characteristics Min 115 Delay from BR Assertion to BG Assertion With no 2TC + external access TH from the DSP During external TC + TH read or write access During external TC + TH read-modifywrite access During Stop mode external bus will not be released and BG will not go low During Wait TH mode 116 Delay from BR Deassertion to BG Deassertion 2TC Max Min Max Min Max 66 MHz 80 MHz Unit
4TC + TH + 14
2TC + TH
4TC + TH + 14
2TC + TH
4TC + TH + 14
ns
4TC + TH + TC + TH 4TC + TH + TC + TH 4TC + TH + (TC WS) + 14 (TC WS) + 14 (TC WS) + 14
ns
6TC + TH + TC + TH 6TC + TH + TC + TH 6TC + TH + ns (2TC WS) +14 (2TC WS) +14 (2TC WS) +14 14 14 14 ns
TC + TH + 15 4TC + 12.5
TH 2TC
TC + TH + 15 4TC + 12.5
TH 2TC
TC + TH + 15 4TC + 12.5
ns ns
2-24
DSP56002/D, Rev. 3
MOTOROLA
Table 2-12 External Bus Asynchronous Timing (Continued)

40 MHz No. Characteristics Min 117 BG Deassertion Duration During Wait TC 5.5 mode All other cases 2TC + TH 5.5 118 Delay from Address, Data, and Control Bus High Impedance to BG Assertion 119 Delay from BG Deassertion to Address and Control Bus Enabled 120 Address Valid to WR Assertion WS = 0 WS > 0 121 WR Assertion Width WS = 0 WS > 0 122 WR Deassertion to Address Not Valid 123 WR Assertion to Data Out Active From High Impedance WS = 0 WS > 0 124 Data Out Hold Time from WR Deassertion (the maximum specification is periodically sampled, and not 100% tested) 125 Data Out Setup Time to WR Deassertion WS = 0 WS > 0 0 Max Min Max Min Max 66 MHz 80 MHz Unit
TC 5.5 2TC + TH 5.5 0
TC 5.5 2TC + TH 5.5 0
ns ns ns
TH
TH
TH
ns
TL 6 TC 6 TC 4 WS TC + TL TH 6
TL 4.5 TC 4.5 TC 4 WS TC + TL TH 4
TL 4.5 TC 4.5 TC 2 WS TC + TL TH 4
ns ns ns ns ns
TH 4 0 TH 7
TH 2.5
TH 4 0 TH 5
TH 1.5
TH 4 0 TH 5
TH 1.5
ns ns ns
TL 0.8 WS TC + TL 0.8
TL 0.4 WS TC + TL 0.4
TL 0.5 WS TC + TL 0.5
ns ns
MOTOROLA
DSP56002/D, Rev. 3
2-25

40 MHz No. Characteristics Min 126 RD Deassertion to Address Not Valid 127 Address Valid to RD Deassertion WS = 0 WS > 0 TH Max Min TH 1 Max Min TH Max ns 66 MHz 80 MHz Unit
TC + TL 6 ((WS + 1) TC) + TL 6 0
TC + TL 6 ((WS + 1) TC) + TL 6 0
TC + TL 6 ((WS + 1) TC) + TL 6 0
ns ns
128 Input Data Hold Time to RD Deassertion 129 RD Assertion Width WS = 0 WS > 0
ns
TC 4 ((WS + 1) TC) 4
TC 4 ((WS + 1) TC) 4
TC 4 ((WS + 1) TC) 4
ns ns
130 Address Valid to Input Data Valid WS = 0 WS > 0 131 Address Valid to RD Assertion 132 RD Assertion to Input Data Valid WS = 0 WS > 0 133 WR Deassertion to RD Assertion 134 RD Deassertion to RD Assertion 135 WR Deassertion to WR Assertion WS = 0 WS > 0
TL 4.5
TC + TL 9.5 ((WS+1) TC) + TL 9.5
TL 4.5
TC + TL 7 ((WS+1) TC) + TL 7
TL 4.5
TC + TL 6 ((WS+1) TC) + TL 6
ns ns ns
TC 7 TC 4
TC 7.5 ((WS+1) TC) 7.5
TC 5 TC 2.5
TC 5.5 ((WS+1) TC) 5.5
TC 5 TC 2.5
TC 5.5 ns ((WS+1) TC) ns 5.5 ns ns
TC 4 TC + TH 4
TC 3 TC + TH 3
TC 3 TC + TH 3
ns ns
2-26
DSP56002/D, Rev. 3
MOTOROLA

40 MHz No. Characteristics Min 136 RD Deassertion to WR Assertion WS = 0 WS > 0 Max Min Max Min Max 66 MHz 80 MHz Unit
TC 4 TC + TH 4
TC 2.5 TC + TH 2.5
TC 2.5 TC + TH 2.5
ns ns
BR 115 BG 117 118 A0A15, PS DS, X/Y, RD, WR 119 116
D0D23
AA0392
Figure 2-21 Bus Request / Bus Grant Timing
MOTOROLA
DSP56002/D, Rev. 3
2-27
A0A15, DS, PS, X/Y (See Note) 127 131 RD 120 135 WR 132 123 125 D0D23 Note:
Data Out
126 134
129
122 121 133 136
130 124
Data In
128
During Read-Modify-Write instructions, the address lines do not change state.
AA0393
Figure 2-22 External Bus Asynchronous Timing
2-28
DSP56002/D, Rev. 3
MOTOROLA
Specifications External Bus Synchronous Timing
EXTERNAL BUS SYNCHRONOUS TIMING

CL = 50 pF + 2 TTL loads Capacitance Derating: The DSP56002 external bus timing specifications are designed and tested at the maximum capacitive load of 50 pF, including stray capacitance. Typically, the drive capability of the external bus pins (A0A15, D0D23, PS, DS, RD, WR, X/Y) derates linearly at 1 ns per 12 pF of additional capacitance from 50 pF to 250 pF of loading. Port B and C pins (HI, SCI, SSI, and Timer) derate linearly at 1 ns per 5 pF of additional capacitance from 50 pF to 250 pF of loading. Active-low lines should be pulled up in a manner consistent with the ac and dc specifications. Table 2-13 External Bus Synchronous Timing
40 MHz Num 140 141 Characteristics Min First CKOUT transition to Address Valid Second CKOUT transition to WR Assertion1 WS = 0 WS > 0 Second CKOUT transition to WR Deassertion Second CKOUT transition to RD Assertion Second CKOUT transition to RD Deassertion First CKOUT transition to Data-Out Valid First CKOUT transition to Data-Out Invalid3 Data-In Valid to second CKOUT transition (Setup) Second CKOUT transition to Data-In Invalid (Hold) First CKOUT transition to Address Invalid3
1. 2. 3.
66 MHz Min Max 5
80 MHz Unit Min Max 5 ns ns ns ns ns ns ns ns ns ns ns
Max 6.2
1.3 0 0 3.4 0 0
4.4 TH + 4.4 9.1 3.9 3.4 5.4
1 3 0 3.4 0 0
4 TH + 4 5 3.9 3 4.5
1 3 0 3.4 0 0
4 TH + 4 5 3.9 3 4.5
142 143 144 145 146 147 148 149

Notes:
4. 5.
AC timing specifications which are referenced to a device input signal are measured in production with respect to the 50% point of the respective input signals transition. WS are wait state values specified in the BCR. First CKOUT transition to data-out invalid (specification # T146) and first CKOUT transition to address invalid (specification # T149) indicate the time after which data/address are no longer guaranteed to be valid. Timings are given from CKOUT midpoint to VOL or VOH of the corresponding pin(s). First CKOUT transition is a falling edge of CKOUT for CKP = 0.
MOTOROLA
DSP56002/D, Rev. 3
2-29
T0 CKOUT A0A15 DS, PS X/Y 140 RD 141 WR
T1
T2
T3
T0
T1
T2
T3
T0
143
144
149
142
147 D0D23 145 BN 171 EXTAL 170 Note: 172 Data Out 146 Data In
148
During Read-Modify-Write Instructions, the address lines do not change states.
AA0395
Figure 2-23 Synchronous Bus Timing
2-30
DSP56002/D, Rev. 3
MOTOROLA
Table 2-14 Bus Strobe/Wait Timing

40 MHz No. Characteristics Min 150 First CKOUT transition to BS Assertion 151 WT Assertion to first CKOUT transition (setup time) 152 First CKOUT transition to WT Deassertion for Minimum Timing 153 WT Deassertion to first CKOUT transition for Maximum Timing (2 wait states) 154 Second CKOUT transition to BS Deassertion 155 BS Assertion to Address Valid 156 BS Assertion to WT Assertion1 157 BS Assertion to WT Deassertion1,3 158 WT Deassertion to BS Deassertion 159 Minimum BS Deassertion Width for Consecutive External Accesses 160 BS Deassertion to Address Invalid2 161 Data-In Valid to RD Deassertion (Set Up) 162 BR Assertion to second CKOUT transition for Minimum Timing 5.3 Max 5.6 Min 5.3 Max 5.6 Min 5.3 Max 5.6 ns ns 66 MHz 80 MHz Unit
TC 7.9
TC 7.9
TC 6
ns
7.9
7.9
ns
5.2
5.2
5.2
ns
0 0
2.4 TC 10.9
0 0
2.4 TC 10.9
0 0
2.4 TC 8.8
ns ns ns ns
(WS1) WS TC TC 13.5 TC + TL + 3.3 TH 1 2 TC+TL+ 7.8
ns
TH 4.6 3.4 9.5
TC
TH 4.6 3.4 9.5
TC
TH 4.6 3.4 9.5
TC
ns ns ns
MOTOROLA
DSP56002/D, Rev. 3
2-31
Table 2-14 Bus Strobe/Wait Timing (Continued)

40 MHz No. Characteristics Min 163 BR Deassertion to second CKOUT transition for Minimum Timing 164 First CKOUT transition to BG Assertion 165 First CKOUT transition to BG Deassertion 170 EXTAL to CKOUT with PLL Disabled EXTAL to CKOUT5 with PLL Enabled and MF < 5 171 Second CKOUT transition to BN Assertion 172 Second CKOUT transition to BN Deassertion
Notes: 1. 2. 3. 4.
66 MHz Min 8 Max TC
80 MHz Unit Min 8 Max TC ns
Max TC
3 0.3
8.8 5.3 9.7 3.7
3 0.3
8.8 5.3 9.7 3.7
3 0.3
8.8 5.3 9.7 3.7
ns ns ns ns
5.7
5.7
5.7
ns
ns
5.
If wait states are also inserted using the BCR and if the number of wait states is greater than 2, then specification numbers T156 and T157 can be increased accordingly. BS deassertion to address invalid indicates the time after which the address are no longer guaranteed to be valid. The minimum number of wait states when using BS/WT is two (2). For read-modify-write instructions, the address lines will not change states between the read and the write cycle. However, BS will deassert before asserting again for the write cycle. If wait states are desired for each of the read and write cycle, the WT pin must be asserted once for each cycle. When EXTAL frequency is less than 33 MHz, then timing T170 is not guaranteed for a period of 1000 TC after PLOCK assertion following the events below: when enabling the PLL operation by software, when changing the Multiplication Factor, when recovering from the Stop state if the PLL was turned off and it is supposed to turn, on when exiting the Stop state.
2-32
DSP56002/D, Rev. 3
MOTOROLA
T2 CKOUT
Tw
T2
T3
T0
T1
T2
Tw
T2
T3
T0
T1
162 BR
164
163
165
BG
AA0396
Figure 2-24 Synchronous Bus Request / Bus Grant Timing
MOTOROLA
DSP56002/D, Rev. 3
2-33
T0 CKOUT
T1
T2
Tw
T2
Tw
T2
T3
T0
140 A0A15, PS, DS, X/Y 150 BS 152 151 WT 143 RD 147 Data In D0D23 141 WR 145 D0D23 Note: Data Out 142 148 144 153 154
149
146
During Read-Modify-Write instructions, the address lines do not change state. However, BS will deassert before asserting again for the write cycle.
AA0397
Figure 2-25 Synchronous BS / WT Timings
2-34
DSP56002/D, Rev. 3
MOTOROLA
A0A15, PS, DS, X/Y 155 BS 157 156 WT 131 RD 161 D0D23 120 WR 123 D0D23 Note: 125 Data Out During Read-Modify-Write instructions, the address lines do not change state. However, BS will deassert before asserting again for the write cycle. 124 Data In 122 128 126 158 158 160
AA0398
Figure 2-26 Asynchronous BS / WT Timings
MOTOROLA
DSP56002/D, Rev. 3
2-35
Specifications OnCE Port Timing
OnCE PORT TIMING

CL = 50 pF + 2 TTL loads Table 2-15 OnCE Port Timing
Num 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 DSCK Low DSCK High DSCK Cycle Time DR Asserted to DSO (ACK) Asserted DSCK High to DSO Valid DSCK High to DSO Invalid DSI Valid to DSCK Low (Setup) DSCK Low to DSI Invalid (Hold) Last DSCK Low to OS0OS1, ACK Active DSO (ACK) Asserted to First DSCK High DSO (ACK) Assertion Width DSO (ACK) Asserted to OS0OS1 High Impedance2 OS0OS1 Valid to second CKOUT transition Second CKOUT transition to OS0OS1 Invalid Last DSCK Low of Read Register to First DSCK High of Next Command Last DSCK Low to DSO Invalid (Hold) DR Assertion to second CKOUT transition for Wake Up from Wait state Second CKOUT transition to DSO after Wake Up from Wait state DR Assertion Width To recover from Wait state To recover from Wait state and enter Debug mode DR Assertion to DSO (ACK) Valid (enter Debug mode) After Asynchronous Recovery from Wait State DR Assertion Width to Recover from Stop state1 Stable External Clock, OMR Bit 6 = 0 Stable External Clock, OMR Bit 6 = 1 Stable External Clock, PCTL Bit 17= 1 Characteristics Min 40 40 200 5TC 3 15 3 3TC + TL 2TC 4TC + TH 3 TC 21 0 7TC + 10 3 12 17TC Max 42 5TC + 7 0 TC Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
15 13TC + 15 17TC
12TC 15
ns
249 250A
ns
15 15 15
65548TC + TL 20TC + TL 13TC + TL
ns ns ns
2-36
DSP56002/D, Rev. 3
MOTOROLA
Table 2-15 OnCE Port Timing

Num 250B Characteristics DR Assertion Width to Recover from Stop state and enter Debug mode1 Stable External Clock,OMR Bit 6 = 0 Stable External Clock,OMR Bit 6 = 1 Stable External Clock,PCTL Bit 17= 1 DR Assertion to DSO (ACK) Valid (enter Debug mode) after recovery from Stop state1 Stable External Clock, OMR Bit 6 = 0 Stable External Clock, OMR Bit 6 = 1 Stable External Clock, PCTL Bit 17= 1
1.
Min
Max
Unit
65549TC + TL 21TC + TL 14TC + TL
ns ns ns
251
65553TC + TL 25TC + TL 18TC + TL
ns ns ns
Notes:
2.
A clock stabilization delay is required when using the on-chip crystal oscillator in two cases: after power-on Reset, and when recovering from Stop mode. During this stabilization period, TC, TH, and TL will not be constant. Since this stabilization period varies, a delay of 75,000 TC is typically allowed to assure that the oscillator is stable before executing programs. While it is possible to set OMR bit 6 = 1 when using the internal crystal oscillator, it is not recommended and these specifications do not guarantee timings for that case. The maximum specified is periodically sampled and not 100% tested.
230 DSCK (Input) 231 232

AA0399
Figure 2-27 OnCE Serial Clock Timing

DR (Input) 233 DSO (Output) (ACK)
AA0400
Figure 2-28 OnCE Acknowledge Timing
MOTOROLA
DSP56002/D, Rev. 3
2-37
DSCK (Input)
(Last)
(OS1)
DSO (Output) 236 DSI (Input) (See Note) Note: High Impedance, external pull-down resistor 237 238
(ACK)
(OS0)
AA0501
Figure 2-29 OnCE Data I/O To Status Timing

DSCK (Input) 234 DSO (Output) Note: High Impedance, external pull-down resistor
AA0502
(Last) 235 245 (See Note)
Figure 2-30 OnCE Read Timing
239 OS1 (Output) 241 240 DSO (Output) (DSO Output) (DSI Input) OS0 (Output) (See Note) (DSCK Input)
241
(See Note) 236 237
Note:
High Impedance, external pull-down resistor
AA0503
Figure 2-31 OnCE Data I/O To Status Timing
2-38
DSP56002/D, Rev. 3
MOTOROLA
CKOUT 242 OS0OS1 (Output) (See Note) Note: High Impedance, external pull-down resistor
AA0504
243
Figure 2-32 OnCE CKOUT To Status Timing
DSCK (Input) 244
(Next Command)
AA0505
Figure 2-33 OnCE Read Register to Next Command Timing
CKOUT
T0, T2
T1, T3 248
DR (Input) 246 DSO (Output)

AA0506
247
Figure 2-34 Synchronous Recovery from Wait State
248 DR (Input) 249 DSO (Output)

AA0507
Figure 2-35 Asynchronous Recovery from Wait State
MOTOROLA
DSP56002/D, Rev. 3
2-39
250 DR (Input) 251 DSO (Output)

AA0508
Figure 2-36 Asynchronous Recovery from Stop State
2-40
DSP56002/D, Rev. 3
MOTOROLA
Specifications Timer Timing
TIMER TIMING
CL = 50 pF + 2 TTL loads Table 2-16 Timer Timing
Num 260 261 262 263 TIO Low TIO High Synchronous Timer Setup Time from TIO (input) Assertion to CKOUT Rising Edge Synchronous Timer Delay Time from CKOUT Rising Edge to the External Memory Access Address Out Valid Caused by First Interrupt Instruction Execution CKOUT Rising Edge to TIO (output) Assertion CKOUT Rising Edge to TIO (output) Deassertion CKOUT Rising Edge to TIO (General Purpose Output) Characteristics Min 2TC + 7 2TC + 7 10 5TC + TH Max TC Unit ns ns ns ns
264 265 266
0 0 0
8 8 8
ns ns ns
TIO 260 261

AA0509
Figure 2-37 TIO Timer Event Input
CKOUT
TIO (Input) 262 ADDRESS 263 First Interrupt Instruction Execution

AA0510
Figure 2-38 Timer Interrupt Generation
MOTOROLA
DSP56002/D, Rev. 3
2-41
Specifications Timer Timing
CKOUT
TIO (Output) 264 265

AA0511
Figure 2-39 External Pulse Generation

fetch the instruction MOVE X0,X:(R0); X0 contains the new value of TIO ; and R0 contains the address of TCSR CKOUT A0A15 PS, DS EXTP, X/Y TIO (Output)
AA0512
266
Figure 2-40 GPIO Output Timing
2-42
DSP56002/D, Rev. 3
MOTOROLA
SECTION PACKAGING
PIN-OUT AND PACKAGE INFORMATION
This sections provides information about the available packages for this product, including diagrams of the package pinouts and tables describing how the signals described in Section 1 are allocated for each package. The DSP56002 is available in three package types: 132-pin Plastic Quad Flat Pack (PQFP) 144-pin Thin Quad Flat Pack (TQFP) 132-pin Ceramic Pin Grid Array (PGA)
MOTOROLA
DSP56002/D, Rev. 3
3-1
Packaging Pin-out and Package Information
PQFP Package Description

Top and bottom views of the PQFP package are shown in Figure 3-1 and Figure 3-2 with their pin-outs.
H5/PB5 GNDH H6/PB6 H7/PB7 HREQ/PB13 HR/W/PB11 GNDH HEN/PB12 VCCH HACK/PB14 HA0/PB8 HA1/PB9 GNDH HA2/PB10 GNDQ VCCQ EXTAL XTAL PINIT PLOCK GNDP PCAP VCCP CKP RESET VCCCK CKOUT GNDCK MODA/IRQA MODB/IRQB MODC/NMI D23 D22
117
Note:
1. NC are No Connection pins that are reserved for possible future enhancements. Do not connect these pins to any power, ground, signal traces, or vias. 2. An OVERBAR indicates the signal is asserted when the voltage = ground (active low). 3. To simplify locating the pins, each fifth pin is shaded in the illustration.
AA0611
Figure 3-1 Top View of the 132-pin Plastic Quad Flat Pack (PQFP) Package
3-2
DR DSO DSI/OS0 BS X/Y GNDA DS VCCA PS A0 A1 GNDA A2 A3 A4 VCCQ GNDQ A5 VCCA GNDA A6 A7 A8 A9 GNDA A10 A11 A12 VCCA A13 GNDA A14 A15
51
H4/PB4 H3/PB3 VCCH H2/PB2 GNDH H1/PB1 H0/PB0 RXD/PC0 TXD/PC1 GNDS SCLK/PC2 SC0/PC3 VCCS SCK/PC6 SC2/PC5 STD/PC8 GNDS SC1/PC4 GNDQ VCCQ SRD/PC7 TIO NC BN WT BG BR VCCC WR RD GNDC NC DSCK/OS1
18
Orientation Mark (Chamfered Edge)
(Top View)
84
GNDD D21 D20 VCCD D19 D18 GNDD D17 D16 D15 D14 GNDD D13 D12 VCCD D11 D10 GNDD GNDQ VCCQ D9 D8 D7 D6 GNDD D5 D4 VCCD D3 D2 GNDD D1 D0
DSP56002/D, Rev. 3
MOTOROLA
84
Note:
AA0612
Figure 3-2 Bottom View of the 132-pin Plastic Quad Flat Pack (PQFP) Package
MOTOROLA
A15 A14 GNDA A13 VCCA A12 A11 A10 GNDA A9 A8 A7 A6 GNDA VCCA A5 GNDQ VCCQ A4 A3 A2 GNDA A1 A0 PS VCCA DS GNDA X/Y BS DSI/OS0 DSO DR
DSP56002/D, Rev. 3
51
GNDD D21 D20 VCCD D19 D18 GNDD D17 D16 D15 D14 GNDD D13 D12 VCCD D11 D10 GNDD GNDQ VCCQ D9 D8 D7 D6 GNDD D5 D4 VCCD D3 D2 GNDD D1 D0
117
D22 D23 MODC/NMI MODB/IRQB MODA/IRQA GNDCK CKOUT VCCCK RESET CKP VCCP PCAP GNDP PLOCK PINIT XTAL EXTAL VCCQ GNDQ HA2/PB10 GNDH HA1/PB9 HA0/PB8 HACK/PB14 VCCH HEN/PB12 GNDH HR/W/PB11 HREQ/PB13 H7/PB7 H6/PB6 GNDH H5/PB5
1
18 H4/PB4 H3/PB3 VCCH H2/PB2 GNDH H1/PB1 H0/PB0 RXD/PC0 TXD/PC1 GNDS SCLK/PC2 SC0/PC3 VCCS SCK/PC6 SC2/PC5 STD/PC8 GNDS SC1/PC4 GNDQ VCCQ SRD/PC7 TIO NC BN WT BG BR VCCC WR RD GNDC NC DSCK/OS1
Orientation Mark (Chamfered Edge on Top Side)
(Bottom View)
3-3
The DSP56002 signals that may be programmed as General Purpose I/O are listed with their primary function in Table 3-9. Table 3-1 DSP56002 General Purpose I/O Pin Identification in PQFP Package
Pin Number 24 23 21 19 18 17 15 14 7 6 4 12 10 13 8 25 26 28 29 35 32 31 38 33 39 Primary Function H0 H1 H2 H3 H4 H5 H6 H7 HA0 HA1 HA2 HR/W HEN HREQ HACK RXD TXD SCLK SC0 SC1 SC2 SCK SRD STD TIO C Port B GPIO ID PB0 PB1 PB2 PB3 PB4 PB5 PB6 PB7 PB8 PB9 PB10 PB11 PB12 PB13 PB14 PC0 PC1 PC2 PC3 PC4 PC5 PC6 PC7 PC8 No port assigned
3-4
DSP56002/D, Rev. 3
MOTOROLA
Table 3-2 DSP56002 Signal Identification by PQFP Pin Number

Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 Signal Name EXTAL VCCQ GNDQ HA2/PB10
GNDH
Pin No. 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
Signal Name TXD/PC1 GNDS SCLK/PC2 SC0/PC3 VCCS SCK/PC6 SC2/PC5 STD/PC8 GNDS SC1/PC4 GNDQ VCCQ SRD/PC7 TIO* NC BN WT BG BR VCCC WR RD GNDC NC DSCK/OS1
Pin No. 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75
Signal Name DR DSO DSI/OS0 BS X/Y GNDA DS VCCA PS A0 A1 GNDA A2 A3 A4 VCCQ GNDQ A5 VCCA GNDA A6 A7 A8 A9 GNDA
HA1/PB9 HA0/PB8 HACK/PB14 VCCH HEN/PB12 GNDH HR/W/PB11 HREQ/PB13 H7/PB7 H6/PB6 GNDH H5/PB5 H4/PB4 H3/PB3 VCCH H2/PB2 GNDH H1/PB1 H0/PB0 RXD/PC0
MOTOROLA
DSP56002/D, Rev. 3
3-5
Table 3-2 DSP56002 Signal Identification by PQFP Pin Number (Continued)

Pin No. 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94
Note: 1. 2.
Signal Name A10 A11 A12 VCCA A13 GNDA A14 A15 D0 D1 GNDD D2 D3 VCCD D4 D5 GNDD D6 D7
Pin No. 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113
Signal Name D8 D9 VCCQ GNDQ GNDD D10 D11 VCCD D12 D13 GNDD D14 D15 D16 D17 GNDD D18 D19 VCCD
Pin No. 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132
Signal Name D20 D21 GNDD D22 D23 MODC/NMI MODB/IRQB MODA/IRQA GNDCK CKOUT VCCCK RESET CKP VCCP PCAP GNDP PLOCK PINIT XTAL
NC are No Connection pins that are reserved for possible future enhancements. Do not connect these pins to any power, ground, signal traces, or vias. An OVERBAR indicates the signal is asserted when the voltage = ground (active low).
3-6
DSP56002/D, Rev. 3
MOTOROLA
Table 3-3 DSP56002 PQFP Pin Identification by Signal Name

Signal Name A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 BG BN BR BS CKOUT CKP D0 D1 D2 Pin No. 60 61 63 64 65 68 71 72 73 74 76 77 78 80 82 83 43 41 44 54 123 126 84 85 87 Signal Name D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 D20 D21 D22 D23 DR DS DSCK DSI Pin No. 114 116 117 119 94 95 96 100 101 103 104 106 107 108 109 111 112 114 115 117 118 51 57 50 53 Signal Name DSO EXTAL GNDA GNDA GNDA GNDA GNDA GNDC GNDCK GNDD GNDD GNDD GNDD GNDD GNDD GNDH GNDH GNDH GNDH GNDP GNDQ GNDQ GNDQ GNDQ GNDS Pin No. 52 1 56 62 70 75 81 48 122 86 92 99 105 110 116 5 11 16 22 129 3 36 67 98 27
MOTOROLA
DSP56002/D, Rev. 3
3-7
Table 3-3 DSP56002 PQFP Pin Identification by Signal Name (Continued)

Signal Name GNDS H0 H1 H2 H3 H4 H5 H6 H7 HA0 HA1 HA2 HACK HEN HR/W HREQ IRQA IRQB MODA MODB MODC NMI OS0 OS1 PB0 VCCQ VCCQ VCCQ VCCQ Pin No. 34 24 23 21 19 18 17 15 14 7 6 4 8 10 12 13 121 120 121 120 119 119 53 50 24 2 37 66 97 Signal Name PB1 PB2 PB3 PB4 PB5 PB6 PB7 PB8 PB9 PB10 PB11 PB12 PB13 PB14 PC0 PC1 PC2 PC3 PC4 PC5 PC6 PC7 PC8 PCAP PINIT VCCS WR WT X/Y Pin No. 23 21 19 18 17 15 14 7 6 4 12 10 13 8 25 26 28 29 35 32 31 38 33 128 131 30 46 42 55 Signal Name PLOCK PS RD RESET RXD SC0 SC1 SC2 SCK SCLK SRD STD TIO TXD VCCA VCCA VCCA VCCC VCCCK VCCD VCCD VCCD VCCH VCCH VCCP XTAL nc nc Pin No. 130 59 47 125 25 29 35 32 31 28 38 33 39 26 58 69 79 45 124 89 102 113 9 20 127 132 40 49
3-8
DSP56002/D, Rev. 3
MOTOROLA
Power and ground pins have special considerations for noise immunity. See Section 4 Design Considerations. Table 3-4 DSP56002 Power Supply Pins in PQFP Package
Pin Number 58 69 79 56 62 70 75 81 45 48 124 122 89 102 113 86 92 99 105 110 116 9 20 5 11 16 22 GNDH VCCH Host Interface Buffers GNDD Data Bus Buffers VCCD VCCC GNDC VCCCK GNDCK Bus Control Buffers Clock GNDA Address Bus Buffers VCCA Power Supply Circuit Supplied
MOTOROLA
DSP56002/D, Rev. 3
3-9
Table 3-4 DSP56002 Power Supply Pins in PQFP Package (Continued)

Pin Number 2 37 66 97 3 36 67 98 127 129 30 27 34 VCCP GNDP VCCS GNDS Serial Port PLL GNDQ VCCQ Internal Logic Power Supply Circuit Supplied
3-10
DSP56002/D, Rev. 3
MOTOROLA
A A1 S S1 J
1 17 18 PIN 1 IDENT
128X
AC AC
X X=L, M, OR N
J1 N
117 116
VIEW AB
V1 M P V AA P1
B1
C L VIEW AB
BASE METAL
L AA
50 51 83
(D)
84
D2 0.016 H L-M N 0.010 T L-M N 0.012 H L-M N 0.002 N

2X NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1982. 2. DIMENSIONS IN INCHES. 3. DIMENSIONS A, B, J, AND P DO NOT INCLUDE MOLD PROTRUSION. ALLOWABLE MOLD PROTRUSION FOR DIMENSIONS A AND B IS 0.007, FOR DIMENSIONS J AND P IS 0.010. 4. DATUM PLANE H IS LOCATED AT THE UNDERSIDE OF LEADS WHERE LEADS EXIT PACKAGE BODY. 5. DATUMS L, M, AND N TO BE DETERMINED WHERE CENTER LEADS EXIT PACKAGE BODY AT DATUM H. 6. DIMENSIONS S AND V TO BE DETERMINED AT SEATING PLANE, DATUM T. 7. DIMENSIONS A, B, J, AND P TO BE DETERMINED AT DATUM PLANE H. 8. DIMENSION F DOES NOT INCLUDE DAMBAR PROTRUSIONS. DAMBAR PROTRUSION SHALL NOT CAUSE THE LEAD WIDTH TO EXCEED 0.019.
E1
PLATING
0.002 L-M
4X
2X
SECTION AC-AC
4X 33 TIPS 4X
C C2
0.004 T
132X SEATING PLANE
C1
132X D1
T 0.008 M T L-M N
R R1 H
K1
GAGE PLANE
U
132X D
0.008 M T L-M N SECTION AA-AA
CASE 831A-02 ISSUE C
DIM A A1 B B1 C C1 C2 D D1 D2 E E1 F G J J1 K K1 P P1 R1 S S1 U V V1 W
INCHES MIN MAX 1.100 BSC 0.550 BSC 1.100 BSC 0.550 BSC 0.160 0.180 0.020 0.040 0.135 0.145 0.008 0.012 0.012 0.016 0.008 0.011 0.006 0.008 0.005 0.007 0.014 0.014 0.025 BSC 0.950 BSC 0.475 BSC 0.034 0.044 0.010 BSC 0.950 BSC 0.475 BSC 0.013 REF 1.080 BSC 0.540 BSC 0.025 REF 1.080 BSC 0.540 BSC 0.006 0.008 0 8
Figure 3-3 132-Pin Plastic Quad Flat Pack (PQFP) Mechanical Information
MOTOROLA
DSP56002/D, Rev. 3
3-11
TQFP Package Description

Top and bottom views of the TQFP package are shown in Figure 3-4 and Figure 3-5 with their pin-outs.
NC A15 A14 GNDA A13 VCCA A12 A11 A10 GNDA A9 A8 A7 A6 GNDA VCCA A5 NC GNDQ VCCQ A4 A3 A2 GNDA A1 A0 PS VCCA DS GNDA X/Y BS DSI/OS0 DSO DR NC 73
Note:
AA0613
Figure 3-4 Top View of the 144-pin Thin Quad Flat Pack (TQFP) Package
3-12
NC D22 D23 MODC/NMI MODB/IRQB MODA/IRQA GNDCK CKOUT VCCCK RESET CKP VCCP PCAP GNDP PLOCK PINIT XTAL NC EXTAL VCCQ GNDQ HA2/PB10 GNDH HA1/PB9 HA0/PB8 HACK/PB14 VCCH HEN/PB12 GNDH HR/W/PB11 HREQ/PB13 H7/PB7 H6/PB6 GNDH H5/PB5 NC
NC D0 D1 GNDD D2 D3 VCCD D4 D5 GNDD D6 D7 D8 D9 VCCQ GNDQ GNDD D10 NC D11 VCCD D12 D13 GNDD D14 D15 D16 D17 GNDD D18 D19 VCCD D20 D21 GNDD NC
109
(Top View)
Orientation Mark
37
NC DSCK/OS1 NC GNDC RD WR VCCC BR BG WT BN NC TIO SRD/PC7 VCCQ GNDQ SC1/PC4 NC GNDS STD/PC8 SC2/PC5 SCK/PC6 VCCS SC0/PC3 SCLK/PC2 GNDS TXD/PC1 RXD/PC0 H0/PB0 H1/PB1 GNDH H2/PB2 VCCH H3/PB3 H4/PB4 NC
DSP56002/D, Rev. 3
MOTOROLA
NC DSCK/OS1 NC GNDC RD WR VCCC BR BG WT BN NC TIO SRD/PC7 VCCQ GNDQ SC1/PC4 NC GNDS STD/PC8 SC2/PC5 SCK/PC6 VCCS SC0/PC3 SCLK/PC2 GNDS TXD/PC1 RXD/PC0 H0/PB0 H1/PB1 GNDH H2/PB2 VCCH H3/PB3 H4/PB4 NC
73
NC DR DSO DSI/OS0 BS X/Y GNDA DS VCCA PS A0 A1 GNDA A2 A3 A4 VCCQ GNDQ NC A5 VCCA GNDA A6 A7 A8 A9 GNDA A10 A11 A12 VCCA A13 GNDA A14 A15 NC
109
(Bottom View) Orientation Mark (on Top Side)
Note:
AA0614
Figure 3-5 Bottom View of the144-pin Thin Quad Flat Pack (TQFP) Package
MOTOROLA
NC H5/PB5 GNDH H6/PB6 H7/PB7 HREQ/PB13 HR/W/PB11 GNDH HEN/PB12 VCCH HACK/PB14 HA0/PB8 HA1/PB9 GNDH HA2/PB10 GNDQ VCCQ EXTAL NC XTAL PINIT PLOCK GNDP PCAP VCCP CKP RESET VCCCK CKOUT GNDCK MODA/IRQA MODB/IRQB MODC/NMI D23 D22 NC
DSP56002/D, Rev. 3
37
NC D0 D1 GNDD D2 D3 VCCD D4 D5 GNDD D6 D7 D8 D9 VCCQ GNDQ GNDD D10 NC D11 VCCD D12 D13 GNDD D14 D15 D16 D17 GNDD D18 D19 VCCD D20 D21 GNDD NC
3-13
The DSP56002 signals that may be programmed as General Purpose I/O are listed with their primary function in Table 3-9. Table 3-5 DSP56002 General Purpose I/O Pin Identification in TQFP Package
Pin Number 44 43 41 39 38 35 33 32 25 24 22 30 28 31 26 45 46 48 49 56 52 51 59 53 60 Primary Function H0 H1 H2 H3 H4 H5 H6 H7 HA0 HA1 HA2 HR/W HEN HREQ HACK RXD TXD SCLK SC0 SC1 SC2 SCK SRD STD TIO C Port B GPIO ID PB0 PB1 PB2 PB3 PB4 PB5 PB6 PB7 PB8 PB9 PB10 PB11 PB12 PB13 PB14 PC0 PC1 PC2 PC3 PC4 PC5 PC6 PC7 PC8 No port assigned
3-14
DSP56002/D, Rev. 3
MOTOROLA
Table 3-6 DSP56002 Signal Identification by TQFP Pin Number

Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 Signal Name NC D22 D23 MODC/NMI MODB/IRQB MODA/IRQA GNDCK CKOUT VCCCK RESET CKP VCCP PCAP GNDP PLOCK PINIT XTAL NC EXTAL VCCQ GNDQ HA2/PB10 GNDH HA1/PB9 HA0/PB8 Pin No. 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 Signal Name HACK/PB14 VCCH HEN/PB12 GNDH HR/W/PB11 HREQ/PB13 H7/PB7 H6/PB6 GNDH H5/PB5 NC NC H4/PB4 H3/PB3 VCCH H2/PB2 GNDH H1/PB1 H0/PB0 RXD/PC0 TXD/PC1 GNDS SCLK/PC2 SC0/PC3 VCCS Pin No. 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 Signal Name SCK/PC6 SC2/PC5 STD/PC8 GNDS NC SC1/PC4 GNDQ VCCQ SRD/PC7 TIO NC BN WT BG BR VCCC WR RD GNDC NC DSCK/OS1 NC NC DR DSO
MOTOROLA
DSP56002/D, Rev. 3
3-15
Table 3-6 DSP56002 Signal Identification by TQFP Pin Number (Continued)

Pin No. 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98
Note: 1. 2.
Signal Name DSI/OS0 BS X/Y GNDA DS VCCA PS A0 A1 GNDA A2 A3 A4 VCCQ GNDQ NC A5 VCCA GNDA A6 A7 A8 A9
Pin No. 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121
Signal Name GNDA A10 A11 A12 VCCA A13 GNDA A14 A15 NC NC D0 D1 GNDD D2 D3 VCCD D4 D5 GNDD D6 D7 D8
Pin No. 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144
Signal Name D9 VCCQ GNDQ GNDD D10 NC D11 VCCD D12 D13 GNDD D14 D15 D16 D17 GNDD D18 D19 VCCD D20 D21 GNDD NC
3-16
DSP56002/D, Rev. 3
MOTOROLA
Table 3-7 DSP56002 TQFP Pin Identification by Signal Name

Signal Name A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 BG BN BR BS CKOUT CKP D0 D1 D2 Pin No. 83 84 86 87 88 92 95 96 97 98 100 101 102 104 106 107 64 62 65 77 8 11 110 111 113 Signal Name D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 D20 D21 D22 D23 DR DS DSCK DSI Pin No. 114 116 117 119 120 121 122 126 128 130 131 133 134 135 136 138 139 141 142 2 3 74 80 71 76 Signal Name DSO EXTAL GNDA GNDA GNDA GNDA GNDA GNDC GNDCK GNDD GNDD GNDD GNDD GNDD GNDD GNDH GNDH GNDH GNDH GNDP GNDQ GNDQ GNDQ GNDQ GNDS Pin No. 75 19 79 85 94 99 105 69 7 112 118 125 132 137 143 23 29 34 42 14 21 57 90 124 47
MOTOROLA
DSP56002/D, Rev. 3
3-17
Table 3-7 DSP56002 TQFP Pin Identification by Signal Name (Continued)

Signal Name GNDS H0 H1 H2 H3 H4 H5 H6 H7 HA0 HA1 HA2 HACK HEN HR/W HREQ IRQA IRQB MODA MODB MODC NMI OS0 OS1 PB0 Pin No. 54 44 43 41 39 38 35 33 32 25 24 22 26 28 30 31 6 5 6 5 4 4 76 71 44 Signal Name PB1 PB2 PB3 PB4 PB5 PB6 PB7 PB8 PB9 PB10 PB11 PB12 PB13 PB14 PC0 PC1 PC2 PC3 PC4 PC5 PC6 PC7 PC8 PCAP PINIT Pin No. 43 41 39 38 35 33 32 25 24 22 30 28 31 26 45 46 48 49 56 52 51 59 53 13 16 Signal Name PLOCK PS RD RESET RXD SC0 SC1 SC2 SCK SCLK SRD STD TIO TXD VCCA VCCA VCCA VCCC VCCCK VCCD VCCD VCCD VCCH VCCH VCCP Pin No. 15 82 68 10 45 49 56 52 51 48 59 53 60 46 81 93 103 66 9 115 129 140 27 40 12
3-18
DSP56002/D, Rev. 3
MOTOROLA
Table 3-7 DSP56002 TQFP Pin Identification by Signal Name (Continued)

Signal Name VCCQ VCCQ VCCQ VCCQ VCCS WR WT X/Y Pin No. 20 58 89 123 50 67 63 78 Signal Name XTAL nc nc nc nc nc nc nc Pin No. 17 70 1 18 36 37 55 61 Signal Name nc nc nc nc nc nc nc Pin No. 72 73 91 108 109 127 144
MOTOROLA
DSP56002/D, Rev. 3
3-19
Power and ground pins have special considerations for noise immunity. See the section Design Considerations. Table 3-8 DSP56002 Power Supply Pins in TQFP Package
Pin Number 81 93 103 79 85 94 99 105 66 69 9 7 115 129 140 112 118 125 132 137 143 27 40 23 29 34 42 GNDH VCCH Host Interface Buffers GNDD Data Bus Buffers VCCC GNDC VCCCK GNDCK VCCD Bus Control Buffers Clock GNDA Address Bus Buffers VCCA Power Supply Circuit Supplied
3-20
DSP56002/D, Rev. 3
MOTOROLA
Table 3-8 DSP56002 Power Supply Pins in TQFP Package (Continued)

Pin Number 20 58 89 123 21 57 90 124 12 14 50 47 54 VCCP GNDP VCCS GNDS Serial Port PLL GNDQ VCCQ Internal Logic Power Supply Circuit Supplied
MOTOROLA
DSP56002/D, Rev. 3
3-21
4X
0.20 T L-M N
4X 36 TIPS
0.20 T L-M N
PIN 1 IDENT
144
109
108
J1 J1 L M
B V
140X
4X
C L X X=L, M OR N G
VIEW Y
36 37 72 73
B1 V1
VIEW Y
N A1 S1 A S VIEW AB C
2
NOTES: 9. DIMENSIONS AND TOLERANCING PER ASME Y14.5, 1994. 10.DIMENSIONS IN MILLIMETERS. 11.DATUMS L, M AND N TO BE DETERMINED AT THE SEATING PLANE, DATUM T. 12.DIMENSIONS S AND V TO BE DETERMINED AT SEATING PLANE, DATUM T. 13.DIMENSIONS A AND B DO NOT INCULDE MOLD PROTRUSION. ALLOWABLE PROTRUSION IS 0.25 PER SIDE. DIMENSIONS A AND B DO INCLUDE MOLD MISMATCH AND ARE DETERMINED AT DATUM PLANE H. 14.DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLED DAMBAR PROTRUSION SHALL NOT CAUSE THE D DIMENSION TO EXCEED 0.35. MILLIMETERS MIN MAX 20.00 BSC 10.00 BSC 20.00 BSC 10.00 BSC 1.40 1.60 0.05 0.15 1.35 1.45 0.17 0.27 0.45 0.75 0.17 0.23 0.50 BSC 0.09 0.20 0.50 REF 0.25 BSC 0.13 0.20 0.13 0.20 22.00 BSC 11.00 BSC 22.00 BSC 11.00 BSC 0.25 REF 1.00 REF 0.09 0.16 0 0 7 11 13
0.1 T
144X DIM A A1 B B1 C C1 C2 D E F G J K P R1 R2 S S1 V V1 Y Z AA 1 2
SEATING PLANE
T
PLATING
AA
C2 0.05
R2 R1
D 0.08
M
BASE METAL
0.25
GAGE PLANE
T L-M N (K) C1 (Y) VIEW AB (Z) E

1
SECTION J1-J1
(ROTATED 90) 144 PL
CASE 918-03 ISSUE C
Figure 3-6 144-pin Thin Plastic Quad Flat Pack (TQFP) Mechanical Information
3-22
DSP56002/D, Rev. 3
MOTOROLA
PGA Package Description

Top and bottom views of the PGA package are shown in Figure 3-7 and Figure 3-8 with their pin-outs.
Orientation Mark 1 A GNDQ B GNDD C VCCD D GNDD E GNDD F D15 G D14 H D11 J VCCD K GNDD L GNDD M VCCD N GNDD D0 GNDA VCCA GNDA GNDA VCCA GNDA VCCA GNDA BS DSCK/ OS1 GNDC D2 D1 A12 A9 A7 A5 A4 A2 PS DSI/OS0 NC VCCC D4 D3 A13 A10 A8 A6 A3 A1 DS DSO BR GNDS D6 D5 A14 A11 A0 X/Y DR BG VCCS D8 D7 A15 RD WR WT GNDS D10 D9 D13 D12 STD SC1 SRD D16 D17 SC0 SCK SC2 D18 D19 D22 H3 H0 SCLK GNDH D20 D21 D23 MODC/ NMI HR/W H4 H1 TXD VCCH MODB/ MODA/ GNDCK CKOUT GNDP IRQA IRQB PINIT EXTAL HA0 HREQ H2 RXD GNDH VCCCK RESET CKP VCCP PCAP PLOCK XTAL HA1 HEN H7 H5 VCCH VCCQ GNDQ VCCQ GNDQ VCCQ GNDQ VCCQ HA2 HACK H6 GNDH GNDH 2 3 4 5 6 7 8 9 10 11 12 13
Top View
TIO
NC
BN
Note:
1. NC are No Connection pins that are reserved for possible future enhancements. Do not connect these pins to any power, ground, signal traces, or vias. 2. An OVERBAR indicates the signal is asserted when the voltage = ground (active low).
AA0615
Figure 3-7 Top View of the 132-pin Ceramic (RC) 13 13 Pin Grid Array Package
MOTOROLA
DSP56002/D, Rev. 3
3-23
Orientation Mark (on Top Side) 13 A GNDH B VCCH C GNDH D VCCH E GNDH F SC2 G SRD H BN J GNDS K VCCS L GNDS M VCCC N GNDC DSCK/ OS1 BS GNDA VCCA GNDA VCCA GNDA GNDA VCCA GNDA D0 GNDD NC DSI/OS0 PS A2 A4 A5 A7 A9 A12 D1 D2 VCCD BR DSO DS A1 A3 A6 A8 A10 A13 D3 D4 GNDD BG DR X/Y A0 A11 A14 D5 D6 GNDD WT WR RD A15 D7 D8 VCCD NC TIO SC1 STD D12 D13 D14 SCK SC0 D17 D16 D15 SCLK H0 H3 D22 D19 D18 GNDD TXD H1 H4 HR/W MODC/ NMI D23 D21 D20 GNDD RXD H2 HREQ HA0 EXTAL PINIT GNDP CKOUT GNDCK MODA/ MODB/ IRQA IRQB VCCD H5 H7 HEN HA1 XTAL PLOCK PCAP VCCP CKP RESET VCCCK GNDD GNDH H6 HACK HA2 VCCQ GNDQ VCCQ GNDQ VCCQ GNDQ VCCQ GNDQ 12 11 10 9 8 7 6 5 4 3 2 1
Bottom View
D9
D10
D11
Note:
1. NC are No Connection pins that are reserved for possible future enhancements. Do not connect these pins to any power, ground, signal traces, or vias. 2. An OVERBAR indicates the signal is asserted when the voltage = ground (active low).
AA0616
Figure 3-8 Bottom View of the 132-pin Ceramic (RC) 13 13 Pin Grid Array Package
3-24
DSP56002/D, Rev. 3
MOTOROLA
The DSP56008 signals that may be programmed as General Purpose I/O are listed with their primary function in Table 3-9. Table 3-9 DSP56002 General Purpose I/O Pin Identification in PGA Package
Pin Number E11 D11 C11 E10 D10 B12 A11 B11 C9 B9 A9 D9 B10 C10 A10 C12 D12 E12 F11 G12 F13 F12 G13 G11 H11 Primary Function H0 H1 H2 H3 H4 H5 H6 H7 HA0 HA1 HA2 HR/W HEN HREQ HACK RXD TXD SCLK SC0 SC1 SC2 SCK SRD STD TIO C Port B GPIO ID PB0 PB1 PB2 PB3 PB4 PB5 PB6 PB7 PB8 PB9 PB10 PB11 PB12 PB13 PB14 PC0 PC1 PC2 PC3 PC4 PC5 PC6 PC7 PC8 No port assigned
MOTOROLA
DSP56002/D, Rev. 3
3-25
Table 3-10 DSP56002 Signal Identification by PGA Pin Number

Pin No. A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 Signal Name GNDQ VCCQ GNDQ VCCQ GNDQ VCCQ GNDQ VCCQ HA2/PB10 HACK/PB14 H6/PB6 GNDH GNDH GNDD VCCCK RESET CKP VCCP PCAP PLOCK XTAL HA1/PB9 HEN/PB12 H7/PB7 H5/PB5 Pin No. B13 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 D1 D2 D3 D4 D5 D9 D10 D11 D12 D13 E1 Signal Name VCCH VCCD MODB/IRQB MODA/IRQA GNDCK CKOUT GNDP PINIT EXTAL HA0/PB8 HREQ/PB13 H2/PB2 RXD/PC0 GNDH GNDD D20 D21 D23 MODC/NMI HR/W/PB11 H4/PB4 H1/PB1 TXD/PC1 VCCH GNDD Pin No. E2 E3 E4 E10 E11 E12 E13 F1 F2 F3 F11 F12 F13 G1 G2 G3 G11 G12 G13 H1 H2 H3 H11 H12 H13 Signal Name D18 D19 D22 H3/PB3 H0/PB0 SCLK/PC2 GNDH D15 D16 D17 SC0/PC3 SCK/PC6 SC2/PC5 D14 D13 D12 STD/PC8 SC1/PC4 SRD/PC7 D11 D10 D9 TIO* NC BN
3-26
DSP56002/D, Rev. 3
MOTOROLA
Table 3-10 DSP56002 Signal Identification by PGA Pin Number (Continued)

Pin No. J1 J2 J3 J4 J10 J11 J12 J13 K1 K2 K3 K4 K5 K9 K10 K11 K12 K13 L1
Note: 1. 2.
Signal Name VCCD D8 D7 A15 RD WR WT GNDS GNDD D6 D5 A14 A11 A0 X/Y DR BG VCCS GNDD
Pin No. L2 L3 L4 L5 L6 L7 L8 L9 L10 L11 L12 L13 M1 M2 M3 M4 M5 M6 M7
Signal Name D4 D3 A13 A10 A8 A6 A3 A1 DS DSO BR GNDS VCCD D2 D1 A12 A9 A7 A5
Pin No. M8 M9 M10 M11 M12 M13 N1 N2 N3 N4 N5 N6 N7 N8 N9 N10 N11 N12 N13
Signal Name A4 A2 PS DSI/OS0 NC VCCC GNDD D0 GNDA VCCA GNDA GNDA VCCA GNDA VCCA GNDA BS DSCK/OS1 GNDC
MOTOROLA
DSP56002/D, Rev. 3
3-27
Table 3-11 DSP56002 PGA Pin Identification by Signal Name

Signal Name A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 BG BN BR BS CKOUT CKP D0 D1 D2 Pin No. K9 L9 M9 L8 M8 M7 L7 M6 L6 M5 L5 K5 M4 L4 K4 J4 K12 H13 L12 N11 C5 B4 N2 M3 M2 Signal Name D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 D20 D21 D22 D23 DR DS DSCK DSI Pin No. L3 L2 K3 K2 J3 J2 H3 H2 H1 G3 G2 G1 F1 F2 F3 E2 E3 D2 D3 E4 D4 K11 L10 N12 M11 Signal Name DSO EXTAL GNDA GNDA GNDA GNDA GNDA GNDC GNDCK GNDD GNDD GNDD GNDD GNDD GNDD GNDH GNDH GNDH GNDH GNDP GNDQ GNDQ GNDQ GNDQ GNDS Pin No. L11 C8 N10 N8 N6 N5 N3 N13 C4 N1 L1 K1 E1 D1 B1 A12 A13 C13 E13 C6 A1 A2 A5 A7 J13
3-28
DSP56002/D, Rev. 3
MOTOROLA
Table 3-11 DSP56002 PGA Pin Identification by Signal Name (Continued)

Signal Name GNDS H0 H1 H2 H3 H4 H5 H6 H7 HA0 HA1 HA2 HACK HEN HR/W HREQ IRQA IRQB MODA MODB MODC NMI OS0 OS1 PB0 PB1 PB2 PB3 PB4 Pin No. L13 E11 D11 C11 E10 D10 B12 A11 B11 C9 B9 A9 A10 B10 D9 C10 C3 C2 C3 C2 D5 D5 M11 N12 E11 D11 C11 E10 D10 Signal Name PB5 PB6 PB7 PB8 PB9 PB10 PB11 PB12 PB13 PB14 PC0 PC1 PC2 PC3 PC4 PC5 PC6 PC7 PC8 PCAP PINIT PLOCK PS RD RESET RXD SC0 SC1 SC2 Pin No. B12 A11 B11 C9 B9 A9 D9 B10 C10 A10 C12 D12 E12 F11 G12 F13 F12 G13 G11 B6 C7 B7 M10 J10 B3 C12 F11 G12 F13 Signal Name SCK SCLK SRD STD TIO TXD VCCA VCCA VCCA VCCC VCCCK VCCD VCCD VCCD VCCH VCCH VCCP VCCQ VCCQ VCCQ VCCQ VCCS WR WT X/Y XTAL nc nc Pin No. F12 E12 G13 G11 H11 D12 N9 N7 N4 M13 B2 M1 J1 C1 B13 D13 B5 A2 A4 A6 A8 K13 J11 J12 K10 B8 H12 M12
MOTOROLA
DSP56002/D, Rev. 3
3-29
Power and ground pins have special considerations for noise immunity. See the section Design Considerations. Table 3-12 DSP56002 Power Supply Pins in PGA Package
Pin Number N9 N7 N4 N10 N8 N6 N5 N3 M13 N13 B2 C4 M1 J1 C1 N1 L1 K1 E1 D1 B1 B13 D13 A12 A13 C13 E13 GNDH VCCH Host Interface Buffers GNDD Data Bus Buffers VCCC GNDC VCCCK GNDCK VCCD Bus Control Buffers Clock GNDA Address Bus Buffers VCCA Power Supply Circuit Supplied
3-30
DSP56002/D, Rev. 3
MOTOROLA
Table 3-12 DSP56002 Power Supply Pins in PGA Package (Continued)

Pin Number A8 A6 A4 A2 A1 A2 A5 A7 B5 C6 K13 J13 L13 VCCP GNDP VCCS GNDS Serial Port PLL GNDQ VCCQ Internal Logic Power Supply Circuit Supplied
-TK
N M L K J H G F E D C B A 1 2 3 4 5 6 7 8 9 10 11 12 13
G G
NOTES: 1. 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. 2. CONTROLLING DIMENSION: INCH. INCHES MIN MAX 1.340 1.380 1.340 1.380 0.100 0.150 0.017 0.022 0.100 BSC 0.170 0.195
-A-
DIM A B C D G K
-BC D 132 PL 0.005 M T A S B S
CASE 789B-01 ISSUE O
Figure 3-9 132-pin Ceramic Pin Grid Array (PGA) Package Mechanical Information
MOTOROLA
DSP56002/D, Rev. 3
3-31
Packaging Ordering Drawings
ORDERING DRAWINGS
Complete mechanical information regarding DSP56002 packaging is available by facsimile through Motorola's Mfax system. Call the following number to obtain information by facsimile:
(602) 244-6591
The Mfax automated system requests the following information: The receiving facsimile telephone number including area code or country code The callers Personal Identification Number (PIN)
Note: For first time callers, the system provides instructions for setting up a PIN, which requires entry of a name and telephone number. The type of information requested: Instructions for using the system A literature order form Specific part technical information or data sheets Other information described by the system messages
A total of three documents may be ordered per call. The DSP56002 132-pin PQFP package mechanical drawing is referenced as 831A-02. The reference number for the 144-pin TQFP package is 918-03. The reference number for the 132-pin ceramic PGA package is 789B-01.
3-32
DSP56002/D, Rev. 3
MOTOROLA
SECTION
DESIGN CONSIDERATIONS
HEAT DISSIPATION
An estimation of the chip junction temperature, TJ, in C can be obtained from the equation: Equation 1: T J = T A + ( P D R JA ) Where: TA = ambient temperature C RJA = package junction-to-ambient thermal resistance C/W PD = power dissipation in package Historically, thermal resistance has been expressed as the sum of a junction-to-case thermal resistance and a case-to-ambient thermal resistance: Equation 2: R JA = R JC + R CA Where: RJA = package junction-to-ambient thermal resistance C/W RJC = package junction-to-case thermal resistance C/W RCA = package case-to-ambient thermal resistance C/W RJC is device-related and cannot be influenced by the user. The user controls the thermal environment to change the case-to-ambient thermal resistance, RCA. For example, the user can change the air flow around the device, add a heat sink, change the mounting arrangement on the Printed Circuit Board, or otherwise change the thermal dissipation capability of the area surrounding the device on a Printed Circuit Board. This model is most useful for ceramic packages with heat sinks; some 90% of the heat flow is dissipated through the case to the heat sink and out to the ambient environment. For ceramic packages, in situations where the heat flow is split between a path to the case and an alternate path through the Printed Circuit Board, analysis of the device thermal performance may need the additional modeling capability of a system level thermal simulation tool. The thermal performance of plastic packages is more dependent on the temperature of the Printed Circuit Board to which the package is mounted. Again, if the
MOTOROLA
DSP56002/D, Rev. 3
4-1
Design Considerations Heat Dissipation
estimations obtained from RJA do not satisfactorily answer whether the thermal performance is adequate, a system level model may be appropriate. A complicating factor is the existence of three common ways for determining the junction-to-case thermal resistance in plastic packages: To minimize temperature variation across the surface, the thermal resistance is measured from the junction to the outside surface of the package (case) closest to the chip mounting area when that surface has a proper heat sink. To define a value approximately equal to a junction-to-board thermal resistance, the thermal resistance is measured from the junction to where the leads are attached to the case. If the temperature of the package case (TT) as determined by a thermocouple, the thermal resistance is computed using the value obtained by the equation (TJ TT)/PD.
As noted above, the junction-to-case thermal resistances quoted in this data sheet are determined using the first definition. From a practical standpoint, that value is also suitable for determining the junction temperature from a case thermocouple reading in forced convection environments. In natural convection, using the junction-to-case thermal resistance to estimate junction temperature from a thermocouple reading on the case of the package will estimate a junction temperature slightly hotter than actual temperature. Hence, the new thermal metric, Thermal Characterization Parameter or JT, has been defined to be (TJ TT)/PD. This value gives a better estimate of the junction temperature in natural convection when using the surface temperature of the package. Remember that surface temperature readings of packages are subject to significant errors caused by inadequate attachment of the sensor to the surface and to errors caused by heat loss to the sensor. The recommended technique is to attach a 40-gauge thermocouple wire and bead to the top center of the package with thermally conductive epoxy. Note: Table 2-2 Thermal Characteristics on page 2-2 contains the package thermal values for this chip.
4-2
DSP56002/D, Rev. 3
MOTOROLA
Design Considerations Electrical Design Considerations
ELECTRICAL DESIGN CONSIDERATIONS
CAUTION
This device contains protective circuitry to guard against damage due to high static voltage or electrical fields. However, normal precautions are advised to avoid application of any voltages higher than maximum rated voltages to this high-impedance circuit. Reliability of operation is enhanced if unused inputs are tied to an appropriate logic voltage level (e.g., either GND or VCC).
Use the following list of recommendations to assure correct DSP operation: Provide a low-impedance path from the board power supply to each VCC pin on the DSP, and from the board ground to each GND pin. Use at least four 0.1 F bypass capacitors positioned as close as possible to the four sides of the package to connect the VCC power source to GND. Ensure that capacitor leads and associated printed circuit traces that connect to the chip VCC and GND pins are less than 0.5 inch per capacitor lead. Use at least a four-layer Printed Circuit Board (PCB) with two inner layers for VCC and GND. Because the DSP output signals have fast rise and fall times, PCB trace lengths should be minimal. This recommendation particularly applies to the address and data buses as well as the RD, WR, IRQA, IRQB, NMI, HEN, and HACK pins. Consider all device loads as well as parasitic capacitance due to PCB traces when calculating capacitance. This is especially critical in systems with higher capacitive loads that could create higher transient currents in the VCC and GND circuits. All inputs must be terminated (i.e., not allowed to float) using CMOS levels. Take special care to minimize noise levels on the PLL supply pins (both VCC and GND).
MOTOROLA
DSP56002/D, Rev. 3
4-3
Design Considerations Power Consumption
POWER CONSUMPTION
Power dissipation is a key issue in portable DSP applications. The following describes some factors which affect current consumption. Current consumption is described by the formula: Equation 3: I = C V f
where:
C = node/pin capacitance V = voltage swing f = frequency of node/pin toggle
For example, for an address pin loaded with a 50 pF capacitance and operating at 5.5 V with a 40 MHz clock, toggling at its maximum possible rate (which is 10 MHz), the current consumption is: Equation 4: I = 50 10 12 5.5 10 10 6 = 2.75mA The maximum internal current value (ICCI-max), reflects the maximum ICC expected when running the code given below. This represents typical internal activity, and is included as a point of reference. Some applications may consume more or less current depending on the code used. The typical internal current value (ICCI-typ) reflects what is typically seen when running the given code. The following steps are recommended for applications requiring very low current consumption: 1. Minimize external memory accesses; use internal memory accesses instead. 2. Minimize the number of pins that are switching. 3. Minimize the capacitive load on the pins. 4. Connect the unused inputs to pull-up or pull-down resistors.
4-4
DSP56002/D, Rev. 3
MOTOROLA
Design Considerations Power Consumption
Current consumption test code:

org jmp org movep move move move move nop rep move rep mov clr move rep mac move jmp nop jmp p:RESET MAIN p:MAIN #$180000,x:$FFFD #0,r0 #0,r4 #$00FF, m0 #$00FF, m4 #256 r0,x:(r0)+ #256 r4,y:(r4)+ a l:(r0)+,a #30 x0,y0,a x:(r0)+,x0 y:(r4)+,y0 a,p:(r5) TP1 MAIN
TP1
MOTOROLA
DSP56002/D, Rev. 3
4-5
Design Considerations Host Port Considerations
HOST PORT CONSIDERATIONS

Careful synchronization is required when reading multibit registers that are written by another asynchronous system. This is a common problem when two asynchronous systems are connected. The situation exists in the host interface. The following paragraphs present considerations for proper operation.
Host Programming Considerations

UNSYNCHRONIZED READING OF RECEIVE BYTE REGISTERS
When reading receive byte registers (RXH, RXM, and RXL) the host programmer should use interrupts or poll the RXDF flag that indicates that data is available. This assures that the data in the receive byte registers will be stable.
OVERWRITING TRANSMIT BYTE REGISTERS

The host programmer should not write to the transmit byte registers (TXH, TXM, and TXL) unless the TXDE bit is set indicating that the transmit byte registers are empty. This guarantees that the transmit byte registers will transfer valid data to the HRX register.
SYNCHRONIZATION OF STATUS BITS FROM DSP TO HOST

HC, HREQ, DMA, HF3, HF2, TRDY, TXDE, and RXDF status bits are set or cleared from inside the DSP and read by the host processor. The host can read these status bits very quickly without regard to the clock rate used by the DSP, but the possibility exists that the state of the bit could be changing during the read operation. This is generally not a system problem, since the bit will be read correctly in the next pass of any host polling routine. Note: Refer to DSP56002 Users Manual sections describing the I/O Interface and Host/DMA Interface Programming Model for descriptions of these status bits.
OVERWRITING THE HOST VECTOR

The Host programmer should change the Host Vector register only when the Host Command bit (HC) is clear. This change guarantees that the DSP interrupt control logic will receive a stable vector.
4-6
DSP56002/D, Rev. 3
MOTOROLA
Design Considerations Host Port Considerations
CANCELLING A PENDING HOST COMMAND EXCEPTION

The host processor may elect to clear the HC bit to cancel the Host Command Exception request at any time before it is recognized by the DSP. Because the host does not know exactly when the exception will be recognized (due to exception processing synchronization and pipeline delays), the DSP may execute the Host Command Exception after the HC bit is cleared. For these reasons, the HV bits must not be changed at the same time the HC bit is cleared.
VARIANCE IN THE HI TIMING

HI timing may vary during initial startup during the time after reset before the PLL locks. Therefore, before a host attempt to load (i.e., bootstrap) the DSP, the host should first make sure that the HI port programming has been completed. The following steps can be used to ensure that the programming is complete: 1. Set the INIT bit in the ICR 2. Poll the INIT bit until it is cleared. 3. Read the ISR. An alternate method is: 1. Write the TREQ/RREQ together with INIT. 2. Poll INIT, ISR, and the HREQ pin.
DSP Programming Considerations

SYNCHRONIZATION OF STATUS BITS FROM HOST TO DSP
DMA, HF1, HF0, and HCP, HTDE, and HRDF status bits are set or cleared by the host processor side of the interface. These bits are individually synchronized to the DSP clock. Note: Refer to DSP56002 Users Manual sections describing the I/O Interface and Host/DMA Interface Programming Model for descriptions of these status bits.
READING HF0 AND HF1 AS AN ENCODED PAIR

A potential problem exists when reading status bits HF0 and HF1 as an encoded pair (i.e., the four combinations 00, 01, 10, and 11 each have significance). A very small probability exists that the DSP will read the status bits synchronized during transition. The solution to this potential problem is to read the HF0 and HF1 bits twice and check for consensus.
MOTOROLA
DSP56002/D, Rev. 3
4-7
Design Considerations Package Compatibility
PACKAGE COMPATIBILITY
The PQFP and TQFP packages are designed so that a single Printed Circuit Board (PCB) can accommodate either package. The two package pinouts are similarly sequenced. Proper orientation of each package with the smaller TQFP footprint inside the PQFP footprint allow connection of PCB traces to either package. For example, the D0 pin is near the corner of both the PQFP package (pin 84) and the TQFP package (pin 109), and is adjacent to D1 on both packages. Note: Some no connect pins in the TQFP pin sequence are excluded from the PQFP pin sequence.
4-8
DSP56002/D, Rev. 3
MOTOROLA
SECTION
ORDERING INFORMATION
DSP56002 ordering information in the table below lists the pertinent information needed to place an order. Consult a Motorola Semiconductor sales office or authorized distributor to determine availability and to order parts. Table 5-1 DSP56002 Ordering Information
Part Supply Voltage Package Type Plastic Quad Flat Pack (PQFP) DSP56002 5V Pin Count Frequency (MHz) 40 132 66 80 40 144 132 66 80 40 Order Number DSP56002FC40 DSP56002FC66 DSP56002FC80 DSP56002PV40 DSP56002PV66 DSP56002PV80 DSP56002RC40
Plastic Thin Quad Flat Pack (TQFP) Ceramic Pin Grid Array
MOTOROLA
DSP56002/D, Rev. 3
5-1
OnCE and Mfax are trademarks of Motorola, Inc.
Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. Typical parameters which may be provided in Motorola data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including Typicals must be validated for each customer application by customers technical experts. Motorola does not convey any license under its patent rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support life, or for any other application in which the failure of the Motorola product could create a situation where personal injury or death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized application, Buyer shall indemnify and hold Motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part. Motorola and are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal Opportunity/Affirmative Action Employer.
How to reach us: USA/Europe/Locations Not Listed: Motorola Literature Distribution P.O. Box 5405 Denver, Colorado 80217 303-675-2140 1 (800) 441-2447 Asia/Pacific: Motorola Semiconductors H.K. Ltd. 8B Tai Ping Industrial Park 51 Ting Kok Road Tai Po, N.T., Hong Kong 852-26629298 Technical Resource Center: 1 (800) 521-6274 DSP Helpline dsphelp@dsp.sps.mot.com Internet: http://www.motorola-dsp.com Japan: Nippon Motorola Ltd. SPD, Strategic Planning Office 4-32-1, Nishi-Gotanda Sinagawa-ku, Tokyo 141, Japan 81-3-5487-8488
Mfax: RMFAX0@email.sps.mot.com TOUCHTONE (602) 244-6609 US & Canada ONLY (800) 774-1848

Motorola: 24-Bit Digital Signal Processor

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MOTOROLA

SEMICONDUCTOR TECHNICAL DATA

Order this document by: DSP56002/D, Rev. 3

16-bit Bus 24-bit Bus

24-bit Timer/ Event Counter

Sync. Serial (SSI) or I/O

Serial Comm. (SCI) or I/O

Host Interface (HI) or I/O

24-bit 56000 DSP Core

Address Generation Unit

PAB XAB YAB GDB PDB XDB YDB

External Address Bus Switch

External Data Bus Switch

Program Decode Controller

Program Address Generator

Data ALU 24 24 + 56 56-bit MAC Two 56-bit Accumulators

Program Control Unit 3 IRQ AA0604

Figure 1 DSP56002 Block Diagram

1996 MOTOROLA, INC.

SECTION 1 SECTION 2 SECTION 3 SECTION 4 SECTION 5

FOR TECHNICAL ASSISTANCE:

1 (800) 521-6274 dsphelp@dsp.sps.mot.com http://www.motorola-dsp.com

Data Sheet Conventions

Logic State True False True False

Signal State Asserted Deasserted Asserted Deasserted

Voltage1 VIL/VOL VIH/VOH VIH/VOH VIL/VOL

Digital Signal Processing Core

Peripheral and Support Circuits

DSP56002 Product Documentation

Table 1 DSP56002 Documentation

Number of Signals 16 24 7 16 Port A1 24 10 4 Port B2 Port C3 15 3 6 1 4

Figure 1-1 is a diagram of DSP56002 signals by functional group.

Signal/Pin Descriptions Introduction

PLL and Clock

SC0SC2 SCK SRD STD

PC3PC5 PC6 PC7 PC8

A0A15 D0D23 PS DS X/Y BS BR BG BN WT RD WR Note:

External Bus Control

Status OnCE Port DSCK DSI DSO DR OS1 OS0

Figure 1-1 Signals Identified by Functional Group

Signal/Pin Descriptions Power

VCCA (3) VCCD (3) VCCC VCCH (2) VCCS

Signal/Pin Descriptions Ground

GNDA (5) GNDD (6) GNDC GND (4) GNDS (2)

Signal/Pin Descriptions PLL and Clock

PLL AND CLOCK

Signal/Pin Descriptions PLL and Clock

Table 1-4 PLL and Clock Signals (Continued)

Signal/Pin Descriptions Address Bus

Signal/Pin Descriptions Bus Control

Output Tri-stated Output Tri-stated

Output Pulled high

Signal/Pin Descriptions Bus Control

Table 1-7 Bus Control Signals (Continued)

Output Pulled low

Output Tri-stated Output Tri-stated

Signal/Pin Descriptions Interrupt and Mode Control

INTERRUPT AND MODE CONTROL

Signal/Pin Descriptions Interrupt and Mode Control

Table 1-8 Interrupt and Mode Control Signals (Continued)

Signal/Pin Descriptions Host Interface (HI) Port

HOST INTERFACE (HI) PORT