International Journal of Computer Information Systems, Vol. 4, No.

1, 2012

High Speed Parallel Counter Design based on State Look-Ahead Logic

R.Venkatesh
PG Scholar Dept of Electronic and Communication Engg., Kalasalingam university ,Krishnankoil , Sriviliputur, tamilnadu, India Venguru007@gmail.com

T.Senthil
Assistant Professor, Dept. of Electronics and Communication Engg., Kalasalingam university, Krishnankoil , Sriviliputur, tamilnadu, India Senthil_td@yahoo.co.in

Abstract Different flip-flop designs vary in the number and

complexity of logic stages they contain, and hence have different inherent parasitic delays and output drive strength. Therefore, Data Transition Look Ahead Logic realized with DLDFF consumes less power than that with conventional counter architecture. First, we design 8-bit parallel counter using state-look ahead logic, with pipeline partitioning methodology achieve high speed operating frequency in parallel counter using only three CMOS-logic module type. From the simulation results, we observe that, the proposed counter using DLDFF has 42% better efficiency than a counter using DFF, and its frequency range up to 1.5GHZ for 8- and 17-bit counters respectively. The circuit has been simulated through on CMOS digital schematic, matlab and Hspice .

be read on-the-fly: iii) a sampling rate equal to the counting rate; and iv) a regular implementation suitable for VLSI. Asynchronous counters: 1. Also known as ripple counter. Ripple counters are the simplest type of binary counters because they require the fewest components to produce a given counting operation. 2. Each FF output drives the CLK input of the next FF. 3. FFs do not change states in exact synchronism with the applied clock pulses. 4. There is delay between the responses of successive FFs. 5. It is also often referred to as a ripple counter due to the way the FFs respond one after another in a kind of rippling effect. Disadvantages of asynchronous counter: 1. Propagation delay occurs through FF cause Q0 2. This effect ripples the next FF resulting Q1 lags some time compare to CLK delay some time from Q 3. The cumulative delay of asynchronous counter is the major disadvantage of this counter in many applications. 4. It limits the rate at which the counter can be clocked and creates decoding problems. 5. The maximum cumulative delay in a counter must be less than the period of the clk waveform. Synchronous counter: The ripple counter is easy to build but there is a limitation of to its highest operating frequency. Here each flip-flop has a delay time and these delays are additive so the propagation delay of the entire counter is the sum of the individual delays. This speed limitation can be overcome by the use of a synchronous or parallel counter. Because here each flip-flop is triggered by the clock and this makes simultaneously transition in all the flip-flops.1.Also known as parallel counter. 2. Synchronous counters eliminate the propagation delay problem because all the clock inputs (cp) are tied to a common clock. 3. Can operate at higher clock frequencies. Asynchronous counters are not useful at very high frequencies, especially for large number of bits. 4. Requires more circuitry than the asynchronous counterpart. 5. The design starts with State diagram, Truth table, K-map & equation, circuit.

Keywords; Architecture design, DLDFF design, highperformance parallel counter design, pipeline counter design.

I.INTRODUCTION Flip-Flop are basic element for storing information and they are fundamental building block for all sequential circuits. In modern high-frequency microprocessor, about 70% of the active switch is consumed by the clock circuitry. In a clock gated flip-flop, unnecessary signal transition and hence invalide data are prevented from propagating down the pipeline. Thereby, switching power is reduced in the combinational logic between flip-flop. COUNTERS are widely considered as essential building blocks for a variety of circuit operations. such as programmable frequency dividers, shifters, code generators, memory select management, and various arithmetic operations. A counter is a register capable of counting number of clock pulses that have arrived at its clock input. They are used for counting number of occurrences of an event and are also useful for generating timing signals to control the sequence of operations in a computer. A counter that follows the binary number sequence is called a binary counter. Basic properties: i) a high counting rate, preferably independent of the counter size; ii) a binary output that can

January

Page 52 of 63

ISSN 2229 5208

International Journal of Computer Information Systems, Vol. 4, No. 1, 2012 II. DELAY FLIP-FLOP In a conventional D Flip Flop shown in Figure 1, the clock signal always flows into the D flipflop irrespective of whether the input changes or not. Part of the clock energy is consumed by the internal clock buffer to control the Transmission gates unnecessarily. Hence, if the input of the flip-flop is identical to its output, the switching of the clock can be suppressed to conserve power.
CONVENTIONAL DFF:

transmission of data is not required. But, when D = 1, Q = 0, the clock is enabled and data gets transmitted. B. Clock control: In Figure.2, the Clock control block consists of the transmission gate TG6 followed by an NMOS transistor. The clock control signal [2] depends on the DLs output. The input to the clock control is given by the external clock CSP and divides into CK and CKN.

C. Operation: A DLDFF is triggered by the positive edge of the clock (CSP). When an input data D is the same as the hold data Q, the DL circuit makes P1 low. This turns the transmission gate in the clock control circuit off. As a result, CK and CKN do not transmit. CK and CKN transmit only when D and Q are different. When D changes to a value different from Q, P1 first changes to high. Next, when CSP rises, CK also rises and changes. Then, P1 changes back to low because D and Q are the same again. This immediately makes CK low. Therefore, a DLDFF consumes less power than a conventional one, when is low because CK is inactive when there are no data transitions. D. Energy efficiency of DL-DFF: Pconv = .PD + PCK PDL-DFF = . (PD + PCK + PP) + PPG/N < ( 1 + PP/PCK)-1 E D-idle = E 0-0 = E 1-1 = EPG/N E 0-1 = E D-idle + ECLK + EG + Eint + Eext E 1-0 = E D-idle + ECLK + EG + Eint EDL-DFF = (E0-1 + E1-0) + (1- ) . ED-idle Where , Pconv -> power efficiency of conventional DFF PDL-DFF -> power efficiency of DATA TRANSITION
LOOK AHEAD DFF EDL-DFF -> LOOK AHEAD DFF Figure 2. Data Transition Look ahead D Flip Flop

Figure 1. Conventional D flip flop DATA TRANSITION LOOK AHEAD DFF:

In a DLDFF shown in Figure 2, the gating function is derived within the flip flop without any external control signal. The external clock signal of the flip-flop still switches. But, the clock signal flowing into the flip flop is deactivated when there are no data transitions. switches. But, the clock signal flowing into the flip flop is deactivated when there are no data transitions.

Energy efficiency of

DATA TRANSITION

E. TIMING DIAGRAM:

A. Data Transition Look Ahead: Figure.2, shows the proposed data transition look ahead D flip flop. The transmission gates TG4 and TG5 (DL) do the data transition look ahead. It compares the hold data at the output with the respective input data and enables the flip flop to write the data, accordingly. The DL block act as an XNOR gate. For example, when D = Q = 1, the clock is inactive and

January

Page 53 of 63

ISSN 2229 5208

International Journal of Computer Information Systems, Vol. 4, No. 1, 2012

III. PARALLEL COUNTER USING DLDFF: A parallel counter is a circuit which provides an m-bit count of the number of the n-inputs that are logic ONES. Larger parallel counters are especially used signal processing elements such as multipliers, convolvers,ect. Parallel counter implementation methods: 1.Threshold gate counters 2.Switching tree counters 3.Carry shower counters 4.Successive doubling counters 5.Quasi digital counters 6.Residue threshold function based counters 7.Reordering counters 8.Synthesized counters. The main contributions of our proposed parallel counter areas follow. 1) A single clock input triggers all counting modules simultaneously, resulting in an operating frequency independent of counter width (assuming ideal parasitic capacitance on the clock wire path, without loss of generality). The total critical path delay (regardless of counter width) is uniform at all counting stages and is equal to the combination of the access time of a 2-bit counting module, a single three-input AND gate delay, and the Data Transition Look Ahead DFF setup-hold time. 2) Our parallel counter architecture leverages modularity, which enables high exibility and reusability, and thus enables short design time for wide counter applications. The architecture is composed of three basic module types separated by DLDFFs in a pipelined organization. These three module types are placed in a highly repetitious structure in both the counting path and the state look-ahead paths, which limits localized connections to only three signals (thus, fan-in<3 and fan-out=1 ). 3) The counter output is in radix-2 representation so the count value can be read on-the-y with no additional logic decoding. 4) Unlike previous parallel counter design that have count latencies of two or three cycles, depending on the counter width, our parallel counter has no count latency, which enables the count value to be read on-the-y.
IV.PARALLEL COUNTER ARCHITECTURE FUNCTION:

V.PARRALLEL COUNTER ARCHITECTURE:

Functional block diagram of our proposed 8-bit parallel counter with state look-ahead logic and counting logic using DLDFFs. The state look-ahead logic consists of all logic encompassed by the dashed box and the counting logic consists of all other logic.

PIPELINE PARTITIONING METHOD:

1. state look ahead logic path 2. counting path Architecture is compose of three basic module type separated by DLDFFs in pipeline organization. Such that module of higher significance are enable when all bit in all module of lower significance is saturate 1.Module-1, 2.Module-2, 3.Module-3. Module-1 and Module-3 are exclusive to the counting path and each module represents two counter bits Module-2 is a conventional positive edge triggered DLDFF and is present in both paths.
COUNTING PATH:

Our proposed parallel counter architecture for a sample 8-bit counter. The main structure consists of the state lookahead path (all logic encompassed by the dashed box) and the counting path (all logic not encompassed by the dashed box). We construct our counter as a single mode counter, which sequences through a xed set of preassigned count states, of which each next count state represents the next counter value in sequence. The counter is partitioned into uniform 2-bit synchronous up counting modules. Next state transitions in counting modules of higher signicance are enabled on the clock cycle preceding the state transition using stimulus from the state look-ahead path. Therefore, all counting modules concurrently transition to their next states at the rising clock edge (CLKIN).

Module-1 is a standard parallel synchronous binary 2-bit counter, which is responsible for low-order bit counting and generating future states for all module-3 in the counting path by pipelining the enable for these future states through the state look-ahead path. The placement of module-2s in the counting path is critical to the novelty of our counter structure. Module-2s in the counting path act as a pipeline between the module-1 and module-3 1 and between subsequent modules. Module-2 placement (coupled with state look-ahead logic) increases counter operating frequency by eliminating the lengthy AND-gate rippling and large AND gate fan-in and fan-out typically present in large width parallel counters. Thus, instead of the modules of higher signicance requiring the ANDing of all enable signals from modules of lower signicance, modules of higher signicance (module-3s in our design) are simply

January

Page 54 of 63

ISSN 2229 5208

enabled by the module-3 s preceding module-2 and state look-ahead logic. Since the coupling of module-2 with module-3 1 introduces an extra cycle delay before module-3 1 is enabled, module-2s DIN is triggered when the module1s count Q1Q0=10 (note that this is only the case for the left most module-2 in the counting path in subsequent module-2s require state look-ahead logic as well). Thus, the module-2s in the counting path provide a 1-cycle look-ahead mechanism for triggering the module-3 enabling the module-2s to maintain a constant delay for all stages and all module-3s to count in parallel at the rising clock edge instead of waiting for the overow rippling in a standard ripple counter.
STATE LOOK AHEAD LOGIC:

The state look-ahead path operates similarly to a carry lookahead adder in that it decodes the low-order count states and carries this decoding over several clock cycles in order to trigger high-order count states. The state look-ahead logic is principally equivalent to the one-cycle look-ahead mechanism in the counting path. For example, in a 4-bit counter constructed of two 2-bit counting modules, the counting paths module-2 decodes the low-order state Q1Q0=10 and carries this decoding across one clock cycle and enables Q3Q2=01 at module-3 1 on the next rising clock edge. This operation is equivalent to decoding Q1Q0=11 and enable Q3Q2=01 on the next immediate rising clock edge. The state look-ahead logic expands this principle to an X-cycle look-ahead mechanism. This state look-ahead logic organization and operation avoids the use of an overhead delay detector circuit that decodes the low order modules to generate the enable signals for higher order modules, and enables all modules to be triggered concurrently on the clock edge, thus avoiding rippling and long frequency delay.

International Journal of Computer Information Systems, Vol. 4, No. 1, 2012 q7q6q5q4q3q2q1q0 and the next counter state equation necessary to enable Q7Q6 will contain q5q4q3q2q1q0 consequently,Q3Q2 at module-3 1 is enabled by the past state q1 from module-1, which carries through one clock cycle in the counting paths module-2, and enable module-3 1 on the next rising clock edge. The 4-bit counter state equation can be expressed as Q3Q2Q1Q0 = Q3Q2 Pipelined(q1 ) ----- (1) Where Pipelined (X) denotes that the past bit values represented by X must be pipelined across one clock cycle. This notation may be recursively applied such that Pipelined (pipelined(X)) would pipeline X across two clock cycles, and so forth. Consequently, the 6-bit counter state equation can be expressed as Q5Q4Q3Q2Q1Q0 = Q5Q4 Pipelined x [(q3 ) Pipelined ( q0)]. --------(2) The complete 8-bit counter state equation can be expressed as: Q7Q6Q5Q4Q3Q2Q1Q0 = Q7Q6 Pipelined [(q5 ) Pipelined [(q3q2) Pipelined ( )] (3) For (1), the past state q1 is pipeline using the one-cycle look-ahead path provided by the left-most module-2 in the counting path. For (2) and (3), the state look ahead path provides the past state q0 and through early overflow pipelining.
CLOCK PERIOD ANALYSIS:

Using the timing diagram depicted, we rst derive the clock period TCLKIN for an 8-bit counter based on the signal propagation through modules and AND gate logic, and subsequently generalize the derivation for an n-bit counter. TCLKIN must be greater than both the counting and the state look-ahead paths delay TCLKIN > TM + TAND3 + Tsetup-hold where (13) is the delay between a module-3 and a subsequent module-2. In addition, (13) can be represented as logic gate delays in order to avoid technology dependent factors, such that Tsetup-hold = 1 INVERTER DELAY TM = 2 INVERTER DELAY TAND3 = 3/2 INVERTER DELAY resulting in TCLKIN = 4.5 INVERTER DELAYS CONCLUSION:

8-bit parallel counter simulation result

VI.DERIVATION OF COUNTER STATE EQUATIONS :

Each counter state equation based on the early overflow pipeline equation. As an example, we derive the counter state equation for the sample 8-bit counter presented. we denote a past counter state using lower case

High-speed parallel counter using Data Transition Look Ahead Logic (DLDFFs) consume less power than conventional D Flip-Flop. Our counter design logic is comprised of only 2-bit counting modules and three-input AND gates. The counter structures main features are a pipelined paradigm and state look-ahead path logic whose interoperation activates all modules concurrently at the systems clock edge, thus providing all counter state values at the exact same time without rippling affects.

January

Page 55 of 63

ISSN 2229 5208

International Journal of Computer Information Systems, Vol. 4, No. 1, 2012 REFERENCES

[1] M. Nogawa and Y.Ohtomo, A Data-Transition Look-Ahead DFF circuit for Statistical Reduction in power consumption, IEEE J. Solid State Circuits, Vol. 33, pp.702706, May, 1998. [2] H. Jacobson, P. Bose, Z. Hu, A. Buyuktosunoglu, V. Zyuban, R. Eickemeyer, L. Eisen, J. Griswell, D. Logan, B. Sinharoy, and J. Tendler, Stretching the limits of clock-gating efficiency in server lass processors, in Proc. Int. Symp. High-Perform Compute. Archit., pp. 238242, Feb. 2005. [3] M.R.Stan, , and D. Ercegovac , Long and fastup/down Counter , IEEE Trans .Comput.,vol.47,no.7,pp.722735,Jul.1998. [4] N. H .E .Weste and D .Harris, CMOS VLSI Design. Reading, MA: Pearson Education, Inc., 2005. [5] J. M. Labaey and M. Pedram, Low Power Design Methodologies. Norwell, MA: Kluwer, ch.3, 1996. [6] S. Abdel-Hafeez, S. Harb, and W. Eisenstadt, High speed digital CMOS divide-by-N frequency divider, in Proc. IEEE Int. Symp. Circuits Syst. (ISCAS), 2008, pp. 592595. [7] M. Alioto, R. Mita, and G. Palumbo, Design of high-speed powerefcient MOS current-mode logic frequency dividers, IEEE Trans. Circuits Syst. II, Expr. Briefs, vol. 53, no. 11, pp. 11651169, Nov. 2006. [8] Altera Corp., Santa Clara, CA, FLEX8000, eld programmable gate array logic device, 2008. [9] A. Bellaour and M. I. Elmasry, Low-Power Digital VLSI Design Circuits and Systems. Norwell, MA: Kluwer, 1995. [10] J. Ousterhout, Berkeley, 1980, Berkley magic layout tools,1980.[Online].Available:http://opencircuitdesign.com/magic/ [11] B. Chang, J. Park, and W. Kim, A 1.2 GHz CMOS dual-modulus prescalar using new dynamic D-type ip-ops, IEEE J. Solid-State Circuits, vol. 31, no. 5, pp. 749752, May 1996. [12] M. Ercegovac and T. Lang, Binary counters with counting period of one half adder independent of Counter size, IEEE Trans. Circuits Syst., vol. 36, no. 6, pp. 924926, Jun. 1989. [13] M. D. Ercegovac and T. Lang, Digital Arithmetic. San Mateo, CA: Mogan Kaufmann, 2004. [14] A. Fard and D. Aberg, A novel 18 GHZ 1.3 mWCMOS frequency divider with high input sensitivity, in Proc. Int. Symp. Signals, Circuits, Syst., Jul. 2005, pp. 409412. [15] C. Foster and F. Stockton, Counting responders in an associative memory, IEEE Trans. Comput., vol. 20, no. 12, pp. 15801583, Dec. 1971. [16] D. C. Hendry, Sequential lookahead method for digital counters, IEEE Electron. Lett., vol. 32, no. 3, pp. 160161, Feb. 1996. ABDELHAFEEZ AND GORDON-ROSS: DIGITAL CMOS PARALLEL COUNTER ARCHITECTURE 1033 [17] N. Homma, J. Sakiyama, T. Wakamatsu, T. Aoki, and T. Higuchi, A systematic approach for analyzing fast addition algorithms using counter tree diagrams, in Proc. IEEE Int. Symp. Circuits Syst. (ISCAS), 2004, pp. V197V-200. [18] B. Hoppe, C. Kroh, H. Meuth, and M. Stohr, A 440 MHz16 bit counter in CMOS standard cells, in Proc. IEEE Int. ASIC Conf., Sep. 1998, vol. 244, pp. 241244. [19] Y. Ito, K. Nakano, and Y. Yamagishi, Efcient hardware algorithms for n choose K counters, in Proc. 20th Int. Parallel Distrib. Process. Symp., Apr. 2006, pp. 18. [20] Y. I. Ismail and E. G. Friedman, On-Chip Inductance in High Speed Integrated Circuits. Norwell, MA: Kluwer, 2001. [21] R. F. Jones, Jr. and E. E. Swartzlander, Jr., Parallel counter implementation, in Proc. 10th Symp. Comput. Arith., 1992, pp. 382385. [22] A. P. Kakarountas, G. Theodoridis, K. S. Papadomanolakis, and C. E. Goutis, A novel high-speed counter with counting rate independent of the counters length, in Proc. IEEE Int. Conf. Electron., Circuits Syst. (ICECS), UAE, Dec. 2003, pp. 11641167. [23] R. H. Katz, Contemporary Logic Design. Redwood City, CA: Benjamin/Cummings, 1994. [24] Y. Leblebici, H. Ozdemir, A. Kepkep, and U. Cilingiroglu, A compact high-speed (31, 5) parallel counter circuit based on capacitive threshold-logic gates, IEEE J. Solid-State Circuits, vol. 31, no. 8, pp.11771183, Aug. 1996. [25] B. Liang, D. Chen, B. Wang, D. Cheng, and T. Kwasniewski, A 43Ghz static frequency divider in 0.13 Mstandard CMOS, in Proc. IEEE Canadian Conf. Elect. Comput. Eng. (CCECE), May 2008, pp. 111114. [26] P. Lin, K. E. Kerr, and A. S. Botha, A novel approach for CMOS parallel counter design, in Proc. 25th EUROMICRO Conf., 1999, pp. 112119. [27] D. R. Lutz and D. N. Jayasimha, Programmable modulo-K counters, IEEE Trans. Circuits Syst. I, Fundam. Theory Appl., vol. 43, no. 11, pp. 939941, Nov. 1996. [28] Mentor Graphics, Wilsonville, OR, Mentor graphics powertrain,1981.[Online]. Available: http://www.mentor.com/ [29] N. Nikityuk, Use of parallel counters for triggering nuclear instruments and methods in physics research, , vol. A321, no. 3, pp. 571 582, Oct. 1992.

AUTHORS PROFILE Mr.R.Venkatesh, doing his M.Tech [VLSI DESIGN ] in kalasalingam university, Tamilnadu, India. He received his B.E degree [Electronics and Communication Engg ] in SACS MAVMM Engg Collage Anna university , Madurai. His research Interests include image processing and wireless Mobile communication.

Mr.T.Senthil doing his Research,Department of Network Engineerig in kalaslingam University. His research Interests include image processing and wireless Mobile communication. In also specialist in analog design & Image proceesing.

January

Page 56 of 63

ISSN 2229 5208