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LABORATORY MANUAL COURSE CODE ECE254 COURSE TITLE : UNIFIED ELECTRONICS LABORATORY-I

TABLE OF CONTENTS
S. No. 1 Description Page No.

To design an implement a function generator to generate 1) Square, 2) triangular and 3) sinusoidal waveforms using IC741 and simulate using pSpice To find gain of the transistor in CE, CB and CC configuration on breadboard and simulate using pSpice To Design and implement 1) Mono-stable 2) Bi-stable and 3) Astable multivibrators using IC555 Timer on breadboard. And simulate using pSpice To implement Full Adder using NAND gates and using pSpice Verify superposition theorem and thevenins theorem using experimental set up on bread board and simulate using pSpice

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To realize a 7-segment code converter on breadboard To realize D/A converters using IC 741 1) R-2R ladder 2) Weighted Ladder, compare the results obtained on breadboard and simulate using pSpice To design and implement an emitter follower circuit on breadboard and simulate using pSpice

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To develop a program to study aliasing in signals using Matlab To study the gain of differential amplifier by varying the value of RE 1) RE= 4.1k ohms 2) RE= 82k ohms on breadboard and and simulate using pSpice To Design and Plot Frequency response of 1) LPF 2) HPF

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3) BPF and 4) BRF using IC741 on breadboard and simulate using pSpice To find gain of the JFET on breadboard and simulate using pSpice To design and realize MOD-10 1) Up counter 2) Down counter on breadboard

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EXPERIMENT NO.: 1 Experiment: - To design an implement a function generator to generate 4) Square, 5) triangular and 6) sinusoidal waveforms using IC741 and simulate using pSpice Learning objective: To know the working principle of square wave generator, triangular wave generator and sine wave generator.

Function Generator Block Diagram: The Schmitt trigger and integrator form a square and triangle generator. The wave shaping circuit uses a differential pair with current source biasing and an emitter resistor. You should have an opamp buffer.

PROCEDURE: 1. Rig up the circuit as shown in the Fig. on the breadboard. 2. Observe the output on CRO. 3. Calculate the amplitude & frequency of the output. 4. Plot the outputs waveforms on the graph paper. 5.Compare the theoretical frequency with the practical frequency of the output.
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TRIANGULAR WAVE GENERATOR

Low Frequency Sine Wave Generator with Quadrature Output Result: Draw the Waveforms, observed on C.R.O. and fill the observed values in the table shown below: OBSERVATION TABLE:

Learning Outcome: (to be written by student in 50-70 words). References: http://circuitdiagram-schematic.com/729/triangular-wavegenerator-circuit/#ixzz1iRe43RLf http://hyperphysics.phy-astr.gsu.edu/hbase/electronic/square.html

EXPERIMENT NO: 2(A) Experiment:- Characteristics of CE configuration using BJT.

Learning objectives: To know the input and output characteristics of three different types of transistor (BJT) configurations THEORY: A BJT is a three terminal two junction semiconductor device in which the conduction is due to both the charge carrier. Hence it is a bipolar device and it amplifier the sine waveform as they are transferred from input to output. BJT is classified into two types NPN or PNP. A NPN transistor consists of two N types in between which a layer of P is sandwiched. The transistor consists of three terminal emitter, collector and base. The emitter layer is the source of the charge carriers and it is heartily doped with a moderate cross sectional area. The collector collects the charge carries and hence moderate doping and large cross sectional area. The base region acts a path for the movement of the charge carriers. In order to reduce the recombination of holes and electrons the base region is lightly doped and is of hollow cross sectional area. Normally the transistor operates with the EB junction forward biased. In transistor, the current is same in both junctions, which

indicates that there is a transfer of resistance between the two junctions. One to this fact the transistor is known as transfer resistance of transistor. PROCEDURE: INPUT CHARECTERISTICS: 1. Connect the circuit as per the circuit diagram. 2. Set VCE ,vary VBE in regular interval of steps and note down the corresponding IB reading. Repeat the above procedure for different values of VCE. 3. Plot the graph: VBE Vs IB for a constant VCE. OUTPUT CHARECTERISTICS: 1. Connect the circuit as per the circuit diagram. 2. Set IB, Vary VCE in regular interval of steps and note down the corresponding IC reading. Repeat the above procedure for different values of IB. 3. Plot the graph: VCE Vs IC for a constant IB. PIN DIAGRAM:

Results: Fill in the response observed in the following table and draw the characteristics on its basis.

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hie =

hfe =

hre =

hoe =

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EXPEIMENT NO: 2(B) Experiment:- Characteristics of CB configuration using BJT.

Learning Objective:- To plot the transistor characteristics of CB configuration. THEORY: In this configuration the base is made common to both the input and out. The emitter is given the input and the output is taken across the collector. The current gain of this configuration is less than unity. The voltage gain of CB configuration is high. Due to the high voltage gain, the power gain is also high. In CB configuration, Base is common to both input and output. In CB configuration the input characteristics relate IE and VEB for a constant VCB. Initially let VCB = 0 then the input junction is equivalent to a forward biased diode and the characteristics resembles that of a diode. Where VCB = +VI (volts) due to early effect IE increases and so the characteristics shifts to the left. The output characteristics relate IC and VCB for a constant IE. Initially increased IC also increases. proportionality. Though increase in VCB

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remains a constant for all values of VCB once it levels off.

PROCEDURE: INPUT CHARACTERISTICS: It is the curve between emitter current IE and emitter-base voltage VBE at constant collector-base voltage VCB. 1. Connect the circuit as per the circuit diagram. 2. Set VCE=5V, vary VBE in steps of 0.1V and note down the corresponding IB. Repeat the above procedure for 10V, 15V. 3. Plot the graph VBE Vs IB for a constant VCE. 4. Find the h parameters.

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OUTPUT CHARACTERISTICS: It is the curve between collector current IC and collector-base voltage VCB at constant emitter current IE. 1. Connect the circuit as per the circuit diagram.

3. Plot the graph VCE Vs IC for a constant IB. 4. Find the h parameters . Results: Fill in the observed response in the following table and design the characteristics on its basis.

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%age ERROR : From data sheet find values of hic, hrc , hfc, hoc and compare these values with practically obtained values to find %age error . Learning outcome: ( to be written by student in 50-60 words).

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EXPERIMENT NO: 2(C) Experiment: Characteristics of CC Configurations using BJT .

Learning Objective: to observe the differences between theoretical and practical results. THEORY: A BJT is a three terminal two junction semiconductor device in which the conduction is due to both the charge carrier. Hence it is a bipolar device and it amplifier the sine waveform as they are transferred from input to output. BJT is classified into two types NPN or PNP. A NPN transistor consists of two N types in between which a layer of P is sandwiched. The transistor consists of three terminal emitter, collector and base. The emitter layer is the source of the charge carriers and it is heartily doped with a moderate cross sectional area. The collector collects the charge carries and hence moderate doping and large cross sectional area. The base region acts a path for the movement of the charge carriers. In order to reduce the recombination of holes and electrons the base region is lightly doped and is of hollow cross sectional area. Normally the transistor operates with the EB junction forward

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biased. In transistor, the current is same in both junctions, which indicates that there is a transfer of resistance between the two junctions. One to this fact the transistor is known as transfer resistance of transistor. PIN DIAGRAM:

INPUT CHARECTERISTICS: 1. Connect the circuit as per the circuit diagram. 2. Set VCE, vary VBE in regular interval of steps and note down the corresponding IB reading. Repeat the above procedure for different values of VCE. 3. Plot the graph: VBC Vs IB for a constant VCE.

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OUTPUT CHARECTERISTICS: 1. Connect the circuit as per the circuit diagram. 2. Set IB, Vary VCE in regular interval of steps and note down the corresponding IC reading. Repeat the above procedure for different values of IB. 3. Plot the graph: VCE Vs IC for a constant IB. Result: fill in the observed results in the following table and draw its characteristics on its basis.

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Percentage ERROR: From data sheet find values of hie, hic , hfc, hoe and compare these values with practically obtained values to find %age error Learning Outcome: (to be written by student in 50-60 words).

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Experiment 3a: ASTABLE MULTIVIBRATOR

AIM: To study and implement IC 555 as Astable Multivibrator.

LEARNING OBJECTIVE: To learn the function of different multi-vibrators and working of 555timer COMPONENTS REQUIRED: red, IC 555 = = 10 K, C= 0.1 and 0.01F, R= 150k, LED

Theory : - In this lab the 555 Timer is examined in detail along with its uses. This timer uses a maze of diodes, transistors, and resistors and for this reason a more simplified diagram of the 555 Timer is used. Below is the typical monostable 555 Timer IC:

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This circuit is dependent on RA, RB, and C. Below is the schematic for the circuit we built: Circuit Diagram:-

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Design: - The following formula was used to find the expected frequency: f = 1/(.693*C*( )) , f=481 Hz

The following are actual measurements taken from the lab: f = 526 Hz The result is very similar to the expected value. The 555 Timer has an internal voltage divider comprising of three 5 k resistors. In our case our supply voltage is 12V which results in a upper voltage threshold of 8V and a lower threshold of 4V. The measurements I obtained from the lab were very similar with a lower threshold of 3.8 V and a higher threshold of 8.1V.

The next part of this section included changing both 10 k resistors to variable 1 M potentiometers. We adjusted the frequency to range from 2 to 5 Hz and observed the LED slowly flashing on and off. We varied the value of the potentiometers to find the smallest and the largest frequency value. We obtained the following results: Largest f
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= 60.1 kHz with RA = 100 and RB = 70 Smallest f = 4.8 Hz with RA = 1 M and RB = 1 M Next we changed VC to +5 V and the frequency doesnt change as the voltage changes, because the threshold voltages change proportionally to the supple voltage, therefore the capacitor has to charge up less. Procedure:1. Make the circuit diagram as shown in above figure on bread board. 2. Give the power supply from dc battery source and see the output. 3. Red colored LED will start glow alternatively depending upon the time constant RC. 4. Observe the output on CRO as well. 5. Now change the time constant by changing the value of RA, RB and C. 6. Measure change in frequency in the output waveform (as well in LED). Observation Table with errors in measurement

S.no.

Measured Time period

Tm+2%

Tm-2%

Average Tmavg= (Tmmax+Tm min)/2

1. 2. 3. 4. 5.

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Calculations using tolerance in component values: f = 1/(.693*C*( ))

RA 10%, RB 10%, C 5% Find min and max values of using new values of components Find average = 1/ Percentage error: ((TM -Tavg)/Tavg) x 100 , and

Scope of Result : At the output square waveforms will be generated and observed.

Exp 3b: Monostable Multivibrator

AIM: To study and implement IC 555 as Monostable Multivibrator.

Components Required: RA=RB= 10 K, C= 0.1 and 0.01F, R= 150k, LED red, IC 555

THEORY: In this lab the 555 Timer is examined in detail along with its uses. This timer uses a maze of diodes, transistors, and resistors and for this reason a more simplified diagram of the 555 Timer is used. Below is the typical monostable 555 Timer IC:
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Internal diagram of IC 555 CIRCUIT DIAGRAMS: The schematic below represents a mono-stable multi-vibrator:

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When the circuit was turned on, the LED was initially off. It was low because the trigger voltage was high due to the pull up resistor, and the voltage across the capacitor at pin 6/7 was equal to zero. After pin 2, the trigger voltage, was grounded the LED turned on and the output went high. This is due to the fact that the mono stable MV was set off. By using an LED at the output of the Timer, we are able to see the output pulse. With the schematic from the lab manual, it is impossible to measure the duration of the pulse by manually triggering the 555 Timer IC. Using a pulse generator with an oscilloscope would be a preferred method.

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DESIGN: Time delay can be calculated using the following equation: t = 1.1RC t = 1.1(10x103 )(0.68x10 6 ) = .0748sec Manually finding the time would be much easier if a larger resistor was used. We tested the operation of the RESET by triggering the input first and then grounding pin 4. When the Reset is grounded the output goes immediately to zero, in other words, the LED turns off before the completion of the timing cycle and the flip flop is reset.

PROCEDURE: 1. Make the circuit diagram as shown in above figure on bread board.

2. Give the power supply from dc batter source and see the output.

3. Red color LED will start glow alternatively depending upon the time constant RC.

4. Observe the output on CRO as well.

5. Now change the time constant by changing the value of RA, RB and C.

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6. Measure change in frequency in the output waveform (in LED as well).

Observation Table with measurement ERRORS Sr no 1 2 3 4 5 6 R C Measured Tm+2 Tm-2% Average Tm avg= % time of ( Tm Max+Tm pulse min)/2 Tm

Value of Tm ranges from

Calculations using tolerance in component values: Calculated pulse duration t = 1.1RC R 10%,, C 5% Find min and max values of t using new values of R and C

Find average Tavg = (tmin+tmax)/2

Percentage error:

= ( (TM -Tavg )/Tavg ) * 100%

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Experiment No.: -4 Experiment: - To realize half/full adder using NAND gates only. Apparatus Required: - IC 7400 Learning Objective: Use of Universal NAND gate to realize a combinational logic. Procedure: 1. Verify the gates. 2. Make the connections as per the circuit diagram. 3. Switch on Vcc and apply various combinations of input according to the truth table . 4. Note down the output readings for half/full adder and sum, carry bit for different combination of input. Half Adder using basic gates:-

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Half Adder using NAND gates only:-

Full Adder using basic gates:-

Full adder using NAND gates only:-

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Result: A tabular column which shows the results of an adder on various possible inputs. Learning Outcome: (to be written by student in 50-70 words).

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EXPERIMENT NO: 5 Aim: Verify superposition theorem and thevenins theorem using experimental set up on bread board and simulate using pSpice Learning Objective: Analysis and verification of Thevenins theorem and superposition theorem. Apparatus Required: 1. Digital multi-meter 2. Power supply (GPC-3020D) 3. Resistors 1 K (1/4 W) [1], 4.7 K (1/4 W) [1], 470 [1], 10 K [1], 47 K [1] 4. Breadboard. Procedure: i) Thevenin Theorem - Connect the circuit as shown in figure 1 on the breadboard - Measure the voltage across AB (i.e. p.d. across load resistor). - Remove load resistor (for first case it is 4.7K). - Measure the open circuit voltage across AB with the help of multimeter ( Placing positive terminal of multimeter at A and negative at B) - Measure the Thevenins resistance with the help of multimeter (with short circuiting voltage sources and open circuiting current sources (if any) (Alternatively you can measure the short circuit current through load). - Connect the circuit as shown in figure 2; replacing ETH and RTH are open circuit voltage and Thevenin resistance respectively, as measured in third step. - Connect the load and measure the voltage across load with the help of voltmeter. - REPEAT above steps for different load resistor. Circuit Diagram:

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ii) Superposition theorem - Connect the circuit as shown in figure 1 on the breadboard. - Set the value of voltage supply 1 to 0 V and supply 2 to 7 V and measure the potential difference across A and B. Also measure the current through load of 4.7K. - Set the value of voltage supply 2 to 0 V and supply 1 to 10 V and measure the potential difference across A and B. Also measure the current through load of 4.7K. - Now set the value of voltage supply 1 to 7 V and supply 2 to 10V and measure the potential difference across A and B and current through load of 4.7K. - REPEAT above steps for different load resistor. Observations:

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Learning Outcome: (to be written by student in 50-70 words).

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EXPERIMENT NO: 6 Experiment: - To realize a 7-segment code converter on breadboard. Learning objective: To study the working of seven segment display. Appratus Required:

Pin connections of BCD to 7 segment decoder IC:

1. A, B, C, D are the binary inputs. 2. a, b, c, d, e, f, g, h are the driver signals to the display elements. 3. LT is the lamp test control, turns all segment On, active Low 4. BL blanks all segments when activated, active LOW 5. LE is the latch enable control.

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Seven-Segment LEDs The seven-segment LED display has four individual digits, each with a decimal point. Each of the seven segments (and the decimal point) in a given digit contains an individual LED. When a suitable voltage is applied to a given segment LED, current flows through and illuminates that segment LED. By choosing which segments to illuminate, any of the nine digits can be shown.

There are two important types of 7-segment LED display. In a common cathode display, the cathodes of all the LEDs are joined together and the individual segments are illuminated by HIGH voltages.

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In a common anode display, the anodes of all the LEDs are joined together and the individual segments are illuminated by connecting to a LOW voltage.

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When the 4511 is set up correctly, the outputs follow this truth table:

RESULT: It can be observed on the seven segment display. Learning Outcome: (to be written by student in 50-70 words).

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EXPERIMENT NO: 7(A)

LEARNING OBJECTIVE: How to convert digital information signal in analog form.

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Result:

Learning Outcome: ( to be written by student in 50-60 words).

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EXPERIMENT NO: 7(B)

Learning Objective: To design a circuit which can convert an analog information into digital form.

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Result:

Learning Outcome: (to be written by student in 50-60 words).

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Experiment No.:8 Experiment :To design and implement an emitter follower circuit on breadboard and simulate using pSpice. Learning Objectives: Measure the characteristics of an emitter follower circuit. Apparatus Required: 1. 1 2N2222 NPN bipolar transistor 3. Multimeter 4. Topward power supply 5. 2 - 2.2 k and 1 - 1 k resistors 6. Breadboard Procedure:
1. Design the ckt.on breadboard as shown in fig. 2. Plot the characteristic curve for the emitter follower.

Circuit Dia.:

Points to Notice: Common-collector transistor amplifiers are so-called because the input and output voltage points share the collector lead of the transistor in common with each other, not considering any power supplies. The common-collector amplifier is also known as an emitter-follower. The output voltage on a common-collector amplifier will be in phase with the input voltage, making the common-collector a non-invertingamplifier circuit.
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The current gain of a common-collector amplifier is equal to plus 1. The voltage gain is approximately equal to 1 (in practice, just a little bit less).

Result: Plot the characteristic for the emitter follower ckt. Learning Outcome: (to be written by student in 50-60 words).

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Experiment no.:9 Experiment: To perform sampling and explain the concept of aliasing using MATLAB. Step1: start with a continuous-time cosine signal at 60 Hz. f = 60; % Hz tmin = -0.05; tmax = 0.05; t = linspace(tmin, tmax, 400); x_c = cos(2*pi*f * t); plot(t,x_c) xlabel('t (seconds)')

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Step2: Let's sample T = 1/800; nmin = ceil(tmin / T); nmax = floor(tmax / T); n = nmin:nmax; x1 = cos(2*pi*f * n*T); hold on plot(n*T,x1,'.') hold off

with a sampling frequency of 800 Hz.

The sampling frequency of 800 Hz is well above 120 Hz, which is twice the frequency of the cosine. And you can see that the samples are clearly capturing the oscillation of the continuous-time cosine.

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Step 3: Let's try a lower sampling frequency. T = 1/400; nmin = ceil(tmin / T); nmax = floor(tmax / T); n = nmin:nmax; x1 = cos(2*pi*f * n*T); plot(t, x_c) hold on plot(n*T, x1, '.') hold off

But aliasing is worse that "just" losing information. When we drop the sampling frequency too low, the samples start to look increasingly like they came from a different, lower-frequency signal.

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Step 4: Let's try 70 Hz. T = 1/70; nmin = ceil(tmin / T); nmax = floor(tmax / T); n = nmin:nmax; x1 = cos(2*pi*f * n*T); plot(t, x_c) hold on plot(n*T, x1, 'o') hold off

The samples above look like they actually could have come from a 10 Hz cosine signal, instead of a 60 Hz cosine signal. Take a look:

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T = 1/70; x_c = cos(2*pi*10 * t); nmin = ceil(tmin / T); nmax = floor(tmax / T); n = nmin:nmax; x1 = cos(2*pi*f * n*T); plot(t, x_c) hold on plot(n*T, x1, 'o') hold off

That's the heart of the "problem" of aliasing. Because the sampling frequency was too low, a high-frequency cosine looked like a lowfrequency cosine after we sampled it.

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Experiment : 10 Experiment :To study the gain of differential amplifier by varying the value of RE 1)RE= 4.1k ohms 2)RE= 82k ohms on breadboard and and simulate using pSpice Learning Objective : To demonstrate the use of Operational Amplifier for performing mathematical operation. PARTS AND EQUIPMENT: DC Power Supply Oscilloscope Function Generator LM 741 Op-amp Resistors Procedure: Difference Amplifier 1) To investigate the use of an operational amplifier in a difference amplifier configuration, connect the circuit of Figure 3. 2) With VS adjusted to produce a 1 V peak sine wave at 1 kHz, observe the output voltage VO (and VS to note the phase relationship) on an oscilloscope set to dc input coupling. 3) Sketch the output voltage waveform. Be sure to note the dc level in the output. 4) Interchange the 5 V dc power supply and the 1 V peak signal generator. Repeat procedure step 3. Circuit Diagram:

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Result: Draw the waveform(on graph paper) ,which has been observed on C.R.O. Learning Outcome: (to be written by student in 50-60 words).

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EXPERIMENT NO:11

Learning Objective: To observe the response of filters.

Low pass filter Program code: format long rp=input('enter the passband ripple'); rs=input('enter the stop band ripple'); wp=input('enter the passband frequency');
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ws=input('enter the stopband frequency'); fs=input('enter the sampling frequency'); w1=2*wp/fs;w2=2*ws/fs; [n,wn]=buttord(w1,w2,rp,rs,'s'); [z,p,k]=butter(n,wn); [b,a]=zp2tf(z,p,k); [b,a]=butter(n,wn,'s'); 69 w=0:.01:pi; [h,om]=freqs(b,a,w); m=20*log10(abs(h)); plot(om/pi,m); ylabel('gain in dB-->'); xlabel('(a)Normalised frequency-->'); Result: enter the pass band ripple 0.15 enter the stop band ripple 60 enter the pass band frequency 1500 enter the stop band frequency 3000 enter the sampling frequency 7000.

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Learning Outcome: (to be written by student in 50-60 words).


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EXPERIMENT NO: 12 Experiment: To Plot the characteristics of given FET & determine rd, gm, IDSS,VP.

Learning Objective: Characteristics of Junction Field Effect Transistor. THEORY: FET is a voltage operated device. It has got 3 terminals. They are Source,Drain & Gate. When the gate is biased negative with respect to the source, the pn junctions are reverse biased & depletion regions are formed. The channel is more lightly doped than the p type gate, so the depletion regions penetrate deeply in to the channel. The result is that the channel is narrowed, its resistance is increased, & ID is reduced. When the negative bias voltage is further increased, the depletion regions meet at the center & ID is cutoff completely. PROCEDURE: DRAIN CHARACTERISTICS: 1. Connect the circuit as per the circuit diagram. 2. Set the gate voltage VGS = 0V. 3. Vary VDS in steps of 1 V & note down the corresponding ID. 4. Repeat the same procedure for VGS = -1V. 5. Plot the graph VDS Vs ID for constant VGS.
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OBSERVATIONS 1. d.c (static) drain resistance, rD = VDS/ID. 3. Open source impedance, YOS = 1/ rd. TRANSFER CHARACTERISTICS: 1. Connect the circuit as per the circuit diagram. 2. Set the drain voltage VDS = 5 V. 3. Vary the gate voltage VGS in steps of 1V & note down the corresponding ID. 4. Repeat the same procedure for VDS = 10V. 5. Plot the graph VGS Vs ID for constant VDS. FET PARAMETER CALCULATION:

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Percentage ERROR : from data sheet find values of gmo and IDSS to get values of practically obtained values to find Percentage error

Learning Outcome: (to be written by student in 50-60words).

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Experiment No.:13 Experiment : To design and realize MOD-10 Up-Down Counter on bread board. Equipment Required: IC 7479 (D Flip-flop), IC 7400 (NAND gate), power supply. Learning Objective: To design a counter. To design a MOD-4 Up Down Conter:This is a counter with input. If X = 0, the device counts up: 0, 1, 2, 3, 0, 1, 2, 3, etc. If X = 1, the device counts down: 0, 3, 2, 1, 0, 3, 2, 1, etc.

Step 1: Derive the state diagram and state table for the circuit. Note two transitions between the state pairs: one is up and one is down. Step 2: Count the States and Determine the FlipFlop Count the States There are four states for any modulo4 counter. N = 4 The states are simple: 0, 1, 2, and 3.

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Calculate the Number of FlipFlops Required Let P be the number of flipflops. We need two flipflops. Step 3: Assign a unique P-bit binary number (state vector) to each state. Here P = 2, so we are assigning twobit binary numbers. Vector is denoted by the binary number Y1Y0.

Each state has a unique 2bit number assigned. Any other assignment would be absurd. Step 4: Derive the state transition table and the output table. There is no computed output, hence no output table. The state transition table uses the 2bit state vectors.

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Step 5: Separate the state transition table into P tables, one for each flip- flop.

Step 6: Decide on the types of flip-flops to use. When in doubt, use all JKs. Here is the excitation table for a JK flipflop

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Step 7: Derive the input table for each flip-flop

Step 8: Derive the input equations for each flip-flop The equations are based on the present state and the input. The input X produces a complication. The simplest match procedure will lead to two equations for each flipflop input: one for X = 0 and one for X = 1. Step 9: Summarize the equations by writing them in one place. Here they are. J1 = X xor Y0 J0 = 1 Step 10: Draw the Circuit As designed, it is:

K1 = X xor Y0 K0 = 1

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By following the same procedure you need to design MOD-10 UpDown Counter. Result: In tabular column, show the response of counter at every clock pulse. Learning Outcome: (to be written by student in 50-60 words).

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