FFT 32K Point Design Example v1.0.

0 README File This readme file for the Fast Fourier Transform (FFT) 32K Point Design contains information about the design example posted on the Altera Support website: http://www.altera.com/support/examples/exm-index.html Ensure that you have read the information on the design example web page before using the example.

This readme file contains the following sections: o o o o o o o o o Package Contents Tool Requirements Quartus II Compilation ModelSim Simulation Models MATLAB Models Core Directory Names Release History Design Examples Disclaimer Contacting Altera

Package Contents ================ Fast Fourier Transform (FFT) 32K Point Design Example v1.0.0 Design files in the zip download include: fft_32K.v - Top level design file implementing the 32-K point FFT parse_fft_input.v - Reorders the input sample into even and odd samples to feed into the two smaller 16K point FFT blocks fft_small.v - Wrapper file generated by the FFT IP MegaCore. The core i s configured to implement transform length of 16K, and it uses the streaming I/O data flow structure. combine_fft.v - Recombines the output of the individual 16K point FFT bl ocks using the appropriate twiddle factors fft_32K_streaming_tb.v - Testbench for RTL simulation fft_32K_streaming_vo_msim.tcl - TCL script to automate the RTL simulatio n process in ModelSim fft_32K_tb.m - MATLAB model to verify the RTL simulation results

Tool Requirements ================= This design example requires the following software package: o Quartus II 5.0 or later o FFT MegaCore v2.1.3 o ModelSim version 6.0 or later Please contact your local sales representative if you do not have one of these software tools.

Quartus II Compilation ====================== To run the compilation for the Viterbi Decoder Node Synchronization project in Q uartus II, perform the following steps: 1. Open Quartus II project: File -> Open Project -> ..\Quartus_II\fft_32K.qpf 2. Specify the FFT MegaCore Function user library: Assignments -> Settings -> Ca tegory (User Libraries) Browse to the <path>\fft-v2.1.3\lib in the Library name box. 3. Review FFT MegaCore parameters using IP Toolbench: Tools -> MegaWizard Plug-i n Manager Select "Edit an existing custom megafunction variation" and choose the FFT IP block: ../source/fft_small.v You can review the parameters by clicking on the "Parameterize" button in IP Toolbench. 4. Regenerate the FFT MegaCore files by clicking on the "Generate" button in IP Toolbench. 5. You are ready to compile the design in Quartus II: Processing -> Start Compil ation To get more details on the FFT IP MegaCore, refer to the FFT MegaCore Function U ser Guide located at: http://www.altera.com/literature/ug/ug_fft.pdf ModelSim Simulation Models ========================== In IP Toolbench, the option to generate Verilog/VHDL simulation model is enabled in the "Set Up Simulation" window. The steps to generate the simulation models from IP Toolbench are highlighted in the previous section: "Quartus II Compilation". We will be using the Verilog IP functional simulation model to verify the design in ModelSim. To run the functional simulation for the FFT 32K Point design using ModelSim, pe rform the following steps: 1. In ModelSim, change the directory to the ..\altera\design_example\FFT_32K\sou rce directory: File -> Change Directory 2. Open the fft_32K_streaming_vo_msim.tcl file and update the path to the megaco re_lib_dir setting to where the FFT IP is installed. 3. Source the TCL script file: Tools -> Execute Macro -> fft_32K_streaming_vo_m sim.tcl The TCL script sets up the ModelSim project, compiles the appropriate librari es and design files, runs the simulation, and displays the result in the waveform editor. To get more details on the IP Functional Simulation Models, refer to the Altera white paper titled "Using IP Functional Simulation Models to Verify Your System Design White Paper" located at:

http://www.altera.com/literature/wp/wp_simgen.pdf MATLAB Models ============= To verify the RTL simulation results are correct, you can compare them with the results from the provided MATLAB models found in the ..\altera\design_example\FFT_32K\MATLAB directory To run the MATLAB models, perform the following steps: 1. In MATLAB, change the directory to the ..\altera\design_example\FFT_32K\MATLA B directory 2. To generate the twiddle factors for the 32K point FFT (twiddle precision is s et to 16 bits), type the following command at the MATLAB workspace: >> [coshex, sinhex, twiddle] = gen_twiddle_factor(32768, 16); 3. To run the MATLAB model, type the following command in the MATLAB workspace: >> fft_32K_tb If the ModelSim RTL simulation results match the results from the MATLAB models, it displays the following message: "Simulation passes - Results Match". Otherwise, it displays the following error message: "Simulation fails - Results Mismatch".

Core Directory Names ==================== The default directory for your design example design is c:\altera\design_example s\fft_32K, but you can specify an alternative directory. Release History =============== Version 1.0.0 ------------Initial release

Design Examples Disclaimer ========================== These design examples may only be used within Altera Corporation devices and rem ain the property of Altera. They are being provided on an as-is basis and as an accomm odation; therefore, all warranties, representations, or guarantees of any kind (whether e xpress, implied, or statutory) including, without limitation, warranties of merchantabil ity, non-infringement,

or fitness for a particular purpose, are specifically disclaimed. Altera express ly does not recommend, suggest, or require that these examples be used in combination with any other pr oduct not provided by Altera.

Contacting Altera ================= Although we have made every effort to ensure that this design example works correctly, there might be problems that we have not encountered. If you have a question or problem that is not answered by the information provided in this readme file or the example's documentation, please contact your Altera Field Applications Engineer. If you have additional questions that are not answered in the documentation provided with this function, please contact Altera Applications: World-Wide Web: Technical Support Hotline: http://www.altera.com http://www.altera.com/mysupport/ (800) 800-EPLD (U.S.) (408) 544-7000 (Internationally)

Copyright (c) 2004 Altera Corporation. All rights reserved.