VISVESVARAYA TECHNOLOGICAL UNIVERSITY

Jnana Sangama, Machhe, Belgaum, Karnataka - 590018

A Dissertation Report on

Design and VLSI Implementation of a Tunable Concurrent Dual-
Band Receiver for a Frequency Range 10-23GHz in 180nm CMOS
Technology.

Submitted in partial fulfillment for the award of degree of

MASTER OF TECHNOLOGY
In
VLSI Design and Embedded Systems

Submitted By

ANIL KUMAR REDDY K.R
USN: 1RV08LVS02

Carried out at
M.S.R. School of Advanced Studies, Bangalore

Under the guidance of:

Internal Guide: External Guide:
Prof. Y. Gopala Rao Prof. Cyril Prasanna Raj P.
Professor, Dept. of ECE Course Manager, VSDC
R.V. College of Engineering, MSRSAS,
Bangalore Bangalore


R. V. COLLEGE OF ENGINEERING
Department of Electronics and Communication Engineering
BANGALORE 560 059
2009-2010


R. V. COLLEGE OF ENGINEERING
Mysore Road, R.V. Vidyaniketan post, Bangalore 560059

Department of Electronics and Communication Engineering



CERTIFICATE
Certified that the project work entitled Design and VLSI Implementation of a Tunable
Concurrent Dual-Band Receiver for a Frequency Range of 10-23GHz in 180nm CMOS
Technology carried out by Mr. ANIL KUMAR REDDY K.R, USN: 1RV08LVS02, a
bonafide student of fourth Semester M.Tech, at the Department of Electronics and
Communication Engineering, R.V.C.E, in partial fulfillment for the award of Master of
Technology in VLSI Design and Embedded Systems of the Visvesvaraya Technological
University, Belgaum during the year 2009-2010. It is certified that all
corrections/suggestions indicated for Internal Assessment have been incorporated in the
report deposited in the department library. The project report has been approved as it satisfies
the academic requirements in respect of project work prescribed for the said degree.



Name&Signature of the guide Name & Signature of the HOD Signature of the Principal




External Viva


Name of the Examiners Signature with Date

1.___________________ _________________

2.___________________ _________________



R.V. COLLEGE OF ENGINNERING
Mysore Road, R.V. Vidyaniketan post, Bangalore 560059

Department of Electronics and Communication Engineering



DECLARATION
I, ANIL KUMAR REDDY K.R, student of fourth semester M.Tech, VLSI Design and
Embedded Systems, Department of Electronics and Communication Engineering, R.V.
College of Engineering, Bangalore, hereby declare that the dissertation entitled Design and
VLSI Implementation of a Tunable Concurrent Dual-Band Receiver for a Frequency
range of 10-23GHz in 180nm CMOS Technology has been carried out by me and
submitted in partial fulfillment for the award of Master of Technology in VLSI Design and
Embedded Systems of the Visvesvaraya Technological University, Belgaum during the
academic year 2009-2010. Further, the matter embodied in the dissertation has not been
submitted previously by anybody for the award of any degree or diploma to any other
university.







Place: Bangalore ANIL KUMAR REDDY K.R
Date: USN: 1RV08LVS02

i

ABSTRACT

The advancement of electronics demands more integration and flexibility, and radio
frequency circuits are no exception. To meet such demands multi-mode multiband
transceivers have been proposed to expand the capabilities of a single communication
system. In addition, the concept of concurrent dual-band operation in radio frequency
electronics has been introduced to improve the overall communication throughput. However
the frequencies of the received RF signals in those architectures are fixed. This limits the
application of this architecture to a subset of emerging standards.

This project extends the previous work on concurrent dual-band receiver front-end
elements LNA and MIXER, by utilizing the concept of frequency tunability. An LNA and
one of the down conversion path mixer has been designed for 10-23GHz and above. The
receiver is capable of receiving one signal with in a low-band (10-16GHz) and the other
signal with in a high-band (16-23GHz) simultaneously. The centre frequencies of these two
signals can be selected independently with a 300MHz baseband bandwidth.

The project was done by using ADVANCED DESIGN SYSTEM from Agilent
Technologies Inc., in CMOS 180nm technology. The RF transistor models provided by
TSMC(Taiwan Semiconductor Corporation), are used for designing both LNA and Mixer.
Low Noise amplifier was designed with 1.8-V power supply and mixer was designed with
3.3-V power supply. An active termination network which terminates the gate of the input
transistor of the LNA was designed for the purpose of matching the impedances and
minimizing the overall noise figure (NF).




ii

ACKNOWLEDGEMENT

An understanding of the work like this is never the outcome of the efforts of a single person.
I take this opportunity to express my profound sense of gratitude and respect to all those who
helped me through the duration of this project. I would specially like to thank
Prof. Y. Gopala Rao, Professor, department of Electronics and Communication
Engineering, R. V. College of Engineering, Bangalore for his valuable guidance, critical
comments and constant encouragement to complete this project.
Prof. Cyril Raj Prasanna P, Course Manager, M.S.R. School of Advanced Studies,
Bangalore, for his creative ideas, valuable suggestions, encouragement, constant
involvement, inspiration and the enthusiasm with which he solved my difficulties.
Dr. B. S. Satyanarayan, Principal and Prof. S. Jagannathan, Head of the Department,
Department of Electronics and Communication Engineering, R. V. College of Engineering,
Bangalore, for giving me an opportunity to carry out my project at R.V. Centre for Cognitive
Technologies, R.V. College of Engineering, Bangalore.
Mr. Rajsekhar, who taught me the analog circuit design, without whom I would not be able
to find myself in the field of circuit design.
I am thankful to all the Faculty Members in the Department of Electronics and
Communication, R.V. College of Engineering, Bangalore, for their constant support. I would
like to thank my Parents and Friends for their moral support. Finally, I thank God, for his
blessings. Last but not least, I would like to thank those, whose name may not have been
appeared here but their efforts have not gone unnoticed.
ANIL KUMAR REDDY.K.R


iii

Table of Contents
List of Figures .................................................................................................................................... v
List of Tables .................................................................................................................................. viii
Chapter 1 .......................................................................................................................................... 1
INTRODUCTION ................................................................................................................................. 1
1.1 Work at a glance .................................................................................................................... 1
1.2 Need for this work................................................................................................................. 2
1.3 Scope of this work .................................................................................................................. 3
1.4 Top-Level block diagram......................................................................................................... 4
1.5 Overview of the thesis............................................................................................................ 5
Chapter 2 .......................................................................................................................................... 6
Review of RF Technology ................................................................................................................... 6
2.1 Introduction to RF and wireless Technology ........................................................................... 6
2.1.1 Design bottleneck ....................................................................................................... 7
2.1.2 Applications .................................................................................................................... 9
2.2 Overview of receiver architectures ...................................................................................... 10
2.2.1 Heterodyne Receivers ..................................................................................................... 10
2.2.2 Homodyne receivers...................................................................................................... 11
2.2.3 Image-Reject Receivers ................................................................................................. 12
2.3 Basic topologies of LNA and MIXER .................................................................................... 14
2.3.1 Low-Noise Amplifier ...................................................................................................... 14
2.3.2 Architectures ................................................................................................................. 14
2.3.3 Specifications of an LNA ............................................................................................... 19
2.3.4 Mixers ................................................................................. Error! Bookmark not defined.
2.3.5 General considerations .................................................................................................. 22
2.4 Inductor as an IC component................................................................................................ 29
Chapter 3 ........................................................................................................................................ 31
LITERATURE SURVEY ........................................................................................................................ 31
3.1 Architecture 1: A Tunable concurrent dual-band receiver front-end (main reference) ...... 31
3.2 Architecture 2: Concurrent dual-band CMOS Low Noise amplifiers and receiver
architectures ............................................................................................................................... 35
3.3 Architecture 3: Concurrent multiband Low Noise amplifiers ........................................... 37
iv

Chapter 4 ........................................................................................................................................ 38
STATEMENT OF THE PROBLEM ........................................................................................................ 38
4.1 Objective.............................................................................................................................. 38
4.2 Methodology ................................................................................................................... 39
4.3 Requirements .................................................................................................................. 39
Chapter 5 ........................................................................................................................................ 41
Design of LNA and MIXER ................................................................................................................ 41
5.1 LNA Design (Tunable concurrent amplifier) .......................................................................... 41
5.1.1 Architecture .................................................................................................................. 41
5.1.2 General Amplifier in common-source configuration .................................................. 42
5.1.3 Input matching ......................................................................................................... 44
5.1.4 Noise Matching ........................................................................................................ 46
5.1.5 Load circuit output matching and Gain ..................................................................... 49
5.1.6 Concurrent multiband LNA linearity measures .......................................................... 50
5.2 GILBERT cell mixer design ................................................................................................. 51
5.2.1 Transistor model and switching pair large-signal equations ...................................... 52
5.2.2 Deterministic signal processing ................................................................................. 55
5.2.3 Mixer noise figure..................................................................................................... 58
5.2.4 Distortion calculations .............................................................................................. 59
5.2.5 Cascading the driver stage and the switching pair ......................................................... 60
Chapter 6 ........................................................................................................................................ 62
IMPLEMENTATION AND RESULTS .................................................................................................... 62
6.1 LNA implementation ...................................................................................................... 62
6.1.1 Gain of the LNA ........................................................................................................ 63
6.1.2 Noise simulation results ................................................................................................ 65
6.1.3 Distrotion results ...................................................................................................... 67
6.2 Active termination ........................................................................................................... 69
Chapter 7 ........................................................................................................................................ 72
Conclusion ....................................................................................................................................... 72
Future scope................................................................................................................................ 72
Bibliography ................................................................................................................................... 73

v

List of Figures

Fig.1.1 Block-level Diagram of the present work...9
Fig.1.2 Concurrent dual-band receiver architecture in [2]..4
Fig. 2.1 RF design hexagon.8
Fig. 2.2 (a) Simple heterodyne downconversion...10
(b) inclusion of an LNA to lower the noise figure10
Fig. 2.3 (a) Simple homodyne receiver..12
(b) homodyne receiver with quadrature downconversion12
Fig. 2.4 Hartley image-reject receiver...13
Fig. 2.5 Weaver image-reject receiver...14
Fig. 2.6 Commonly used single-band LNAs
(a) Common-gate.17
(b) Common-source with inductive degeneration17
Fig. 2.7 Concurrent amplifier topologies
(a) Common-Base (CB)-CB18
(b)CB-Common Source ..18
(c) Resistor termination ...18
(d) Active termination..18
Fig. 2.8 Concurrent dual-band CMOS LNA.20
Fig. 2.9 Illustration of cross-band intermodulation..21
Fig. 2.10 (a) Simple switch used as a mixer...23
vi

(b) Implementation of switch with an NMOS device..23
Fig. 2.11 Active mixer24
Fig. 2.12 Folding of RF and image noise into the IF band.25
Fig. 2.13 Downconversion of an AM signal...26
Fig. 2.14 (a) Single-balanced mixer28
(b) Double-balanced mixer.28
Fig. 2.15 Square type Inductor29
Fig. 3.1 Concurrent dual-band receiver proposed in [2]32
Fig. 3.2 (a) Input matching ...33
(b) conversion gain..33
Fig. 3.4 Noise figure of the receiver system including GaN LNA34
Fig. 3.5 An architecture for concurrent dual-band receiver...36
Fig. 5.1 Concurrent amplifier schematic41
Fig.5.2 General model for a single-stage amplifier in common-source configuration.43
Fig. 5.3 Simplified small-signal model of Fig. 5.1 when bulk is ac grounded..43
Fig. 5.4 A CMOS Gilbert cell52
Fig. 5.5 A single-balanced active CMOS mixer53
Fig. 5.6 Waveforms P
0
(t) and P
1
(t)56
Fig. 5.7 Numerically evaluated conversion gain of the switching pair c..57
Fig. 6.1 Low-Band LNA with biasing scheme shown..63
Fig. 6.2 Simulated gain of low-band amplifier
(a) with 253fF 64
(b) with 168fF, at the output...64
Fig. 6.3 Source noise voltage..65
Fig. 6.4 Simulated noise results
vii

(a) Total noise at the output 66
(b) Input referred noise figure.66
Fig. 6.5 Frequency domain spectrum
(a) Input ..68
(b) Output (also indicates IM2 distortion)...68
Fig. 6.6 Third-order inter modulation...69
Fig. 6.7 Circuit diagram of active termination.70
Fig. 6.8 Active Termination
(a) Input-impedance (Z
11
).71
(b) Input-reflection coefficient(S
11
)..71









viii


List of Tables

2.1 Typical mixer characteristics...23
6.1. DC operating condition62




1

Chapter 1
INTRODUCTION

This chapter provides the motivation and an overview of the front end of a concurrent
dual-band receiver [2]. As the technology is advancing, the integration of more and more
number of devices on to a single chip has become feasible. Particularly with the
improvements occurred at the component level (layout) has enabled the RF industry to
include more functionalities in a single receiver system. For example, in the past, the receiver
is capable of receiving only one signal at a time in the band of operation, but now receivers
are being designed to receive two signals at a time without significantly increasing area and
footprint. The challenge in design is to get less area as possible and provide the best
performance in the entire band of operation. At the end of this chapter, how this thesis is
organized to make one to understand the work presented in a most effective way is presented.
1.1 Work at a glance
The main objective of the project is to design an LNA (Low-Noise Amplifier) and
one mixer, which is called Low-Band mixer. This mixer performs the usual frequency
translation in addition to providing sufficient gain to combat with the noise. The LNA will
separate the incoming total RF (Radio Frequency) signal band into two separate bands (High-
Band and Low-Band), which are then processed further by the mixer, each signal having its
own down-conversion path. An active termination is needed for the LNA to maximize the
power transfer from the antenna and also to lower the noise figure. The signal will be
received in 10-23GHz band and the LNA separates this band into low-band and high-band.
Low-band extends from 10-16GHz and high-band is from 16-23GHz. Because the LNA is
operating in band of frequencies and the output load is tuned according to the RF signal
received at the input, this amplifier can also be called as Tunable Concurrent Amplifier
(TCA) [2]. Fig.1.1 shows the block-diagram of the work presented here which is also a part
of the typical front-end of a receiver.
2


Fig.1.1 Block-level Diagram of the present work
1.2 Need for this work
Standard receiver architectures, such as superhetero-dyne and direct conversion [4],
accomplish high selectivity and sensitivity by narrow-band operation at a single input
frequency. These modes of operation limit the systems available bandwidth and robustness
to channel variations and thus its functionality. On the other hand, wide-band modes of
operation are more sensitive to out out-of-band unwanted signals (blockers) due to transistor
nonlinearity. These out-of-band blockers can severely degrade receivers sensitivity.
The diverse range of modern wireless applications necessitates communication
systems with more bandwidth and flexibility. More recently, dual-band transceivers [2] have
been introduced to increase the functionality of such communication systems by switching
between two different bands to receive one band at a time. While switching between bands
improves the receivers versatility (e.g., in multi-band cellular phones), it is not sufficient in
the case of a multi-functionality transceiver where more than one band needs to be received
simultaneously (e.g., a multi band cellular phone with a global positioning system (GPS),
receiver and a Bluetooth interface). Using conventional receiver architectures [4] [5],
simultaneous operation at different frequency bands can only be achieved by building
multiple independent signal paths with an inevitable increase in the cost, footprint, and power
dissipation. Although there have been efforts to minimize the number of additional
RF in
Active
termination
Tunable
Concurrent
Amplifier
High-Band
Low-Band
f
L1
f
H1
3

components used for the second band of operation (e.g., for adding GPS to a CDMA phone),
none of these efforts attempt simultaneous reception of more than one band.
The work presented in [1], introduces a new concurrent dual-band architecture which
is capable of simultaneous operation at two different frequencies without dissipating twice as
much power or a significant increase in cost and footprint. This concurrent operation can be
used to extend the available band-width, provide new functionality, and/or add diversity to
battle channel fading. The concurrent operation is realized through an elaborate frequency
conversion scheme [3], in conjunction with a novel concurrent dual-band low-noise
amplifier. These new concurrent multiband LNAs provide simultaneous narrow-band input
matching and gain at multiple frequency bands, while maintaining low noise.
The above discussion outlines that as we advance in technology, there is a need for
adding more functionalities in a single receiver system without increasing the power
dissipation and area. It can also be said that increasing market demand for consumer
electronics is the major cause, forcing the engineers to invent new architectures and be in
phase with the industry.
1.3 Scope of this work
As mentioned before, if we want to integrate more functionality in a single receiver
system, then this type of architecture for front-end of a receiver is inevitable keeping in view
the cost and the footprint among many other things such as, sensitivity and versatility. One
application where these concurrent dual-band receivers are extensively used is a phased-
array system. A phased-array system is one in which an array of receivers are placed to
mitigate multi-path loss, particularly used in high-performance designs such as radar
systems. Very large-scale phased arrays (~10
6
elements) can provide tremendous array gain,
noise improvement, and beam forming capabilities [6], for a variety of applications such as
radar and communications. Excellent repeatability in CMOS technology offers dramatic cost
and size reduction in such systems.


4

1.4 Top-Level block diagram
Fig.1.2: Concurrent dual-band receiver architecture in [2]
The above figure shows the top-level block diagram of the project and also indicates the
present work (enclosed in square box). The detail of the design is presented in [2], which is
actually designed for phased-arrays systems. It operates across a tri-tave (6-18GHz)
bandwidth with a nominal 17-25dB conversion gain, worst-case -15dBm IIP3 (third-order
input intercept point), and worst-case -24.5dBm ICP1dB (1dB gain compression point
referred to input). The reference [2], extends the previous work on concurrent dual-band
receivers by introducing frequency tenability. As a proof of concept, a receiver element is
designed for 6-18GHz scalable phased-array receiver. The receiver is capable of receiving
one signal within a low band (6-10.4GHz) and the other signal within a high band (10.4-
18GHz) simultaneously. The centre frequencies of these two signals can be selected
independently with a 300MHz baseband bandwidth. In the final implementation, a GaN
broad-band low-noise amplifier (LNA) was placed in front of this receiver for pre-
amplification. A single-input, double-output tunable concurrent amplifier (TCA) amplifies
the RF input signal and separates into its low-band and high-band components. Both the
high-band and low-band have their own down-conversion signal paths. If the second LO
frequency is chosen to be half of the first LO frequency image signals will always fall out of
the 6-18GHz frequency range; thus they can be filtered out easily by an off-chip filter. A
RF in
Active
Termination
High-Band
Low-Band
TCA
fH1
fL1
fH2_I
fH2_Q
fL2_I
fL2_Q
BB_HI


BB_HQ


BB_LI


BB_LQ
PRESENT
WORK
5

total of six mixers are required to offer quadrature outputs for complex modulation scheme.
Two frequency synthesizers are used for LO generation, where implementation details can be
found in [3].
1.5 Overview of the thesis
The next chapter is devoted to discuss some of the basic features of the transmitters
and receivers. Various types of transmitters and receivers are presented where much of the
attention is given to receivers. This chapter enables the readers to understand the importance
of each block in receiver, namely, LNA, mixer...etc. and also the design metrics that need to
be take care of for good reception. Various types of power amplifiers are also discussed. At
the end of the chapter, an introduction to the design presented in this work is given.
Chapter 3 will try to give some of the recent advances in concurrent dual-band
receivers. Various architectures of concurrent receivers are presented and limitations in each
of them have been identified. This chapter helps us to set the design specifications very
clearly and also gives a hint on what can be done in the future.
Chapter 4 deals with the problem statement and chapter 5 and 6 discusses design and
implementation details. Chapter 7 shows the results obtained. The thesis concludes in
Chapter 8 with a discussion of achieved results and suggestion for future work.





6

Chapter 2
Review of RF Technology

This chapter provides the basic concepts in RF Design and gives an overview of receiver
architectures. Various design specifications such as IP3, CP1dB, conversion gainetc. are
also discussed. Various topologies of LNAs and Mixers are given and their noise
characteristics have been identified. Effects of nonlinearity and how the nonlinearity is
quantified are discussed in great detail. The purpose of this chapter is not to discuss
exhaustively about receiver architectures, but, direct the reader to a good reference which
covers a lot of details about the ongoing concept. At the end of the chapter, an introduction to
the design of the presented work is given.
2.1 Introduction to RF and wireless Technology
Wireless technology came to existence when, in 1901, Guglielmo Marconi
successfully transmitted radio signals across the Atlantic Ocean. The consequences and
prospects of this demonstration were simply overwhelming. The possibility of replacing
telegraph and telephone communications with wave transmission through the ether
portrayed the exciting future. However, while two-way wireless communication did
materialize in military applications, wire-less transmission in daily life remained limited to
one-way phone conversations would still go over wires for many decades.
The invention of the transistor, the development of Shannons information theory,
and the conception of the cellular system - all at Bell Laboratories - paved the way for
affordable mobile communications, as originally implemented in car phones and eventually
realized in portable cellular phones.
Market surveys show that in the United States more than 28,000 people join the
cellular phone system every day, motivating competitive manufacturers to provide phone sets
with increasingly higher performance and lower cost. In fact, the present goal is to reduce
both the power consumption and price of cell phones by 30% every year- although it is not
clear for how long this rate can be sustained. A more glorious prospect, however, lies in the
7

power of two-way wireless communication when it is introduced in other facets of our lives:
home phones, computers, facsimile, and television. While an immediate objective of the
wireless industry is to combine cordless and cellular phones so as to allow seamless
communications virtually everywhere, the long-term plan is to produce an omnipotent
wireless terminal that can handle voice, data, and video as well as provide commuting power.
Other luxury items such as the global positioning system (GPS) are also likely to become
available through this terminal sometime in the future. Personal communication services
(PCS) are almost here.
2.1.1 Design bottleneck
Multidisciplinary Field In contrast to the other types of analog and mixed-signal
circuits, RF systems demand a good understanding of many areas that are not directly related
to the integrated circuits (ICs). Most of these areas have been studied extensively for more
than half a century, making it difficult for an IC designer to acquire the necessary knowledge
in a reasonable amount of time. Even at present, the literature pertaining to RF design
appears in more than 30 journals and conferences.
Owing to this issue, traditional wireless system design has been carried out at
somewhat disjoint levels of abstraction: communication theorists create the modulation
scheme and baseband signal processing; RF system experts plan the transceiver architecture;
IC designers develop each of the building blocks; and manufacturers glue the ICs and other
external components together. In fact, architectures are planned according to the available
off-the-shelf components, and ICs are designed to serve as many architectures as possible,
leading to a great deal of redundancy at both system and circuit levels.
RF Design Hexagon RF circuits must process analog signals with a wide dynamic
range at higher frequencies. It is interesting to note that the signals must be treated as analog
even if the modulation is digital or the amplitude carries no information. The trade-offs
involved in the design of such circuits can be summarized in the RF design hexagon shown
in fig. 2.2, where almost any two of the six parameters trade with each other to some extent.
Our observation is that, while digital circuits directly benefit from the advances in IC
technologies, RF circuits do not as much. This issue is exacerbated by the fact that RF
8

circuits often require external components-for example, inductors-that are difficult to bring
onto the chip even in modern processes.


Figure 2.1 RF design hexagon

Design Tools Computer-aided analysis and synthesis tools for RF ICs are still in
their infancy, forcing the designer to rely on experience, intuition, or insufficient simulation
techniques to predict the performance. For example, nonlinearity, time variance, and noise in
RF circuits usually require studying the spectrum of signals, but the standard ac analysis
available in SPICE uses only linear, time-invariant models. Thus, circuits are simulated in the
time domain so as to include nonlinear or time-variant effects, and the resulting waveforms
are subsequently transformed to the frequency domain to obtain the spectrum. The difficulty
is that the time-domain simulation must be run for a long period to resolve closely spaced
frequency components. In addition spectral averaging techniques may be necessary if random
noise is used in the time domain analysis.
Another issue in simulating RF circuits relates to external components that cannot be
modeled by typical devices in SPICE. For example, surface acoustic wave (SAW) filters,
used in both receive and transmit path, exhibit input and output impedances that can be
characterized only by scattering (S) parameters-essentially a table of numbers. Modeling
Power Noise
Linearity
Supply
Voltage
Gain
Frequency

9

such circuits with RLC networks provides a first-order approximation, but it may not predict
effects such as instability and impedance mismatch.
2.1.2 Applications
In addition to the familiar wireless products such as pagers and cellular phones, RF
technology has created many other markets that display a great potential for rapid growth,
each presenting its own set of challenges to RF designers.
WLANs Communication among people or pieces of equipment in a crowded area
can be realized through a wireless local area network (WLAN). Using frequency band around
900 MHz and 2.4 GHz, WLAN transceivers can provide mobile connectivity in offices,
hospitals, factories, etc., obviating the need for cumbersome wired networks. Portability and
re-configurability are prominent features of WLANs.
GPS The use of GPS to determine ones location as well as obtain the directions
becomes attractive to the consumer market as the cost and power dissipation of GPS
receivers drop. Operating in the 1.5-GHz range, such systems are under consideration by
automobile manufacturers, but they may be available as low-cost hand held-held products
sometime in the near future.
RF IDs RF identification systems, simply called RF IDs, are small, low-cost tags
that can be attached to the objects or persons so as track their position. Applications range
from luggage to troops in military operations. Low power consumption is especially critical
here as the tags life time may be determined by that of a single battery. RF ID products in
the 900-MHz and 2.4-GHz range have recently appeared in the market.
Home Satellite Network The programs and services available through satellite
television have attracted many consumers to home satellite networks. Operating in the 10-
GHz range, these networks require the addition of a dish antenna and a receiver to a
television set and directly competes with cable TV.
10

2.2 Overview of receiver architectures
2.2.1 Heterodyne Receivers
Filtering a narrow channel that is centered at high frequencies and is accompanied by large
interferes demands prohibitively high Qs (quality factor). In heterodyne (hetero-different
and dyne-to mix) architectures, the signal band is translated to much lower frequencies so as
to relax the Q required of the channel-select filter. Illustrated in Fig. 2.2(a), the translation is
carried out by means of a mixer, which is viewed here as a simple analog multiplier. To bring
the center frequency from
1
to
2
, the signal first mixed with a sinusoid A
0
cos
0
t, where

0
=
1
-
2
, thereby yielding a band around
2
and another around 2
1
-
2
. A low-pass filter
then removes the latter. This operation is called downconversion mixing or simply
downconversion. Because of its typical high noise, the downconversion mixer is preceded
by a low-noise amplifier [Fig. 2.2(b)]. The sinusoid is generated by a local oscillator (LO).


Figure 2.2 (a) Simple heterodyne downconversion, (b) inclusion of an LNA to lower the
noise figure.
Called the intermediate frequency (IF), the centre of the downconverted band (
2
) is a
critical parameter, bearing trade-offs with many other aspects of the performance.
LPF






A0cos0t
0
2 1
(a)
LNA LPF
A0cos0t
(b)
11

2.2.2 Homodyne receivers
When the RF spectrum is directly translated to the baseband during the first downconversion
then it is called homodyne, direct-conversion, or zero-IF architecture. Shown in Fig.
2.3 is a simple homodyne receiver, where the LO frequency is equal to the input carrier
frequency. Note that channel selection requires only a low-pass filter with relatively sharp
cutoff characteristics. The circuit of Fig. 2.3(a) operates properly only with double-sideband
AM signals because it overlaps positive and negative parts of the input spectrum. For
frequency and phase-modulated signals, the downconversion must provide quadrature
outputs [Fig. 2.3(b)] so as to avoid loss of information. This is because the two sides of FM
and QPSK spectra carry different information and must be separated into quadrature phases
in translation to zero frequency.
The simplicity of the homodyne architecture offers two important advantages over a
heterodyne counterpart. First, the problem of the image is circumvented because
IF
=0. As a
result, no image filter is required, and the LNA need not drive a 50- load. Second, the IF
SAW (surface acoustic wave) filter and subsequent downconversion stages are replaced with
low-pass filters and baseband amplifiers that are amenable to monolithic integration. Despite
its simplicity, this architecture is not so popular due to a number of issues that are not so
serious in heterodyne receivers. Some of them are:
Channel Selection Rejection of out-of-channel interferes by an active filter is more difficult
than by a passive filter, fundamentally because active filters exhibit much more noise-
linearity-power trade-offs than do their passive counterparts.
DC Offsets since in a homodyne topology the downconverted band extends to zero
frequency, extraneous offset voltages can corrupt the signal and, more importantly, saturate
the following stages.
In addition to the above two, I/Q mismatch, LO leakage, even-order distortion, and flicker
noise will also affect the performance of homodyne architectures.

12


Figure 2.3(a) Simple homodyne receiver, (b) homodyne receiver with quadrature
downconversion.
2.2.3 Image-Reject Receivers
Hartley Architecture An image-reject architecture originating from a single-side band
(SSB) modulator introduced by Hartley in 1928 is illustrated in Fig. 2.4. Hartleys circuit
mixes the RF input with quadrature phases of the local oscillator, sin
LO
t and cos
LO
t, low-
pass filters the resulting signals, and shifts one by 90
0
before adding them together. To
understand the underlying principle, suppose the input signal is

cos

cos

, where the first term represents the desired channel and the
second term the image. Without loss of generality, we assume low-side injection:

. Multiplying by the LO phases and neglecting high-frequency components, we

obtain the following signals at points A and B, respectively:

sin

sin

(2.1)

cos

cos

(2.2)
LPF




cos0t
0 0
(a)
(b)
LNA
LPF
LPF
LNA
cos0t
sin0t
I
Q
13

Writing (2.1) as

sin

. (2.3)
And utilizing the result sint = -cost, we have

cos

. (2.4)
Upon addition of

and

, we obtain

at the output. Thus the

RF signal is downconverted with no corruption by then the image. The key point here is that
the signal components at B and C have the same polarity, whereas the image components
have opposite polarities. This occurs because the 90
0
shift operation distinguishes between

and

.

Figure 2.4 Hartley image-reject receiver.
Weaver Architecture In the Hartley architecture, we noted that quadrature
downconversion followed by a 90
0
phase shift produces in the two paths the same polarities
for the desired signal and opposite polarities for the image. Illustrated in Fig. 2.5, the weaver
architecture replaces the 90
0
stage by a second quadrature mixing operation to perform
essentially the same function. Without loss of generality, we assume
2
<<
1
. The spectrum
at point A is convolved with j[(+
2
)-(-
2
)] 2, yielding at point C the translated replicas
with no factor j. similarly the spectrum at point B is convolved with [(+
2
)+(-
2
)]/2
and hence is translated both up and down in frequency. Subtracting the spectrum at point C
from that at point D, we note that the replicas of the image that fall in the band of interest
LPF
LPF 90
0
RF input
Sin
LO
t
cos
LO
t
A
B
C
IF output
output
14

cancel each other, yielding the desired signal with no corruption. Since the downconverted
spectrum sill contains the image at +
2
+
IF
and
2
-
IF
, an output low-pass filter is required
to select only the desired band.

Figure 2.5 Weaver image-reject receiver.
2.3 Basic topologies of LNA and MIXER
2.3.1 Low-Noise Amplifier
The first stage of a receiver is typically a low-noise amplifier (LNA), whose main function is
to provide enough gain to overcome the noise of subsequent stages (such as a mixer). Aside
from providing this gain while adding as little noise as possible, an LNA should
accommodate large signals without distortion, and frequency must also present a specific
impedance, such as 50 , to the input source. This last consideration is particularly important
if a passive filter precedes the LNA, since the transfer characteristics of many filters are quite
sensitive to the quality of the termination. The following section discusses some of the
commonly used LNA topologies and performance parameters that characterize the design.
2.3.2 Architectures
The bipolar junction transistor was the first solid-state active device to provide practical gain
and NF (noise figure) at microwave frequencies. In the seventies, breakthroughs in the
development of field-effect transistors (FETs) (e.g., GaAs MESFET) led to higher gain and
lower NF than bipolar transistors for the frequencies in the range of several gigahertzes.
Currently, advanced FETs and bipolar transistors still compete for lower NF and higher gain
LPF
LPF
RF input
Sin
1
t
cos
1
t
A
B
C
IF output
output
Sin
2
t
Cos
2
t
15

at frequencies in excess of 100 GHz. Examples are the high electron-mobility transistors
(HEMTs), such as pseudomorphic high electron-mobility transistors (pHEMTs),
metamorphic high electron-mobility transistors (MHEMTs), as well as heterojunction bipolar
transistors (HBTs), built using a variety of semiconductor materials (e.g., GaAs, InP, Si,
SiGe). Traditionally, very low-noise amplifiers at high frequencies have been made using
transistors with high electron mobility and high saturation velocity on high-resistivity
substrates for the following principal reasons.

1. Higher carrier mobility and peak drift velocity result in a higher transistor
transconductance and shorter carrier transit time for a given current, thus allowing for
the reduction of the dc current for the same transconductance (gain) in transistors
which lowers the input-referred noise and, hence, the NF. This gives compound
semiconductors a significant advantage over silicon, as for instance, the electron
mobility and the peak drift velocity are typically six and two times larger,
respectively, for GaAs when compared to silicon.

2. Higher carrier mobility also results in lower parasitic drain and source series resistors.
The parasitic source resistance can be a major contributor to the overall NF of certain
LNAs, such as those used for satellite communications.

3. Due to mostly technological limitations, the series input resistance of silicon-
based transistors is usually higher than those of compound semiconductors. In
particular, the lower resistance of the metal gate of GaAs MESFETs compared to
higher resistance of the poly-silicon gate in MOSFETs and thin bases in bipolar
transistors, result in a lower NF for GaAs transistors.

4. The loss properties of on-chip passive components can have a significant effect on the
noise and gain performance of the LNAs. High-resistivity substrates minimize the
substrate-loss components. As the loss and noise are closely related through the
fluctuation-dissipation theorem of statistical physics, the energy loss reduction
translates to a lower NF for the amplifier.
16

There are two types of LNAs based on the frequency (ies) of operation and are.

1 Single band low noise amplifier.
2 Concurrent dual band (multi- band) LNA.

A single band LNA will provide gain and noise match at single frequency of interest [7] [8],
whereas, a dual band or a multi band LNA will provide the gain and noise match at two or
more frequencies of interest. Some of the commonly used single band LNA topologies are
shown below [2].

The common-gate configuration shown in fig. 2.6 (a) uses the resistive part looking
into the source of the transistor to match the input to a well-defined source impedance (e.g.,
50). This impedance is 1/ (g
m
+g
mb
) in the case of a MOSFET, where g
m
and g
mb
are
transconductances of the top-gate and back-gate transistors, respectively. However, it can be
shown that the NF is lower bounded to 2.2 dB for a perfectly matched long-channel CMOS
transistor unless a transformer is used at the input.
These LNA topologies will provide gain and input match at one particular frequency
of the interest. In other words, they are narrow-band. In a single band LNA, passive networks
are used to shape the response of the wide-band transconductance of the active device in the
frequency domain to achieve and matching at the frequency of interest. This concept can be
generalized to multiple frequency bands noting that the intrinsic transconductance of the
active device is inherently wide-band and can be used at multiple frequencies
simultaneously. Fig. 2.7 shows the architectures of a concurrent dual band LNA.
17


Figure 2.6 Commonly used single-band LNAs (a) Common-gate (b) Common-source with
inductive degeneration.
Fig. 2.7 shows some of the candidate topologies for such a kind of amplifier, often
called Tunable Concurrent Amplifier (TCA). The TCA needs to provide good broad band
matching and good isolation between its two outputs. The topology in Fig.2.7 (a) consists of
two common base (CB) transistors. By sizing the two CB transistors carefully, good
matching and isolation between two resonant tanks can be simultaneously achieved.
However, noise generated from M
1
will not be isolated from M
2
, which results in poor noise
performance. Fig. 2.7 (b) replaces one of the CB transistors in Fig.2.7 (a) with a common
source (CS) cascade topology. The benefits of doing so are that a larger g
m1
can be used for
input matching, which improves noise figure of the upper path; that the noise generated in M
2

is isolated from the upper path, and that possibly a larger g
m2
can be used to improve the
noise figure of the lower path, at the cost of higher power consumption. The topology in Fig
2.7 (c) uses a simple 50 resistor for input matching. This way, the relationship between the
transistor g
m
and the input matching can be decoupled; thus, a large g
m
can be used for both
paths to improve noise figure. However, the termination resistor contributes noise power, and
V
out

V
bias

V
in
V
dd

L
1

C
1

L
s

V
in
V
dd

L
1

C
1

L
s

V
out

L
g

18



Figure 2.7 Concurrent amplifier topologies (a) Common-Base (CB)-CB (b) CB-Common
Source (c) Resistor termination (d) Active termination
M2
gm2
M1
gm1
RF in
Vbias2
Vbias1
HB out
LB out
Vg
50
M2
gm2
M1
gm1
Vbias2
Vbias1
HB out
LB out
RF in
Vbias3
50
(d)
(c)
gm1
gm2
Vbias
Vbias
HB out
LB out
M1
M2
RF in
M2
gm2
Vbias2
Vbias1
RF in
(a) (b)
19

the overall power consumption is higher than the circuit in Fig. 2.7 (b). In Fig. 2.7 (d) an
active termination replacing the 50 resistor is used to reduce the noise contribution.
The architecture shown in Fig. 2.8 consists of a dual-resonance input matching
network, and a dual-resonance output network. For concurrent operation, resonant
frequencies of these two networks need to be matches. To make the dual-band LNA tunable
variable capacitors need to be implemented (Cg, Cgs, C
1
and C
2
), which have a typical tuning
range of three (e.g., MOS varactors). Under this constraint, a tunable dual-resonance input
matching network and output network can be designed to cover any frequency in the band of
interest.
However, there are three major problems of this architecture: firstly, the high band
and the low band frequencies cannot be independently controlled, secondly, the achievable
region of operation is only a small portion of the desired operation region. Thirdly, matching
the resonant frequencies of the two networks is difficult.
2.3.3 Specifications of an LNA
In this section, we will discuss the performance specifications of an LNA. As mentioned
before, the goal is to gain up the input signal, while adding as little noise as possible.
Voltage Gain: (Av)
Defined as, the ratio of output voltage to the input voltage. Typically, this value will
be in the range of 15dB to 30dB.
Input Matching (S
11
):
In RF designs, we will always consider the Power gain of the system. From the
maximum power transfer theorem, it can be shown that maximum power will be delivered to
the load when source and load impedances are complex conjugate to each other. As shown in
fig .2, a common-gate topology will offer a real input impedance which can be varied by
varying the transconductances of the device and hence the width. A common-source with
inductive degeneration will also offer a real input impedance to the source.

20



Figure 2.8 concurrent dual-band CMOS LNA
Noise Figure (NF):
In many analog circuits, the signal-to-noise ratio (SNR), defined as the ratio of the
signal power to the total noise power, is an important parameter. In RF design, on the other
hand, even though the ultimate goal is to maximize the SNR for the received and detected
signal, most of the front-end receiver blocks are characterized in terms of their noise figure
rather than the input-referred noise. This is partly for computational convenience and partly
from tradition. The most commonly accepted definition for NF is
Noise figure =

................................................. (2.5)

The noise figure will have a lower bound which depends on the topology used for LNA.
Typically, it will be in the range of 2.2dB to 6dB (max).

Lg
Cg
L
bond

pad
M1
M2
Vbias
L
1
L
2
C
1
C
2
Vout
Vin
V
dd

21

Input IP3 & Input CP1:
Linearity is an important measure in the receiver as it determines the largest signal
that can be handled by the receiver and controls its dynamic range. The linearity of a single-
band LNA is often described using its nth-order intercept point IPn and 1-dB compression
point CP1. In a concurrent multiband LNA, the IP3 and CP1 in each band with no significant
signal in the other bands are still important and will be referred to as IP3
inband
and CP1
inband
,
respectively. However, its concurrent multiband nature, other non-linearity measures should
also be considered. A strong signal in any band can compress the LNA gain at all
frequencies. A cross-band compression measure can be defined as the signal power in band
A that causes a 1-dB drop in the small signal gain in band B which will be denoted as
CP1
A>B
. in addition to this cross-band compression, in-band signals from desired bands can
mix due to amplifiers nonlinearity and cause in-band undesired signals, as shown in Fig. 2.9
.
Figure 2.9 Illustration of cross-band intermodulation.
2.3.4 Mixers
Most circuit analysis proceeds with the assumption of linearity and time invariance.
Violations of those assumptions, if considered at all, are usually treated as undesirable.
However, the high performance of modern communication equipment actually depends
critically on the presence of at least one element that fails to satisfy linear time invariance:
mixer. Mixers are still ideally linear but depend fundamentally on a purposeful violation of
time invariance. For example, the superheterodyne receiver uses a mixer to perform an
Band A Band B
Multi-band LNA
f1
f2
n. f1- m. f2
22

important frequency translation of signals. Armstrongs invention has been the dominant for
70 years because this frequency translation solves many problems in one fell swoop.
In superheterodyne architecture, the mixer translates an incoming RF signal to
a lower frequency, known as intermediate frequency (IF). Although Armstrong originally
sought this frequency lowering simply to make it easier to obtain the requisite gain, other
significant advantages accrue as well. As one example, tuning is now accomplished by
varying the frequency of a local oscillator, rather than by varying the center frequency of a
multi pole band pass filter. Thus, instead of adjusting several LC networks in tandem to tune
to a desired signal, one simply varies a single LC combination to change the frequency of a
local oscillator (LO). The intermediate frequency stage can then use fixed bandpass filters.
Selectivity is therefore determined by these fixed-frequency IF filters, which are much easier
to realize than variable frequency filters.
2.3.5 General considerations
In this section we will describe some of the general considerations about the mixer. Mixers
perform frequency translation by multiplying two signals (and possibly their harmonics).
Downconversion mixers employed in the receive path have two distinctly different inputs,
called the RF port and the LO port. The RF port senses the signal to be downconverted and
the LO port senses the periodic waveform generated by the local oscillator. This can be seen
in the simple circuit of Fig. 2.10 (a), where the output is equal to the RF input when S
1
is on
and zero when S
1
is off. This operation can also be viewed as multiplication of the RF signal
by a rectangular waveform. Note that the circuit is linear, time variant system with respect
to the RF port and a nonlinear, time-variant system with respect to the LO port. This is true
for most Downconversion mixers of interest.
The signal amplified by the LNA (and possibly filtered by an image-reject filter)
is applied to the RF port of the mixer. Thus, this port must exhibit sufficiently low noise and
high linearity, the latter because nearby interferes are amplified by the LNA and hence can
produce stronger intermodulation products. If the circuit of Fig. 2.10 (a) incorporates a MOS
switch [Fig. 2.10 (b)], then the on-resistance of the transistor contributes noise. Furthermore,
as the RF input signal varies, the gate-source overdrive voltage of M
1
and hence its on-
resistance change, introducing nonlinearity in the voltage division between M
1
and R
L.
23




Figure 2.10(a) Simple switch used as a mixer, (b) Implementation of switch with an NMOS
device.
Listed in Table 2.1 are performance parameters of typical Downconversion mixers.
With a noise figure of 12 dB and an IIP
3
of +5 dBm, a mixer can be preceded by an LNA
having a gain of approximately 15 dB with acceptable degradation in the overall noise and
nonlinearity.

TABLE 2.1 Typical mixer characteristics
NF 12 dB
IIP +5 dBm
Gain 10 dB
Input Impedance (Heterodyne) 50
Port-to-Port Isolation 10-20 dB


Passive and Active Mixers The circuit of Fig. 2.10 (b) is an example of passive
mixers because it does not provide any gain. The loss of the circuit can be calculated by
noting that, if the LO signal has a 50% duty cycle, then the RF input is multiplied by a
dimensionless square wave toggling between 0 and 1. Such a waveform has a fundamental at
W
LO
with an amplitude equal to sin (/2)/ = 1/. Since the IF signal results from convolving
the input spectrum with this fundamental, the voltage gain of the circuit is equal to 1/.
V
IF

V
RF

R
L
V
LO

V
RF

R
L
M1
S
1

24

Active mixers, by contrast, generally provide gain. Shown in Fig. 2.11 is an
example, where the RF input varies the drain current of M
1
, and M
2
and M
3
is function as a
switching pair driven by the LO. Thus, the drain current of M
1
is in essence multiplied by a
square wave as it is routed to R
1
and R
2
alternatively. The proper choice of device size and
bias currents provide significant voltage gain in this circuit.

Figure 2.11 Active mixer
By virtue of their gain, active mixers reduce the noise contributed by subsequent
stages and are widely used in RF systems. Passive mixers, on the other hand, typically
achieve a higher linearity and speed and find application in microwave and base station
circuits.
Conversion Gain The gain of mixers must be carefully defined to avoid confusion. The
Voltage conversion gain of a mixer is defined as the ratio of the rms voltage of the IF
signal to the rms voltage of the RF signal. Note that these two signals are centered around
two different frequencies. The voltage conversion gain cam measured by applying a
sinusoidal at W
RF
and examining the amplitude of the downconverted component at W
IF.

The power conversion gain of a mixer id defined as the IF
power delivered to the load divided by the available RF power from the source. If the input
impedance and the load impedance of the mixer are both equal to the source impedance, for
V
LO
R
1
R
2
V
RF
V
IF
M
1
M
3
M
2
25

example 50, then the voltage conversion gain and power conversion gain of the mixer are
equal when expressed in decibels.
SSB and DSB Noise Figures The noise figure of mixers is often a source of great confusion.
For simplicity, let us consider a noiseless mixer with unity gain. As shown in Fig. 2.12, the
spectrum sensed by the RF port consists of a signal component and the thermal noise of R
S
in
both the signal band and the image band. Upon Downconversion, the signal, the noise in the
signal band, and the noise in the image band are translated to W
IF
. Thus, the output SNR is
half the input SNR if the input frequency response of the mixer is the same for the signal
band and the image band. In other words, the noise figure of a noiseless mixer is equal to 3
dB.

Figure 2.12 Folding of RF and image noise into the IF band
The above measurement provides the single-sideband noise figure (SSB NF) of the mixer.
The term SSB indicates that the desired signal spectrum resides on only one side of the LO
frequency, a common case in heterodyne systems. Now, consider the homodyne
Downconversion of an AM signal by means of a single noiseless mixer. In this case, the
input and output signal-to-noise ratios are equal, giving a noise figure of 0 dB. This is called
the double-sideband noise figure (DSB NF) so as to emphasize that the input signal
spectrum on both sides of
LO.
R
s
X
Y

LO

LO

IF



Thermal
noise
Signal
Band
Image
Band
Spectrum at X
Spectrum at Y
26


Figure 2.13 Downconversion of an AM signal
In summary, the SSB noise figure of a mixer is 3 dB higher than the DSB
noise figure if the signal and the image bands experience equal gains at the RF port of a
mixer. Typical noise figure meters measure the DSB NF and predict the SSB value by simply
adding 3 dB.
Port-to-Port Isolation The isolation between each two ports of a mixer is critical. The LO-
RF feedthrough results in LO leakage to the LNA and eventually to the antenna, whereas the
RF-LO feedthrough allows string interferes in the RF path to interact with the local oscillator
driving the mixer. The LO-IF feedthrough is important because if substantial LO signal exists
at the IF output even after low-pass filtering, then the following stage may be desensitized.
Finally, the RF-IF isolation determines what fraction of the signal in the RF path directly
appears in the IF, a critical issue with respect to the even-order distortion problem in
homodyne receivers.
Single-Balanced and Double-Balanced Mixers If a mixer accommodates a differential LO
signal but a single-ended RF signal, it is called single-balanced, an example being the
topology shown in Fig. 2.14 (a). If a mixer operates with both differential LO and an RF
input, then it is called double balanced, the active version of which assumes the form of a
Gilbert cell [Fig. 2.14 (b)].
R
s
X
Y

LO

LO

0



Thermal
noise
Signal
Band
Spectrum at X
Spectrum at Y
27

The single balanced configuration exhibits less input-referred noise for a given power
dissipation than the double-balanced counterpart. However, the circuit is more susceptible to
noise in the LO signal. The double-balanced mixer generates less even-order distortion, thus
relaxing the half IF issue in heterodyne receivers and lowering the beat components in
homodyne architectures. Nevertheless, since the RF signal processed by the LNA (and
possibly the image-reject filter) is usually single-ended, one of the input terminals of the
double-balanced mixers is simply connected to a bias voltage. This in turn creates different
propagation timesi.e., phase shiftsfor the two signal phases amplified by M
1
and M
2
in
Fig 2.14 (b), leading to finite even-order distortion.
Mixer Spurious Response In general, a mixer generates various cross-products of the RF
and LO signals and their harmonics. The frequency of the resulting components can be
expressed as | m.
RF
n.
LO
|, where m and n are integers. A difficult task in receiver design
is to ensure that, except for |
LO

RF
|, such components do not fall in the IF band. Owing
to nonlinearities in the RF path, it is possible that harmonics of the interferes beat with
harmonics of the LO, corrupting the downconverted signal. The spurious free response for
various combinations of m and n is usually analyzed with the aid of computer programs.





28


(a)

(b)
Figure 2.14(a) Single-balanced mixer, (b) Double-balanced mixer


M1
M6
M5
M4
M3
M2
VRF
VLO
VI
VDD
V
LO
R
1
R
2
V
RF
V
IF
M
1
M
3 M
2
V
DD
29

2.4 Inductor as an IC component
From the point of view of RF circuits, the lack of a good a good inductor is by far the most
conspicuous shortcoming of standard IC processes. Although active circuits can sometimes
synthesize the equivalent of an inductor, they always have higher noise, distortion, and power
consumption than real inductors made with some number of turns of wire.
The most widely used on-chip inductor is the planar spiral, which can assume any
shapes; circular, octagonal, square, and hexagonal. The choice of shape is more often made
on the basis of whether the layout tool accommodates non-Manhattan geometries. Octagonal
or circular spirals are moderately better than squares (typically on the order of 10%) and
hence are favored when layout tools permit their use. The most common realizations use the
top most metal layer for the main part of the inductor (occasionally with two or more levels
strapped together to reduce resistance) and provide a connection to the center of the spiral
with a crossunder implemented with some level of metal. These conventions arise from quite
practical considerations: the top most metal layers in an integrated circuit are usually the
thickest and thus generally the lowest in resistance. Furthermore, maximizing the distance to
the substrate minimizes the parasitic capacitance between the inductor and the substrate. An
example for the square type of inductor is shown below.

Figure 2.15 Square type Inductor
d
out
d
in
s
30

The inductance of an arbitrary spiral is a complicated function of geometry, and accurate
calculations require the use of field solvers or Greenhouses method. However, a (very)
crude zeroth-order estimate, suitable for hand calculations, is

........ (2.6)
Where L is in henries, n is the number of turns, and r is the radius of the spiral in meters. This
equation typically yields numbers on the high side, but generally within 30% of the correct value (and
often better than that). For shapes other than square spirals, multiply the value given by the spiral
formula by the square root of the area ratio to obtain a crude estimate of the correct value. Thus, for
circular spirals, multiply the square-spiral value by

, and by 0.91 for octagonal

spirals.
BONDWIRE INDUCTORS In addition to planar spirals, bondwires are also
frequently used to make inductors. Because standard bondwires are 1 mil (thats 0.001
inches, or about 25 m) in diameter, they have much more surface area per length than
planar spirals and hence less resistive loss, and therefore higher Q values. Also, they may be
placed well above any conductive planes to reduce parasitic capacitances (thereby increasing
the self-resonant frequency) and decrease the loss due to induced image currents. If we may
neglect the influence of nearby conductors (i.e., if we assume that the return currents are
infinitely far away), then the DC inductance of a bondwire is given by:

.. (2.7)





31

Chapter 3
LITERATURE SURVEY

This chapter presents some of the recent concurrent dual-band receiver architectures
published in the literature. This chapter enables us to understand what a concurrent dual-band
receiver must be capable of and the type of LNAs used in order get the concurrency in the
operation.
3.1 Architecture 1: A Tunable concurrent dual-band receiver front-end
(main reference)
This reference [2] presents a study and design of tunable concurrent dual-band receiver.
Different system architectures and building blocks have been compared and analyzed. A
tunable concurrent dual-band receiver front end has then been fabricated and characterized. It
operates across a tri-tave 6-18GHz bandwidth with a nominal 17-25dB conversion gain,
worst-case -15dBm IIP3, and worst-case -24.5dBm ICP1dB.
The implemented IC (integrated circuit) was mounted on a printed circuit board
(PCB) for mechanical stability during measurements. Dual-band RF inputs were applied
through a coplanar waveguide probe, and baseband output pads are connected to SMA
connectors through PCB traces and bond-wires. All measurement results are calibrated with
input reference plane at the TCAs GSG pads, and the output reference plane at the SMA
connectors.
Fig. 3.1 shows the proposed architecture of this work. A single-input, double-output
tunable concurrent amplifier (TCA) amplifies the RF input signal and separates into its low-
band and high-band components. Both the high-band and low-band have their own down-
conversion signal paths. If the second LO frequency is chosen to be half of the first LO
frequency image signals will always fall out of the 6-18GHz frequency range; thus they can
be filtered out easily by an off-chip filter. A total of six mixers are required to offer
quadrature outputs for complex modulation scheme. Two frequency synthesizers are used for
LO generation, where implementation details can be found in [3].
32


Figure 3.1 Concurrent dual-band receiver proposed in [2].
Fig. 3.2(a) shows the measurement results of the receiver input matching. S
11
is insensitive to
supply voltage variations and the TCA tuned load bit settings. Fig. 3.2(b) shows the nominal
conversion gain (black thick line) and variable gain range (the range between the upper and
the lower dotted line). Since both the TCA and the high-band RF mixer are tuned circuits, at
a given set of RF inputs, each tuned load is set to be in-band, meaning its resonant frequency
is matched to the corresponding operating RF and IF frequencies. The conversion gain
decreases with frequency in the high-band due to the large parasitic capacitance at the output
of the RF mixers. However, this can be recovered by setting the VGA to higher gain. In
addition, the isolation between high-band and low-band signal path is better than 47dB.
Third-order intercept point was measured by standard two-tone tests, and the
measurement results are shown Fig. 3.3. Improved IIP3 at higher frequency is due to the
conversion gain drop. The output referred in-band 1dB compression point is also shown in
Fig.3.3. The solid line and the dashed line in Fig. 3.4 show the noise figure of the whole
receiver with or without the GaN LNA, respectively. The noise figure increases at higher
frequencies because the gain of the RF mixer drops due to its excessive parasitic capacitance
at its port. The receiver excluding baseband VGAs consumes 17 mA from 1.2V power
RF in
Broad-band
matching
High-Band
Low-Band
TCA
fH1
fL1
fH2_I
fH2_Q
fL2_I
fL2_Q
BB_HI


BB_HQ


BB_LI


BB_LQ
33

supply, and 81.2 mA from a 2.5V power supply. Each of the open-drain VGAs consumes
33.5 mA under nominal operation.





Figure 3.2 (a) Input matching (b) conversion gain

34


Figure 3.3 In-band Input-referred IP3, and output-referred 1dB compression at maximum
gain.

Figure 3.4 Noise figure of the receiver system including GaN LNA.


35

3.2 Architecture 2: Concurrent dual-band CMOS Low Noise amplifiers
and receiver architectures
In this paper, a new concurrent dual-band receiver architecture is introduced that is capable
of simultaneous operation at two different frequency bands. The concurrent operation results
in higher bandwidth, lower total power dissipation and less sensitivity to channel variations.
The architecture uses a novel concurrent dual-band low noise amplifier (LNA), combined
with an elaborate frequency conversion scheme to reject the image bands. A general
methodology for the design of concurrent LNAs is provided that makes it possible to achieve
simultaneous narrowband gain and matching at multiple frequencies. The methodology is
demonstrated by implementing an integrated dual-band concurrent LNA using 0.35m
CMOS transistors. The LNA provides narrow-band gain and matching at 2.45GHz and
5.25GHz bands, simultaneously. It drains 4 mA of current and achieves voltage gains of
14dB and 15.5dB, input return losses of 25dB and 15dB, and noise figures of 2.3dB and
4.5dB at these two bands, respectively.
The objective is to devise a receiver that can simultaneously receive
the signal at two different frequency bands with maximum reuse of power and building
blocks. The first gain stage in a concurrent dual-band receiver is its LNA. Traditional single-
band LNAs use a single or cascade transistor stage to provide wideband transconductance
and combine it with proper passive resonant circuitry at the input and output to shape the
frequency response and achieve gain and matching at the single band of interest [l]. A very
important observation here is that the transconductance of the active device is still wideband
and can be used to provide gain and matching at other frequencies of interest without any
penalty in power dissipation. This observation leads to a compact and efficient front-end for
a concurrent dual-band receiver which consists of a dual-band antenna [2][3], followed by a
monolithic dual-band filter [4] and a concurrent dual-band LNA that provides simultaneous
gain and matching at two bands, as shown on the left-hand side of Fig. 3.5. A detailed
approach to the design of such multi-band LNAs will be described in [1]. The frequency of
the first local oscillator (LO) that appears after the LNA and performs the first down
conversion determines the image frequency (ies) and plays an important role in the
performance of the system. For a non-concurrent receiver, it has been proposed to choose the
36

first LO frequency half-way between the two frequency bands and select the band of interest
by choosing the appropriate sideband produced by an image-separation mixer [5].

Figure 3.5 An architecture for concurrent dual-band receiver.

Although this method is sufficient for the non-concurrent approaches, it will suffer
from some serious shortcomings if used for a concurrent receiver, where the LNA amplifies
the signal in both of the desired bands. This is because one band is the image of the other and
there is no attenuation of the image by either the antenna or the filter. The situation is
exacerbated by the LNA gain in the image band. In this scenario, one is solely relying on the
image rejection of the single sideband receiver, which is limited by the phase and amplitude
mismatch of the quadrature LOs and the signal paths, and is insufficient in a concurrent
receiver. An alternative approach that does not suffer from the above problem and, in fact,
significantly improves the image rejection is to use an offset LO. The LO frequency is offset
from the midpoint of the two bands in such a way that the image of the first band falls at the
notch of the front-end transfer function. The attenuation at the notch frequency is determined
by the compounded attenuation of the dual-band antenna, filter, and LNA. Similarly, the
image of the second band will fall outside the pass-band of the front end and will be
attenuated, accordingly. Using a quadrature first LO makes the stage fit to act as the first half
of any single-sideband image reject architecture, such as Weaver [6]. Since the receiver has
to demodulate two bands concurrently, two separate paths must be used eventually. Each
f
LO1
I
Q
f
LO2
f
LO3
I
I
Q
Q
A
B
RF in
Dual-band
LNA
37

path comprises of the second half of the image-reject architecture, as shown Fig. 3.6 which
provide further image- rejection. This architecture eliminates an extra antenna, a front-end
filter, an LNA, and a pair of mixers, which in turn result in power, footprint and area savings.
At the same time large image rejection in excess of that of the single-sideband receiver is
achieved through diligent frequency planning.
3.3 Architecture 3: Concurrent multiband Low Noise amplifiers
The concept of concurrent multiband low-noise-amplifiers (LNAs) is introduced. A
systematic way to design concurrent multiband integrated LNAs in general is developed.
Applications of concurrent multiband LNAs in concurrent multiband receivers together with
receiver architecture are discussed. Experimental results of a dual-band LNA implemented in
a 0.35 m CMOS technology as a demonstration of the concept and theory is presented. In a
single-band LNA, passive networks are used to shape the response of the wide-band
transconductance of the active device in the frequency domain to achieve gain and matching
at the frequency of interest. This concept can be generalized to multiple frequency bands
noting that the intrinsic transconductance of the active device is inherently wide-band and
can be used at multiple frequencies simultaneously.

It is crucial to note the fundamental differences between the concurrent and the
existing non-concurrent approaches. In conventional dual-band LNAs, either one of the two
single-band LNAs is selected according to the instantaneous band of operation, or two (three)
single-band LNAs are designed to work in parallel using two (three) separate input matching
circuits and two (three) separate resonant loads. The former approach is non-concurrent,
while the latter consumes twice (three times) as much power if used in a concurrent setting.
The other existing approach is to use a wide-band amplifier in the front-end. Unfortunately,
in a wide-band LNA, strong unwanted blockers are amplified together with the desired
frequency bands and significantly degrade the receiver sensitivity. In this section, we present
an analytical approach to the design of a general class of integrated concurrent multiband
LNAs. The concurrent LNA is proposed as a solution to the aforementioned problems in a
concurrent receiver.
38

Chapter 4
STATEMENT OF THE PROBLEM

This chapter gives an overview of what this work is comprised of. Stating the objective and
the methodology that has been followed during the course of the work, this chapter is
concluded by mentioning the requirements that are needed for successful completion of the
project.
4.1 Objective
The main objective is to design an LNA and one downconversion mixers and an active
termination network that comes before the LNA. The LNA must be capable of receiving the
signals in the band extending from 10-23GHz and separating them into Low-Band (10-
16.5GHz) and High-Band (16.5-23GHz) in addition to providing sufficient gain and input
matching (S
11
). Cascade type LNA topology is used to design the amplifier and at the output
a 3-bit tuned load is placed which can be tuned to the frequency of the signal received at the
input. Three capacitors are used to accomplish this task and three transistors are used o select
the combination of the capacitors needed. An inductor is also used at the output, and as one
can expect, the output frequency that we are interested in, is the resonant frequency of the
combination of the load selected. The design procedure and implementation details can found
in the next chapter (chapter 5).
After the LNA the signal will be separated into its Low-Band (LB) and High-Band
(HB), as explained earlier. The two mixers will now process these signals. Each band is
having its own downconversion path. One mixer is working in 10-16.5GHz band (called low-
band mixer) and the other one is working in 16.5-23GHz (called high-band mixer). Both
these mixers have their input at RF frequency, so these mixers are also called RF mixers.
After the mixers, an IF (intermediate frequency) buffer is placed to buffer the IF output given
by the mixers. It is also used to provide some more gain in the downconversion path to
protect the high-impedance node at the output of the mixer. Active double-balanced type
mixer topology is used for both the mixers. The design procedure and complete
implementation details can found in the next chapter (chapter 5).
39

4.2 Methodology
Just like any other design methodology, we start with the device characterization. The device
is characterized by g
m
/I
d
vs. V
od
, g
m
/C
gs
vs. V
od
, and device intrinsic gain plots, where g
m
is
the transconductance of the device, I
d
is the current flowing through the device, C
gs
is the
gate-source capacitance, and V
od
is the gate-source overdrive voltage g
m
/I
d
plot gives the
information that for a particular choice of device transconductance and overdrive voltage,
how much current is needed to flow through the device for a particular device width. g
m
/Cgs

plot gives the speed with which we can operate the device for the given transconductance and
overdrive voltage. The choice of device models greatly affects the device performance. The
device models used here are provided by TSMC

(Taiwan Semiconductor Corporation).

After completing the device characterization, we start designing the LNA and mixers
by deriving the specifications from the system level [2]. The topology chosen and the design
procedure are given in detail in the next chapter. After the completion of the design, we
simulate and verify the results in order meet the specifications. The procedure to simulate
LNAs and mixers is given in great depth in references [9] [10].
4.3 Requirements
The following are the typical requirements needed:
1. Any tool which supports RF designs. Most popular are the CADENCE VIRTUOSO
ADE (analog design environment) and ADVANCED DESIGN SYSTEM (ADS) by
AGILENT Technologies Inc. We used ADS to simulate the circuits.
2. TSMC (Taiwan Semiconductor Manufacturing Corporation) 180nm RF design kit is
also available for the Agilent ADS tool. Though the two device models mentioned
above are perfectly valid, to make sure that we are getting the same results in both of
the tools, we designed the circuits in Agilent ADS tool also.
3. The model which is used must have continuous derivatives in all regions of operation.
Failing this requirement would lead to inaccurate judgment of Intercept points and 1-
dB compression points. Plotting the derivatives of device transconductance vs. gate-
source overdrive voltage would help us to resolve this issue.
4. The most important design requirement is good understanding of the RF concepts.
The best starting point would be the book by Thomas Lee, Stanford University, and
40

Behzad Razavis RF MICROELECTRONICS. Apart from these, to understand the
design details, various references are mentioned wherever required.























41


Chapter 5
Design of LNA and MIXER

This chapter outlines the design procedure of LNA (low-noise amplifier) and mixers. Various
design specifications are defined and derived analytically. Specifically, how the concurrency
in the operation of the receiver is achieved is discussed in detail. Cascode type topology is
used for the design of LNA and Gilbert cell topology is used for mixer design.
5.1 LNA Design (Tunable concurrent amplifier)
5.1.1 Architecture


Figure 5.1 Concurrent amplifier schematic

42

The above shown figure is the architecture used for realizing the low-noise amplifier. As
indicated in Fig. 5.1, cascode type topology has been utilized. 1 3-bit select load is used to tune
to the desired frequency. The switch has been modeled as having a finite resistance in the on
state and having a finite capacitance in the off state. This capacitance can affect the resonant
frequency of the LC tank selected. To overcome this problem, the load capacitance has been
chosen such that the total capacitance (including that of the switch) together with the load
inductance will give the desired frequency. Also shown, the matching network used to get
good input matching and an active termination in order to overcome the noise. The following
sections detail the design procedure and related equations of the TCA (tunable-concurrent
amplifier).

5.1.2 General Amplifier in common-source configuration
In this section, we use a general model for an amplifier in the common-source configuration to
obtain an equivalent circuit for the input impedance and a general expression for the gain at
multiple frequencies. This equivalent circuit will be used to achieve simultaneous power and
noise matching in a concurrent multiband LNA. Fig. 5.2 shows a transistor with arbitrary gate
impedance Zg, gatesource impedance Zgs, source impedance Zs, gatedrain impedance Zgd,
and load impedance Z
L
. The impedances shown in Fig. 5.2 also include the transistors
inherent passive components (e.g., Cgs, Cgd). General expressions for input impedance and
voltage- gain of this amplifier are given by

.. (5.1)

(5.2)

Fig. 5.3 is the equivalent small-signal model for the circuit in Fig. 5.2 where the bulk is ac-
grounded. To simplify this equivalent model, we define Zs
'
=Zs|| Zsb and Z
L
'
= Z
L
||Zdb, where
Zsb, Zdb are the sourcebulk and drainbulk impedances. The transistors output resistor, r
o
,
can be neglected, because it is relatively large compared to relatively small impedances in an
43

RF circuit. Then, the small-signal input impedance and the voltage gain of this circuit are
given by (5.1), and (5.2) respectively.


Figure 5.2 General model for a single-stage amplifier in common-source configuration.

.


Figure 5.3 Simplified small-signal model of Fig. 5.1 when bulk is ac grounded

Gate
Source
Drain
Z
g
Z
L
Z
s

Z
gd
-g
mb
V
s
g
m
V
g
V
gs
r
0
Z
gs
Z
in

V
in

V
out

Z
g

Z
gs

Z
gd

Z
S

Z
L

44



5.1.3 Input matching
The input of the LNA is either fed directly by the antenna or is connected to the antenna
through a band-pass filter, a diplexer/duplexer, or both. In any case, the impedance looking
into the input of the LNA should be power matched (i.e., complex conjugate matched) to the
impedance of the preceding stage for maximum signal power transfer. Additionally, it is
essential to provide the correct impedance to the preceding stage to satisfy its nominal
specifications (e.g., band-pass filter characteristics, such as roll-off, etc., depend on filter
loading). The expressions given above can be further simplified if we assume that Zgd is
much larger than the other impedances. This assumption neglects the effect of the transistors
intrinsic Cgd and its associated Miller effect. Then, the input impedance expression of
simplifies to

(5.3)


This expression will be used to design multiband input matching networks.
Theoretically, the input impedance of any stable amplifier with a nonzero real part
can be perfectly matched to any arbitrary source impedance (with a positive real part) for a
single frequency using lossless passive components at the input of the amplifier. Equation
(5.3) can be used to generalize this power match concept to multiple frequencies. It can be
used to generate numerous topologies to achieve simultaneous impedance matching at
multiple distinct frequencies. In an LNA, it is also necessary to achieve a noise match at the
input for the frequency (ies) of interest to minimize the NF. In the following section on noise
matching, we will demonstrate that one way to minimize the NF of the amplifier of Fig. 5.2
is by designing the passive network so that it satisfies

................................................................................................................ (5.4)
45

at multiple frequencies of interest. However, this can only be achieved using lossless passive
components. Therefore, in practice, one should minimize, to its smallest real part, R
min
.
Having satisfied the above condition, the input impedance will be

.. .. (5.5)


Theoretically, a large number of passive topologies for Zgs and Zs
'
can provide input
impedance matching at multiple frequency bands. One particular example which is of great
practical value is when Zgs is just the intrinsic gatesource capacitance, Cgs and, hence, Zs
'

has to be an inductor as in the single-band common-source LNA. For negligible passive loss
(R
min
0) and a real-value impedance, (e.g., 50 for most practical cases), the source inductor
is given by

(5.6)


This will result in a passive network for Zg that will minimize

for all the

frequencies of interest. The optimum source inductance depends on

and, hence, process

parameters. Ignoring Cgd, in a deep short-channel CMOS biased in the velocity saturation
region,

is approximately given by

(5.7)
Where

is electron mobility in the channel, Ec is the critical field, V

at
is the saturation
velocity, and L is transistors channel length. Therefore, for a given deep sub-micrometer
CMOS technology with constant channel length where carriers are velocity saturated, the
value of

is almost fixed and is independent of the bias current and the device size. For a
bipolar transistor,

has a current dependency. However, if junction capacitors are

negligible for a transistor biased with a high collector current, this current dependency is
46

small and again the value of

is independent of bias current. In a long-channel CMOS,

depends on the bias current and the device width and so will

.
5.1.4 Noise Matching
An important design parameter in receiver design, which is the measure of receiver noise, is
the noise factor (also known as NF, when expressed in decibels). The definition of the noise
factor of any transducer (e.g., LNA, mixer, filter, etc.) given by

(5.8)
where N
total
is the total noise power per unit bandwidth available at the output port at a
corresponding output frequency when the noise temperature of its input termination is a
standard 290 K .Any noisy two-port network can be represented by a noiseless two-port
network with input equivalent voltage e
n
and current sources i
n,.
Then, the noise-factor F will
be given by

(5.9)
Where Y
s
is the reference source admittance (e.g., Y
s
=1/50 ) for the NF and i
s
is the noise
current associated with it.

Now, we will find an expression for the NF of the general single-stage common-
source amplifier of Fig. 5.1. While it is possible to include all the different noise sources in
the calculations, we will make certain simplifying assumptions to keep the expressions
tractable. In the following calculations, we assume that the only dominant noise sources are
the drain and gate-induced current source i
nd
and i
ng
for the MOS transistor. It is also
assumed that passive impedances shown in Fig. 5.1 do not contribute any noise. The noise of
any physical input resistance r
g
at the input appears as an additional term r
g
/R
S
in the
expressions for F. Practically, r
g
are very important in determining the NF, as well as input
impedance of the LNA. They determine the minimum noise-factor (Fmin) of a transistor.

47



In case of an MOS transistor, noise current densities are known to be

= 4KT

(5.10)
Where c
*
is the complex conjugate of the correlation coefficient between gate and drain noise
currents.
To gain more design insight, for the time being let us focus on the effect of the drain current
noise, which is often the most dominant noise source in the amplifier. In this case, the noise
factor is given by

F = 1+

(5.11)
Since Zg, Zgs, and

are assumed to be passive networks, and Y

S
is a real admittance in all
the practical cases (e.g., 1/50 ), the minimum value of the first term of the product above
occurs when

.... . (5.12)
for all frequency bands,
i
. For this to be possible, all three passive networks should be
lossless. Therefore, in practice, one should choose the passive networks Zg,Zgs, and Z
S
'
to
minimize at each center frequency of interest,
i
. We will refer to this minimum real value at
each center frequency as R
min
(
i
). This is the same constraint that we referred to in the
previous subsection on the input matching of concurrent LNAs. The above-mentioned
general constraint for a concurrent multiband LNA should also work in the more
48

straightforward case of a single-band LNA. In this case, if Zgs is simply the gatesource
capacitance, and if Zg and Z
S
'
networks consist of single inductors, we can satisfy (5.12) by
setting

(5.13)
Where is the center frequency of interest in the single-band LNA. In addition to the
minimization of at each center frequency of interest, (5.11) suggests that using higher Zgs
and higher device transconductance can lower the NF further. One simple way of obtaining a
large Zgs is to keep the Zgs network as simple as the intrinsic gatesource capacitance, i.e.,
using no explicit component between the gate and the source. Taking the effect of all noise
sources, we can express the noise figure for an MOS device as follows.

(5.14)

Note that no assumptions about the single-band operation of the amplifier were made and,
hence, these equations are valid in the general case of a concurrent multiband LNA.

In the case of MOS transistors, compared to bipolar, there are more degrees of freedom in the
design, such as finger width W
f
and the number of fingers n
f
. It is clear that the fingers should
be as short as the technology allows minimizing r
g
for any given overall device width, W. Of
course, we can control W by adjusting n
f
(W= n
f.
W
f
). A larger W results in a smaller r
g
and,
hence, a smaller gate-resistance noise contribution. However, while a larger increases the
transistors transconductance g
m
, it also increases the drain current consumption and has a
negative overall effect on drain noise current contribution to the amplifiers NF. Therefore,
there is an optimum W and, hence, an optimum n
f
resulting in the lowest NF in this topology.
This approach does not compromise the voltage gain significantly, as it is shown in the next
section that the voltage gain of this amplifier is independent of device transconductance and
the number of fingers to the first order.
49

The other parameter of interest is the gatesource overdrive voltage Vod=Vgs-Vt, of
the MOS transistor. For small values of Vod, g
do
and g
m
increase linearly with Vod until
velocity saturation occurs and then becomes constant. Meanwhile, g
do
and consequently the
device noise keep increasing with Vod. As can be seen from (5.14), the drain noise
contribution to F is proportional to g
do
and inversely proportional to the square of g
m
.
Therefore, NF drops with Vod in the beginning and then rolls back up.
5.1.5 Load circuit output matching and Gain
While the input and output of a stand-alone LNA usually need to be matched to 50 to
transfer the power efficiently using transmission lines, the output of an LNA in an integrated
front-end does not necessarily have to be matched in a similar way. Usually an integrated
LNA drives the capacitive input of the first down-conversion mixer in the receiver chain and,
hence, it is not desirable to match the output to a real impedance. This difference also
explains why it is more common to report some form of power gain (e.g., G
p
or S
21
) for
stand-alone LNAs, and the voltage gain A
v
for the LNAs in integrated front-end circuits. The
NF expression for the receiver using voltage gain and input-referred voltage sources can be
derived when the output of the LNA is not impedance matched.
Assuming no body effect (g
mb
) and a small Cgd (Zgd=), the voltage gain expression
simplifies to

(5.15)

Which can be used to calculate the gain at all frequencies. At the frequency bands of interest
where (5.12) holds for minimum NF, the gain equation further reduces to

.. (5.16)


If Zs is implemented as an inductor to provide the real part of the input impedance, its value
is given by (5.6) which is almost independent of the bias current in a deep velocity-saturated
short-channel MOS transistor and also in a bipolar transistor. Therefore, voltage gain given
by (5.16) will be independent of current to the first order. In this case, increasing the bias
50

current will only increase the NF with no significant improvement in A
v
. To achieve the
highest gain and selectivity at the frequencies of interest, it is desirable to use a multi-
resonant load at the output whose impedance is maximum at the frequencies of interest.
5.1.6 Concurrent multiband LNA linearity measures
Linearity is an important measure in the receiver as it determines the size of the largest
signal that can be handled by the receiver and controls its dynamic range. The linearity of a
single-band LNA is often described using its nth-order intercept point and 1-dB compression
point CP1. In a concurrent multiband LNA, the IP3 and CP1 in each band with no significant
signal in the other bands are still important and will be referred to as IIP3
inband
and CP1
inband
,
respectively. However, due to its concurrent multiband nature, other nonlinearity measures
should also be considered. A strong signal in any band can compress the LNA gain at all
frequencies. A cross-band compression measure can be defined as the signal power in band
A that causes a 1-dB drop in the small-signal gain in band B which will be denoted as
CP1
A>B.
In addition to this cross-band compression, in-band signals from different desired
bands can mix due to the amplifiers nonlinearity and cause in-band undesired signals. We
show the input intercept point associated with this cross-band inter-modulation as IPn
crossband
,
where n is the order of nonlinearity leading to this effect.
We can derive expressions for the nonlinearity measures of concurrent multiband
LNAs in terms of device nonlinearity similar to the case of single-band LNAs. We can also
relate these cross-band nonlinearity measures to the single-band ones.
Assuming the amplifier output has a third-order polynomial dependence on the input

(3.16)

we can calculate the in-band and cross-band 1-dB compression points

(3.17)

.... (3.18)
51

As can be seen from the above equations, the cross-band 1-dB compression occurs 3 dB
earlier than the in-band one. This suggests that, for the same amount of nonlinearity, a
concurrent multiband LNA needs to be 3 dB more linear than its single-band counterpart. If
different applications at various bands have maximum signal powers, the concurrent
multiband LNA has to be 3 dB more linear for the strongest signal when compared to a
single- band LNA.
5.2 GILBERT cell mixer design
In this section, we presented the design of a Gilbert cell mixer. Most of the design issues
discussed here are in general, such that the designer can make use the normalized graphs
provided, for any given technology.

The Gilbert cell, shown in Fig. 5.4, was initially designed with bipolar transistors [11] to
operate as a precision multiplier, but it has been used widely as a mixer with the transistors
driven by the strong local oscillator (LO) signal acting as switches. The operation principle is
the same in CMOS technology. It is a doubly balanced mixer, meaning that if only one of the
LO or input signals is applied, the output is ideally zero. The output signal ideally does not
contain a component at the LO frequency and its harmonics. There exists high port-to-port
isolation among the input, LO, and output ports, alleviating problems such as LO leakage to
the antenna and reducing the amount of output filtering required. The Gilbert cell consists of a
transconductance or driver stage, which is a differential pair biased at a fixed operating point, and
two switching pairs driven by the strong LO signal. Resistive or tuned tank loads can be
connected at the output, and degeneration can be used to linearize the transconductance stage.
The output current is

(3.19)
where the above currents are defined in Fig. 5.4. If i
s
is the small-signal current at one output
branch of the driver stage, assuming ideal switching, during the first half of the LO period

while during the other half

This alternation in the sign of the output

signal provides the desired mixing effect.

52


Figure 5.4 A CMOS Gilbert cell

It will be helpful below to consider half a Gilbert cell, shown in Fig. 5.5. This circuit is a
single-balanced mixer itself, meaning that the output current

is zero when only an input

signal is applied without the LO signal. The transconductance stage is a single transistor.
From (3.19), the output of the Gilbert cell is the difference of the output currents of two
single-balanced mixers, and therefore the results carry over easily from the single- to the
double-balanced case.
5.2.1 Transistor model and switching pair large-signal equations
The simple square-law MOSFET model is not accurate for modern short-channel
technologies, and a better approximation for the IV relation of a MOS transistor is [12]

.. (3.20)
In (3.20), is the drain current,

is the gate-source voltage, and

is the threshold voltage

of the device. Parameter depends on the technology and the size of the device and is
proportional to the channel width. Parameter models to a first order the source series
53


Figure 5.5 A single-balanced active CMOS mixer.

resistance, mobility degradation due to the vertical field, and velocity saturation due to the
lateral field in short-channel devices. It depends on the channel length and is independent of
the body effect.
Since a large ac drive is applied to the switching pair, the bias of M1 and M2 is not fixed but
varies periodically with time. When a differential voltage greater than a certain value

is
applied between the gates of the two transistors, one of them switches off. When the absolute
value of the instantaneous LO voltage

is lower than

, the current of the driver stage is

shared between the two devices. In this case, it is desirable to find the drain current of each
transistor for a given LO voltage and driver-stage bias current. We will assume that the
output conductance of the devices can be neglected, and therefore M3 can be modeled with
an ideal current source. We will also assume that the load of M1 and M2 is such that they
remain in saturation during the part of the LO period that they are on. The large-signal
behavior of the switching pair is described by the system of two equations given by

(3.21)
and

.... (3.22)
where

is the K parameter of M1, M2, and

are the gate-source voltages of M1,

M2. If we normalize

and

as follows:
54

.. (3.23)

(3.24)
and also let

. (3.25)
then (3.21) and (3.22) become

.. (3.26)

.. (3.27)
Equations (3.26) and (3.27) can be transformed to one nonlinear equation with

as the
unknown, which can be solved rapidly with an iterative numerical method. Considering a
positive

the desired value of

lies between

and

(3.28)

which is the value of

when the whole bias current passes through M1.With the

transformation of (3.23) and (3.24), the normalized current of each transistor can be found in
terms of

and

independent of the technology parameters. For , for example

(3.29)

The transconductance of each transistor will be needed below and can be calculated
as the derivative of I with respect to

from (3.20), or in normalized form as the derivative

of

with

from (3.29). It is worth noticing that no specific value of

is needed to
calculate the drain current of M1 and M2. The behavior of the switching pair is independent
of

and therefore to a first order is independent of the body effect and the common-mode
LO voltage. This observation allows us to omit the small-signal body transconductance
below.
55

In the following analysis, some performance parameters of the switching pair will be given in
terms of the normalized bias current

and LO amplitude

, with being the real LO

amplitude. The subthreshold conduction of the transistors has been neglected. Therefore, if
the devices operate at very low current density, the prediction will be inaccurate; especially
for low LO amplitude where the transistors do not act as switches and their behavior depends
on their IV characteristics.
5.2.2 Deterministic signal processing
If capacitive effects are ignored, the output current of the single-balanced mixer of Fig. 5.5 is
a function of the instantaneous LO voltage

and the current at the output of the driver

stage

, with

being the bias current and

the small-signal current.

.. (3.30)

Since

is small, a first-order Taylor expansion gives

.. (3.31)
or

(3.32)

Both

and

are periodic waveforms, depicted in Fig. 5.6. As can be seen from

(3.19) and (3.32), in a doubly balanced structure with perfect device matching,

is
eliminated. During the time interval when the LO voltage is between

and -

and both
transistors are on,

and

depend on

, and the IV characteristics of the

transistors. The small-signal current in each branch is determined by current division, and
one can see that

(3.33)
56


Figure 5.6 Waveforms P
0
(t) and P
1
(t)

Where

t and

t represent the instantaneous small-signal transconductances of M1

and M2. According to (3.32), a signal component of is multiplied by the waveform

and therefore the frequency spectrum of the corresponding output is

.. (3.34)

Where

is the LO frequency,

are the Fourier components of

, and X (f) is the

frequency spectrum of .
It is worth noticing that with good device matching,

, with

being
the LO period, and hence

has only odd-order frequency components. The same

observation can be made for

. Usually the term for or is of interest,

57

corresponding to shifting up or down the input signal in the frequency domain by one
multiple of the LO frequency, and in this case

represents the conversion

gain of the switching pair alone. Since

t where v

t is the input voltage

signal at the gate of M3 and

is the transconductance of M3, the conversion gain of the

single-balanced mixer in transconductance form is

. (3.34)

For high LO amplitude,

approaches a square waveform and c approaches 2/ Fig. 5.7

shows c, evaluated numerically as a function of the normalized bias current

and LO
amplitude

for a sinusoidal LO waveform. Assuming

, as it should be for
proper mixer operation, an estimate for c can be obtained by approximating

with a
straight line during

. (3.35)
Where the sinusoidal LO waveform

sin

(3.36)

and

is given by (3.28). It is easy to observe that the conversion gain of the Gilbert cell is
also given by (3.34). If degeneration or an input matching network is used, the
transconductance of the driver stage is not

but can be calculated with linear circuit

techniques and multiplied with c to provide the conversion gain.

58


Figure 5.7 Numerically evaluated conversion gain of the switching pair c.
5.2.3 Mixer noise figure
There are various sources of noise present in the mixer, such as, noise from the driver stage,
thermal noise generated in the switching pair. Having calculated noise contribution from the
various sources to the output, the noise figure of the mixer can be estimated. Consider that
the load introduces output noise, which can be represented by an equivalent noise resistance
R
L
. The single-sideband (SSB) noise figure for the single-balanced mixer is as shown in
(3.37) and the Gilbert cell respectively is

(3.37)

. (3.38)
Where the quantities

are evaluated with the bias current of each switching pair

and the symbols

have been used for the noise factor of M1 and M3, respectively. If
a band-pass filter is used at the input (which filters out noise from the source resistor at
frequencies outside the input signal band), the term

in (3.37) and (3.38) becomes one. If

the useful signal is present in both sidebands around the LO frequency, the double-sideband
59

noise figure is the appropriate noise performance metric. For the single-balanced mixer and
the Gilbert cell, this is half of the SSB noise figure given by (3.37) and (3.38), respectively.
As in the SSB case, if a band-pass filter is used at the input to reject noise from the source
resistor at frequencies outside the two input signal bands, the first term

becomes one.
Comparing the above equations and neglecting the noise from the LO port, we observe that
for equal conversion gain, the double-balanced structure consumes twice the power of the
single-balanced one and has a higher noise figure.
5.2.4 Distortion calculations
At low frequencies the switching pair is a memoryless system. Neglecting the output
resistance of the transconductance stage, the output current, defined as the difference of the
drain currents of M1 and M2, is a function of the instantaneous values of the output current
of the transconductance stage and the LO voltage:

(3.40)

where

, denote values without input signal present, and

denote incremental values.

Since

is small, a third-order Taylor expansion provides

(3.41)
or

. (3.42)

where

are periodic waveforms of which a typical shape is shown in Fig.

5.6. The value of these waveforms is easily determined when one of the transistors is off. For
example, when M2 is off

and

. When instantaneously

and

, because of symmetry. When the

conductance of both M1 and M2 is significant,

and depend on the bias

current

, the LO voltage , and the device characteristics.

Without loss of generality,

, and

can be considered odd functions of time

and can be expanded in a series of sinusoids. In this case (3.42) provides
60

sin

.. ( 3.43)

Where

is the

coefficient of the waveform

in the series, and

is the LO
frequency. The mixer is usually used for upconversion or downconversion by one LO
multiple and in this case the distortion behavior of the switching pair in the frequency band
of interest can be described by a time-invariant power series

. (3.44)
Where

sin

.. (3.45)
And

is the LO period. If

consists of two tones of equal magnitude

at two closely
spaced frequencies

and

cos

cos

. (3.46)

And the generated third-order intermodulation is

.. (3.47)
5.2.5 Cascading the driver stage and the switching pair

Let us assume now that the nonlinearity of the transconductance stage is described by a
power series as follows:

. (3.48)

Where

is the input voltage. Cascading the power series of the transconductance stage
with that of the switching pair, the output current can be related to the input voltage with a
new time-varying power series. Substituting (3.48) in (3.42) we obtain
61

(3.49)

Using the expansion of

and

in a series of sinusoids as in (3.43) we obtain

sin

(3.50)

If frequency translation by one LO multiple is of interest, the distortion performance can be
described by a time-invariant power series

. (3.51)

Where

(3.52)

(3.53)

.. (3.54)

Observe that these coefficients can be obtained directly by cascading the power series (3.48)
and (3.44).
The total mixer third-order intermodulation is now given by

( 3.55)


62

Chapter 6
IMPLEMENTATION AND RESULTS

This chapter presents the implementation details and results that we achieved. The design
was implemented in CMOS 180nm technology by using ADVANCED DESIGN SYSTEM
tool. LNA was designed with 1.8-V power supply and Mixers were designed in 3.3-V power
supply.
6.1 LNA implementation
As mentioned earlier, cascode type topology has been employed for the LNA design. Both
LB (low-band) and HB (high-band) utilize this topology. A cascode implementation offers
better input-output isolation and gain without twice the power consumption as that of the
common-source topology. As it is usual for many LNA designs to use inductive degeneration
to synthesize the real input impedance, however, we make use of an active termination for
the same purpose to decrease the noise figure (NF). The output load consists of an inductor
of 0.68nH and three capacitors which are required to select the desired band. The capacitor
values are chosen such that it includes the parasitic capacitance present at the output node.
The low-band LNA schematic is shown in Fig. 6.1. The amplifier is drawing 6.29mA of
current from a 1.8-V power supply. Total power dissipation is 22mW. The operating
condition of each transistor is shown in table 6.1., where index column indicates the
transistor index.

Table 6.1 DC operating condition.



63

Each transistor has a W/L ratio of (200m/0.18m). Because the main function of the
cascode transistor is to buffer the current which is flowing through the input transistor, its
gate can be connected to the power supply obviating the need for generating one more bias
voltage. The simulated gain, noise figure and inter-modulation distortion results are shown in
the following sections.


Figure 6.1 Low-Band LNA with biasing scheme shown.
6.1.1 Gain of the LNA
The simulated gain throughout the band (LB) is shown in the Fig. 6.2. As the loading
conditions are changing with respect to the frequency of operation, the gain is not a constant
value. At any frequency in the LB, a nominal gain of 13dB can be expected, although a
64

higher value can be obtained. Fig. 6.2 (a) shows the simulated gain in decibels for 253fF load
at the output.



(a)

(b)
Figure 6.2 Simulated gain of low-band amplifier (a) with 253fF (b) with 168fF, at the
output.
65

In Fig. 6.2(a), the peak value of the gain is attained at 10.8GHz, which is 15.63dB. Although
the resonant frequency of the inductor (0.68nH) and load (253fF) combination is 12.2GHz
approximately, the peak gain was not attained at this frequency because of the drain parasitic
loading of the cascode transistor. The gain at this frequency is 11.394dB, which is an
acceptable value for an LNA.
6.1.2 Noise simulation results
The transconductance of the input transistor plays an important role in the calculation of
noise figure. Only one device should contribute to the total output noise. Otherwise, the noise
figure will not be in the acceptable limits. Figure 6.4 shows the simulated noise voltage at the
output and the noise figure in dB in the band of operations (10-16.5GHz). Total output noise
is maximum of 9nV. The noise of the source resistance was set at a standard value of 800pV.
The noise figure is 3.86dB approximately in the band of operation. The noise figure is also
dependant on the frequency of operation, because, the noise present in the nearby frequencies
of the selected frequency, is different. The following figure shows the noise voltage with
respect to the frequency of operation.
Figure 6.3 Source noise voltage.

66


(a)
(b)
Figure 6.4 Simulated noise results (a) Total noise at the output (b) Input referred noise
figure.

67

6.1.3 Distrotion results
As any nonlinear device will produce output at frequencies (harmonics) other than the
fundamental frequency, its affect on circuit performance is characterized by calculating
distortion caused due to a particular frequency. Often, low-noise amplifiers are characterized
by specifying IM2 (second order inter-modulation) level in the output spectrum relative to
the fundamental frequency, meaning that, by specifying the magnitude of the 2
nd
harmonic
frequency relative to the fundamental frequency. In addition to the IM2 specification,
amplifiers have to meet the IM3 (third-order intermodulation) requirements. IM3 is defined
as, if two closely spaced frequencies (relative to the fundamental) enter into the a nonlinear
device, then the output spectrum will consists of frequency components very near to the
fundametal frequency. This situation is exacerbated when a low-pass filter has to follow the
nonlinear block. Two filter two such closely spaced frequencies, filters have to made of high
Q components, which is often a costly approach. Fig. 6.5 shows the output spectrum and the
input spectrum in the frequency domain. In the Fig. 6.5(b), output spectrum consists of the
fundamental frequency of -6.619dBm at 13GHz and 2
nd
harmonic at -56.097dBm, 26GHz.
The difference between these two power levels is the IM2 distortion, which is, -49.9dBm
approximately. 40dBm is the typical lower limit for the IM2.
Fig. 6.6 illustrates IM3 didtortion. We used the standard two-tone test to get third-
order intercept point. In general, the quantities like noise figure, IM2, IM3..etc.. are usually
port referred which means that they can be specified as input referred or output referred.
Usually all these metrics are input-referred to avoid confusion and to compare the
performance of different LNAs. Two closely spaced tones around 13GHz with 100kHz
offset were applied aand the resulting output spectrum is shown in Fig. 6.6. In the figure, we
see that fundamental tone is at 13.00005GHz and the inter-mod term is at 13.00015GHz.,
whose difference is 55.092dBm. Accordingly, the input-referred intercept point (IIP3) will be
at 20.9dBm.



68


(a)

(b)
Figure 6.5 Frequency domain spectrum (a) Input (b) Output (also indicates IM2 distortion)
69


Figure 6.6 Third-order inter modulation
6.2 Active termination
Fig. 6.7 shows the circuit diagram of the active termination. As mentioned eralier, the
objective of designing the active termination is to terminate the gate of the input transistor of
the LNA with a 50- resistance. But, if we directly place the a 50- resistor, then, the noise
figure of the LNA would go up, resulting, total increase in the systems NF. So, we replace
that resistor with active devices presenting the same resistance as that of a 50- resistor, but,
giving much less noise. This circuit is biased at the same bias voltage as that of the LNA,
obiviating the need for generating the bias separately. The PMOS transistor and the resistor
R
3
combination can be viewed as a load for the NMOS transistor, making the analysis of the
circuit easier. NMOS transistor has dimensions (80m/0.18m) and PMOS has dimensions
(97m/0.18m).

70


Figure 6.7 Circuit diagram of active termination.
Fig. 6.8(a) shows the input impedance (Z
11
) of the active termination and Fig.6.8(b) shows
its input-reflection coefficient (S
11
). As indicated in the Fig. 6.8, the input-impedance has a
nominal value of 50- across the band 10-23GHz. Because of the parasitic capacitances of
the devices, the input-impedance is changing with the frequency. Z
11
has a minimum value of
47.584- at 23GHz, and, has a maximum of 54.202- at 15.20GHz.
The input-reflection coefficient (S
11
), shown in Fig. 6.8(b), is changing from
-21.345dB to -7.429dB as frequency is swept from 10-23GHz. Though becoming worse with
frequency, a matching network before the LNA can be designed to match the impedance of
the antenna and the LNA, so that maximum power can be transferred.




71


(a)

(b)
Figure 6.8 Active Termination (a) Input-impedance (Z
11
) (b) Input-reflection coefficient(S
11
)
72

Chapter 7
Conclusion

A concurrent Dual-Band low-noise amplifier (LNA) and a downconversion mixer have been
designed in 180nm CMOS technology. The LNA is designed to operate in 10-23GHz
frequency band and the downconversion mixer is designed to work in 10-16.5GHz band. An
active termination network is also designed for the purpose of impedance matching and
minimizing the noise contribution. The Low-Noise Amplifier has been designed in 1.8-V
power supply and the mixer has been designed in 3.3-V power supply.
Low-noise amplifier has a nominal gain of 13dB throughout the operating band (10-
23GHz), gain being dependant of the load setting. It has an NF of 3.86dB approximately,
IM2 distortion of 50dBm, and IIP3 of greater than 20dBm. Mixer has a conversion gain of
17-25dB, worst-case -15dBm IIP3, and worst-case -24.5dBm ICP1dB.
Future scope
As shown in Fig. 1.2, the present work is selected from the whole receiver front end (up to
baseband), which was originally designed for phased-array system. We can further extend
this project to include the high-band mixer and IF (intermediate frequency) buffer to provide
sufficient gain at the RF section itself.





73

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74

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Websites:
www.designers-guide.com
www.rftools.com
www.edaboard.com
www.ieeexplore.org
www.rfic.berkeley.edu