The 8051 Architecture and Programming

Supratim Gupta

Programming Issues
Hardware Information Architecture of the processor p Architecture of the peripheral interconnection Software Instructions Complex Instruction Set Computer (CISC) 135 Instructions for 8051

8051 Architecture
Specific Features 1. 8-bit CPU with registers A (accumulator) and B 2. 16-bit program counter (PC) and data pointer (DPTR) 3. 8-bit program status word (PSW) 4. 8-bit stack pointer (SP) 5. Internal ROM or EPROM of 4k (8051) 6. Internal RAM of 128 bytes 4 register banks each containing 8 registers of 8-bit 16-bytes bit addressable registers 80 bytes general purpose data memory

8051 Architecture
Specific F t S ifi Features 7. 32 input-output pins arranged as 4 eight-bit ports (P0 P3) 8. Two 16 bit timer/counters : T0 and T1 9. Full duplex serial data receiver/transmitter 10. Control registers : TCON, TMOD, SCON, PCON, IP, and IE 11. 2 external and 3 internal interrupt sources 12. Oscillator and clock circuit

Cntd

Cntd

8051 Architecture

8051 Programming Model g g

8 IP 8 IP 7F General Purpose 8 B8* 8 B8* 8 IP 8C TH0 98* 8 8 B8* 8 IE 8A TL0 99 8 8 A8* 8 89 TMOD 8D TH1 87 8 8 8 88* TCON 8B TL1 D0* PSW 0FFF

SCON SBUF PCON 30 2F Bit Add. Area 20 8 81 1F Bank 3 18 SP 17 Bank 2 10 8 83 8 82 16 0F Bank 1 08 DPH DPL PC R7 07 Data Pointer R6 R5 8 80* 8 A0* R4 8 90* R3 3 P0 Latch P2 Latch P1 Latch R2 R1 00 R0 * => bit addressable Internal RAM

No Address

B0* 0000 Internal ROM

P3 Latch

Pin Description of 8051 p

P1.0 P1.1 P1.2 P1.3 P1.4 P1 4 P1.5 P1.6 P1.7 RST (RXD)P3.0 (TXD)P3.1 (INT0)P3.2 (INT1)P3.3 (T0)P3.4 (T0)P3 4 (T1)P3.5 (WR)P3.6 (RD)P3.7 XTAL2 XTAL1 GND 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 Vcc P0.0(AD0) P0.1(AD1) P0.2(AD2) P0.3(AD3) P0 3(AD3) P0.4(AD4) P0.5(AD5) P0.6(AD6) P0.7(AD7) EA/VPP ALE/PROG PSEN P2.7(A15) P2.6(A14) P2 6(A14) P2.5(A13) P2.4(A12) P2.3(A11) . ( 0) P2.2(A10) P2.1(A9) P2.0(A8)

8051

A Pin of Port 1
Read latch TB2 Vcc Load(L1) Internal CPU bus Write to latch
D Q

P1.X
Clk Q

P1.X pin M1

TB1 Read pin

P1.x

A Pin of Port 0
Read latch TB2

Internal CPU bus Write to latch

P0.X
Clk Q

P0.X pin M1

TB1 Read pin

P0.x

Crystal Oscillator Connection y

Using a quartz crystal oscillator g q y We can observe the frequency on the XTAL2 pin.
C2 33pF 33pF C1

XTAL2

XTAL1 GND

Port 3 Alternate Functions

P3 Bit P3.0 P3 0 P3.1 P3.2 P3 2 P3.3 P3.4 P3.5 P3.6 P3.7 Function F nction RxD TxD INT0 INT1 T0 T1 WR RD Pin 10 11 12 13 14 15 16 17

RESET Value of Some 8051 Registers

Register PC ACC B PSW S SP DPTR RAM are all zero. zero. Reset Value 0000 0000 0000 0000 0007 0000

TMOD Register

Timer 1

Timer 0

Gate When t ti G t : Wh set, timer only runs while INT(0 1) is high. l hil INT(0,1) i hi h C/T : Counter/Timer select bit. 0 to set it in timer mode M1 : Mode bit 1. M0 : Mode bit 0.

TCON Register g

TF1: Timer 1 overflow flag. TR1: Timer 1 run control bit. TF0: Ti TF0 Timer 0 overflag. fl TR0: Timer 0 run control bit. IE1: External interrupt 1 edge flag. p g g IT1: External interrupt 1 type flag. IE0: External interrupt 0 edge flag. IT0: External interrupt 0 type flag. flag

Interrupt Enable Register

EA : Global enable/disable. Gl b l bl /di bl --- : Undefined. ET2 :Enable Timer 2 interrupt. p ES :Enable Serial port interrupt. ET1 :Enable Timer 1 interrupt. EX1 :Enable External 1 interrupt. E ternal interr pt ET0 : Enable Timer 0 interrupt. EX0 : Enable External 0 interrupt.

Interrupt Vector Address p

Type of Interrupt IE0 TF0 IE1 TF1 SERIAL Address 0003H 000BH 0013H 001BH 0023H

Peripheral Architecture p

Block Diagram of ADC0808

Peripheral Architecture p

Peripheral Architecture p

Input pins Address pins Add i ALE pin p SC pin Clock pin EOC pin

: 8 channels in multiplexed fashion : 3 address bits defines each input channels dd bi d fi hi h l : Latches the address bits : Instructs the ADC to start conversion : Provides clock input to the ADC : Low state on EOC indicates end of conversion

Peripheral Architecture p

Block Diagram of DAC0808

Peripheral Architecture p

Peripheral Architecture p

o u t

re f

A M 2

S B

A 7 4

..........

A 2 4

A LSB 2 5 6

Programming the 8051 g g

Modules: Initialization module D I i i li i Data Initializations (for RAM or SFRs) (f SFR ) Configuration of Control registers Address Vectoring R M d l Run Module Main program for performing a specific task or group of tasks

Programming the 8051 g g

Problem Statement: State and Explain an algorithm for square wave generation

Programming the 8051 g g

One Simple Solution: Step 1: Make a port pin low p p p Step 2: Give necessary delay Step 3: S 3 Toggle the port pin l h i Step 4: Go to Step 2. Note: Multi-task is not possible with this algorithm

RTOS in the 8051

Concept: All the tasks are time-multiplexed Requirements: S ifi d Time interval generation Specified Ti i l i Overall tasks divided into two broad categories Background tasks (Time critical job) F Foreground t k (N ti critical job) d tasks (Non time iti l j b)

Interrupt

Time

Time Ti ISR: Interrupt Service Routine

RTOS in the 8051

Resource for time interval generation: Timer0 or Timer1 Design Issues: Mode of timer (16 or 8 bit) 8-bit) tim_mod .equal 02h mov TMOD, #tim_mod , Computation of content to be used for initialization of timer

Timer Interrupt Generation p

Oscillator Frequency (fosc) To Timer/Counter circuit

12

Interrupt Interval:

12d t Rmax 1 Rmin d f osc

Rmax = FFFF = FF (for 16-bit mode) (for 8-bit mode)

Rmin = User settable

RTOS in the 8051

Time Slot Generation using single timer interrupt by multiplying factor with basic timer interrupt interval TM0: push ACC push PSW ;----------Basic time interval-----------------tm_0: mov A,tickN cjne A #1 tm 1 A,#1,tm_1

;----------Basic time interval*tickN-----------sjmp back tm_1: dec ACC mov tick10,A back: pop PSW pop ACC reti

RTOS in the 8051

Configuration of ports as input or output

mov P0 #FFh P0, ; Set port0 as input port

mov P1, #00h ; Set port1 as output Add Address V t i Vectoring .org 0 ajmp main j p .org 000bh ajmp TM0 ;jump to timer0 routine

RTOS in the 8051

Consists of infinite loop C i t f i fi it l

main: acall level1 sjmp main j p

;jump to service routine for foreground task

Serial Communication

SM0 SM1 SM2 REN TB8 RB8 TI RI

: Serial port mode bit 0 : Serial port mode bit 1 : Multiprocessor communication enable : Receiver enable. Set this bit to receive characters
t : Transmit bit 8 The 9th bit in case of mode 2 and 3 8.

: Receive bit 8. The 9th bit in case of mode 2 and 3 : Transmit flag. Set when a byte transmitted completely : Receive flag. Set when a byte transmitted completely

Serial Communication

SM0 0 0 1 1

SM1 0 1 0 1

Mode SMOD1 of PCON 0 1 2 3 X 0 1 0 1 0 1

Baud Rate fosc/12 B0 = Set by Timer 1/2 B1 = 2*B0 = Set by Timer 1/2 fosc/64 fosc/32 B0 = Set by Timer 1/2 B1 = 2*B0 = S t b Ti Set by Timer 1/2

Serial Communication

TH 1 256

f o sc B req 384
f o sc B req 192

TH 1 256

Serial Communication

Transmission
clr TI ; Clear the transmit flag

mov SBUF, #D ; Send letter D to transmit Loop: jnb TI , Loop ; Check for transmission over Reception p Loop: jnb RI , Loop ; Check for reception complete mov A SBUF ; R d received d A, Read i d data

Serial Communication with PC

Microcontroller PC Serial Port TTL/CMOS Logic RS232 Logic

Logic Protocol CMOS TTL Logic Protocol RS232

Low Voltage Level (0) 0-Vcc/2 0-0.8V Transmission Low Voltage ( ) Level (0) (+5)- (+25)V

High Voltage Level (1) Vcc/2 - Vcc 2V-0-Vcc

Note Vcc= Supply Vcc is 4.75 5.25 V

Reception Low Voltage ( ) Level (0) > (+3)V High Voltage ( ) Level (1) < (-3) V

High Voltage ( ) Level (1) (-5)- (-25)V

Serial Communication with PC

Implementation p

Hardware: Universal Microcontroller Programmer Software: Assembler for 8051 Converts *.asm file to *.obj Linker for 8051 Links several *.obj files and converts the whole to *.hex Hex code downloader application program Provided with universal programmer Download the hex code into the microcontroller