A new model of subthreshold swing for sub-100 nm MOSFETs

Lin-An Yang
*
, Chun-Li Yu, Yue Hao
School of Microelectronics, Xidian University, Xian 710071, China
Received 8 April 2007; received in revised form 16 May 2007
Available online 10 August 2007
Abstract
A novel subthreshold swing model that linearly depends on the drain bias voltage (V
ds
) and negative-exponentially depends on the
eective channel length (L
e
) is proposed for LDD MOSFETs on 90 nm CMOS technology. It simplies the description of the eective
gate overdrive voltage (V
gte
) and yields a single-equation IV compact model to present the transition of the drain current (I
ds
) between
subthreshold and strong inversion. The simulation shows an excellent prediction to the characteristics of sub-100 nm MOSFETs espe-
cially in the subthreshold region that is very important in reliability analysis of short channel devices. Compared with the existing thresh-
old voltage-based compact models, the modeling is low in calculation consumptions therefore suitable for the circuit simulation.
2007 Elsevier Ltd. All rights reserved.
1. Introduction
While MOS devices scaling down to the ultra-deep sub-
micron regime, the supply voltage decreases to the level of
lower than 1 V in practice. In this case, an accurate sub-
threshold current model of MOSFETs nds more valuable
application in reliability analysis of devices. Among the
existing threshold voltage-based compact models for short
channel devices, the BSIM series still dominate the regime
of the devices technology before 65 nm node because of
good accuracy and easy understanding [13], despite some
drift-diusion surface potential-based models have found
rapid developments for nanometer MOS devices. Normally,
the modeling of IV characteristics include a diusion
current-based subthreshold current model, a drift-current-
based strong inversion current model and a smooth transi-
tion model between the two regions, all of which require a
large number of tted and extracted parameters to maintain
the modeling accuracy. When the gate oxide thickness
decreases to 12 nmregime in sub-100 nmMOSFETs, there
appear some enhanced eects, such as gate and drain leak-
age induced by gate tunneling, reverse short channel eect
induced by high substrate doping, parasitic resistance
caused by shallow source/drain junction, etc., all of which
not only signicantly degrade the subthreshold characteris-
tics of devices, but also increase the complexity of device
modeling. In BSIM4 model [3], for example, a complicated
model of eective gate overdrive voltage (V
gte
) is employed
to smooth the current discontinuity between strong inver-
sion and subthreshold regions in order to form a unied
IV model. Although possessing a good accuracy, this kind
of device model is of great inconvenience for circuit simula-
tion since too many tting parameters are required. Thus
this work put the emphasis on developing a concise model
of eective gate overdrive voltage (V
gte
), wherein a novel
subthreshold swing model with fewer tting parameters is
proposed, aimed at obtaining an empirically based IV
model with single-equation for both the subthreshold
region and the strong inversion region, needless another
subthreshold current model as that in BSIM4 model. The
LDD MOSFETs with the mask gate lengths ranging from
90 nm to 0.50 lm and the gate oxide thickness of 1.24 nm
fabricated on 90 nm CMOS technology are investigated to
verify the modeling of ultra-deep submicron devices.
2. Modeling of ultra-deep submicron MOSFETs
In the theory of inversion charge of MOSFETs, the
strong inversion and the weak inversion are two important
0026-2714/$ - see front matter 2007 Elsevier Ltd. All rights reserved.
doi:10.1016/j.microrel.2007.06.007
*
Corresponding author. Tel.: +86 29 88201759; fax: +86 29 88201641.
E-mail address: layang@xidian.edu.cn (L.-A. Yang).
www.elsevier.com/locate/microrel
Available online at www.sciencedirect.com
Microelectronics Reliability 48 (2008) 342347
regions for modeling. First of all, we summarize the mod-
eling in strong inversion where the gate voltage V
gs
is larger
than the threshold voltage V
th
. In this region, a universal
drain current characteristic derived from the inversion
charge for short channel MOSFET has been modeled by [4]
I
ds

WC
ox
l
eff
L
eff
1
V
dsx
L
eff
E
c
_ _V
gs
V
th
0:5aV
dsx

V
dsx
1
l
d
E
c
L
eff
l
d
E
c
V
dsx
_ _
; 1
where V
dsx
is dened as the eective drain voltage replacing
the saturation voltage V
dsat
to smooth the drain current
transition from linear to saturation regions [4]. The other
parameters such as the eective channel length L
e
, velocity
saturation region length l
d
, critical saturation electric eld
E
c
, and eective mobility l
e
are determined by parameter
extraction. W and C
ox
are the gate width and gate oxide
capacitance. This widely used IV model can present the
drain current characteristics in whole the linear and the sat-
uration regions, i.e., the low and high V
ds
regions. The
shortcoming of this kind of V
th
-based model is that it is
always sensitive to the accuracy of parameter extractions.
With a drastic decrease of supply voltage for deep-sub-
micron devices, the performance of devices in weak inver-
sion, i.e., in subthreshold region, becomes more and more
important. For modeling the drain current in subthreshold
region where V
gs
< V
th
, an eective gate overdrive voltage
V
gte
is developed to replace the term (V
gs
V
th
) in (1).
For example, BSIM3 and BSIM4 give a kind of V
gte
model,
shown as [2,3]
V
gte

nV
t
ln 1 exp
m

V gseV
th

nV t
_ _ _ _
m

nC
oxe

2U
s
qNDEPe
si
_
exp
1m

V gseV
th
V
0
off
nV t
_ _ ; 2
where V
t
= k
B
T/q is the thermal voltage, and the oset
voltage V
0
off
, modifying coecient m
*
, eective gate voltage
V
gse
, etc., are obtained by extraction, most of which require
a large number of tting parameters to maintain the mod-
eling accuracy [3]. Among these parameters, the subthresh-
old swing n is an important parameter for describing the
drain current characteristics in subthreshold region and
transition region, which is modeled in BSIM4 by
n 1 NFACTOR
C
dep
C
oxe

Cdsc Term CIT

C
oxe
; 3
where
Cdsc Term CDSC CDSCD V
ds
CDSCB V
bseff

0:5
cosh DVT1
L
eff
lt
_ _
1
: 3a
Obviously, the denition of n is of some complexity, and
the yielding V
gte
model requires too many tting coe-
cients, which is inconvenient for circuit simulation. Besides,
another subthreshold drain current dierent from (1) is still
required, which is modeled by [3]
I
ds
l
W
L

qe
si
NDEP
2/
s
V
2
t

1 exp
V
ds
V
t
_ _ _ _
exp
V
gs
V
th
V
0
off
nV
t
_ _
: 4
Thereby (2) accompanied with (3) is used to match the
smooth transition between (1) and (4). The modeling accu-
racy has been widely accepted in suitable device regime.
3. Concise V
gte
model with a novel denition of subthreshold
swing
To circumvent the complexity of above mentioned
model, a more concise V
gte
model is proposed in this work
as
V
gte
g ln1 e
V gsV
th
=g
: 5
With this model, Eq. (1) can be directly used to describe the
subthreshold characteristics, needless adding another sub-
threshold drain current model such as (4). Clearly the
implement is much easier than those in existing models
[25]. Note that g is a key parameter to govern the accuracy
of the drain current transition between subthreshold and
strong inversion in this V
gte
model. Generally speaking, g
is related with nV
t
similar to that in (2). For long channel
MOSFET, the subthreshold swing n is often regarded as
a constant, so is nV
t
. Some previous models for short chan-
nel devices also employ the constant n for simplicity. In
fact, g closely depends on the bias voltages due to that
the surface potential /
s
is related to the bias voltage instead
of a constant in short channel device. Thus this work gives
a concise denition to the parameter g as
g nV
t
; 6
where a new subthreshold swing n is modeled by taking the
drain bias and the channel length into account, and omit-
ting the inuence of substrate bias by forcing V
sb
= 0,
shown as follows
n n
0
f L
eff
; V
ds
: 7
This n model consists of two terms: n
0
is dened as the sub-
threshold swing of long channel device and is regarded as a
constant; f(L
e
, V
ds
) is a function related with eective
channel length and drain voltage, and is determined by
parameters extraction. In the long channel device, the con-
tribution of f (L
e
, V
ds
) is very weak because of bias-inde-
pendent surface potential, thus g approximately equals
the constant n
0
V
t
. With shortening of the channel, the
inuence of f (L
e
, V
ds
) on the subthreshold swing in-
creases. To unveil this tendency, the LDD NMOSFETs
with dierent mask gate lengths are used for parameter
extraction by using Eqs. (1), (5), (6) and (7). The extraction
results in Fig. 1 gives an approximately linear dependence
between n and V
ds
, and further, the inuence of V
ds
increases with shrinkage of the channel length. Conse-
quently, the y-axis intercepts and the slopes of these n
L.-A. Yang et al. / Microelectronics Reliability 48 (2008) 342347 343
versus V
ds
straight lines can be calculated. The results and
the tting curves are drawn in the inset of Fig. 1. It clearly
shows a negative-exponential dependence of the intercept
and slope on the eective channel length L
e
, where the L
e
extraction is discussed later. With the curves the function
f(L
e
, V
ds
) can be easily determined by optimization, there-
fore the model (7) can be written in details by
n n
0
a
1
e
L
eff
=l
0
a
2
V
ds
; 8
where a
1
and a
2
are the tting coecients, l
0
is dened
as the critical length. This yields the intercept of n
0
+
a
1
a
2
exp(L
e
/l
0
) and the slope of a
1
exp(L
e
/l
0
). By least
square optimizing both negative-exponential curves simul-
taneously, the parameters can be obtained as: n
0
= 2.75
(normally, the empirical value of n
0
is between 1 and 3
for long channel devices), a
1
= 3.36, a
2
= 2.29, and
l
0
= 0.033 with the same dimension as L
e
. Mathematically,
the term exp(L
e
/l
0
) in (8) tends to zero when L
e
is large,
but can not be omitted when L
e
< 5l
0
. That means the
inuence of V
ds
on n must be taken into account when
L
e
< 0.165 lm, i.e., the mask gate length L
mask
is approx-
imately lower than 0.2 lm. Note that L
e
= L
mask
DL,
and the extracted channel length reduction DL of
0.0252 lm from the referenced devices will be discussed
later. Thus for ultra-deep submicron device, the increase
of n with V
ds
will slow down V
gte
changing from V
gt
to zero
(see Eq. (5)), certainly enlarge the subthreshold current due
to the current continuity. The result is consistent with the
tendency in other existing models that the subthreshold
current is empirically proportional to 1 exp(V
ds
/V
t
)
[3,6]. Instead of the gate overdrive voltage (V
gs
V
th
) by
the new V
gte
model (5), the IV model (1) is suitable for
not only the strong inversion but also the subthreshold
region. Thus the improved IV model with a simple V
gte
expression does not require another diusion current
model in subthreshold region. Especially, the new sub-
threshold swing n model requires only four tting coe-
cients, which are much lower than that in (3), therefore
signicantly reduces the calculations for circuit simulation.
In some literatures such as [7], a single-equation IV model
is also developed which shows accurate and practical
results in subthreshold region. But the modeling of V
gte
is
still complicated and requires more tting coecients com-
pared with the new model. Further, literature [7]employs
the longer channel MOSFETs on 0.25 lm CMOS technol-
ogy, in which case the model can not present the clear
inuence of V
ds
and L
e
.
4. Parameter extraction for IV modeling
The ultra-thin gate oxide (t
ox
= 1.24 nm) LDD NMOS-
FETs with W/L
mask
= 6/0.09, 0.13, 0.16, 0.22, 0.28, 0.35
and 0.5 lm fabricated on 90 nm CMOS technology are
referenced in this work. First of all, we employ the
measurement-based threshold voltages model, as is given
by [4]
V
th
V
th0V
ds
50 mV
rV
ds
V
th0V
ds
50 mV

e
0
e
Si
r
0
r
1
V
sb

pC
ox
L
m
eff
V
ds
; 9
where V
th0V
ds
50 mV
is the extraction from I
ds
V
gs
charac-
teristic at V
ds
= 50 mV by transconductance change (TC)
extraction technique which is found well for ultra-thin gate
oxide MOSFETs among existing V
th
extraction techniques
because it can reduces the impact of parasitic resistance
and mobility variation [8]. Dierent devices with the gate
lengths ranging from 0.09 lm to 0.5 lm are employed for
V
th
extraction, where dierent drain biases are supplied
to present the reverse short channel eect (RSCE) induced
by the heavy doping of channel which is widely used in ul-
tra-deep submicron device. Given in Fig. 2 are the ex-
tracted V
th
at 50 mV and 1.5 V drain biases and zero
0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6
3
4
5
6
7
8
Symbol: extraction
Curve: fitting
I
n
t
e
r
c
e
p
t
Effective Gate Length, L (m)
S
l
o
p
e

L
mask
=0.09m
L
mask
=0.13m
L
mask
=0.16m
L
mask
=0.22m
L
mask
=0.28m
L
mask
=0.35m
S
u
b
t
h
r
e
s
h
o
l
d

S
w
i
n
g
,
n
Drain Voltage, V
ds
(V)
Fig. 1. Plots of n against V
ds
extracted from LDD NMOSFETs with the
mask gate lengths ranging from 90 nm to 0.35 lm. The inset is the plots of
y-axis intercepts and the slopes of n versus V
ds
straight lines, where the
solid lines are the curves tted by negative-exponential function.
0.0 0.1 0.2 0.3 0.5 0.6
0.2
0.3
0.4
0.5
0.6
0.7
0.8
(V =0)
V =0.05V
V =1.5V
T
h
r
e
s
h
o
l
d

V
o
l
t
a
g
e
,

V


(
V
)
Gate Mask Length, L (m)
0.4
Fig. 2. Extracted threshold voltage V
th
by TC method at drain bias
voltages of 50 mV and 1.5 V, respectively. The substrate bias is zero.
344 L.-A. Yang et al. / Microelectronics Reliability 48 (2008) 342347
substrate bias, where the plot of V
th
versus L
mask
clearly
presents the RSCE tendency. After several drain and sub-
strate biases, the measured I
ds
V
gs
data are used to deter-
mine the tting parameters r
0
, r
1
and m in (9) by
optimization and the results are listed in Table 1. Com-
pared with the existing V
th
models based on experiments
[3,9], Eq. (9) is more convenient to present the eect of
drain induced barrier lowering (DIBL). More importantly,
the motivation of our using the measured V
th
instead of
calculation-based V
th
model is to maintain the accuracy
of V
th
-based model (1) for simulating IV characteristics
of LDD NMOSFETs.
Secondly, the drain/source parasitic series resistance
R
ds
, the channel length reduction DL, the eective mobility
l
e
, etc., are imperative for device modeling. Practically,
the constant R
ds
, DL, and low electric eld l
0
are desired
for compact model. But the signicant gate leakage, drastic
mobility degradation and V
th
shift always impact the
meaningful parameter extractions in ultra-deep submicron
devices. Based on the widely used L-array method, this
work employs V
th
optimization technique to extract above
parameters [10]. With this technique, the extraction error
caused by signicant gate leakage and V
th
shift is greatly
reduced, and the uctuation of extracted results by dier-
ent existing methods also shrinks. The constant R
ds
, DL,
and l can be easily obtained in high gate bias region which
is reasonable in compact model for circuit simulation. The
results from the referenced devices by this extraction
method are listed in Table 1. To other important parame-
ters, the extracted V
dsat
by means of G-function method
can be used to optimize the parameters E
c
, a, d
0
and A
which are required in V
dsat
and V
dsx
expressions. The
results are also given in Table 1.
5. Simulation results and discussion
With above proposed models and parameter extrac-
tions, Fig. 3 gives the simulated and measured drain cur-
rent and drain conductance characteristics of device with
mask gate length of 90 nm. The drastic channel length
modulation (CLM) eect and drain induced barrier lower-
ing (DIBL) eect are well modeled by excellent agreement
between simulation and measurement in linear and satura-
tion regions. Further more, Fig. 4 presents the measured
and simulated I
ds
V
gs
and g
m
V
gs
characteristics at dier-
ent drain biases, showing a good continuity of the rst
order of drain current model in reversion region. Fig. 5
shows the comparison between the simulated and mea-
sured drain current of 90 nm device in the low gate bias
region. The signicant degradation of subthreshold charac-
teristics with the increasing V
ds
is accurately predicted,
which implies that the improved IV model is valid in sub-
threshold region for sub-100 nm devices. The serious deg-
radation of subthreshold current at high V
ds
is due to the
ultra-thin gate oxide in the referenced device which is
reected on the high value of a
1
in (8). It can be predicted
that a
1
will decrease with the improvement of gate oxide
technology. To verify the model in longer channel devices,
the LDD NMOSFETs with the gate lengths ranging from
0.13 lm to 0.35 lm are investigated. Fig. 6 gives the output
drain currents in linear and saturation regions at the gate
biases of 0.6 V and 1.2 V. A good agreement between sim-
ulation and measurement demonstrates that the new model
is suitable for the wide range of gate length. Fig. 7 gives
Table 1
Extracted parameters for modeling of IV characteristics
R
ds
(x) DL (lm) l
0
(cm
2
/Vs) E
c
(V/cm) a d
0
A m r
0
r
1
25.32 0.0252 158.3 2.55 10
4
1.06 0.2 10 1.5 1.8 0.3
0.0 0.3 0.6 0.9 1.2 1.5
0
5
10
15
20
0.3 V
0.6 V
0.9 V
1.2 V
V
gs
=1.5 V
D
r
a
i
n

C
o
n
d
u
c
t
a
n
c
e
,

g
d
s

(
m
S
)
Drain Voltage, V
ds
(V)
D
r
a
i
n

C
u
r
r
e
n
t
,

I
d
s

(
m
A
)
Symbol: measurement
Solid Line: simulation
W/L
mask
=6/0.09 m
-1
0
1
2
3
4
5
6
7
Fig. 3. Measured and simulated output drain current and drain conduc-
tance of LDD NMOSFET with 90 nm mask gate length.
0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4
0
1
2
3
4
5
6
7
8
Symbol: measurement
Solid line: simulation
W/L
mask
= 6/0.09m
V
ds
=0.05V
V
ds
=0.55V
V
ds
=1.05V
V
ds
=1.50V
D
r
a
i
n

C
u
r
r
e
n
t
,

I
d
s

(
m
A
)
Gate Voltage, V
gs
(V)
0
2
4
6
8
10
T
r
a
n
s
c
o
n
d
u
c
t
a
n
c
e
,
g
m

(
m
S
)

Fig. 4. Measured and simulated I
ds
V
gs
and g
m
V
gs
characteristics of
LDD NMOSFETs with mask gate length of 90 nm at dierent drain
biases.
L.-A. Yang et al. / Microelectronics Reliability 48 (2008) 342347 345
the variation of drain current with the channel length in
subthreshold and transition regions at low drain bias
(V
ds
= 50 mV) and Fig. 8 at high drain bias (V
ds
= 1.5 V)
respectively. It is observed that the subthreshold character-
istics signicantly degrade when the gate length shrinks to
sub-100 nm regime, and a serious degradation occurs with
increasing V
ds
. In summary, the excellent agreements
between simulations and measurements indicate that the
proposed IV model is valid not only in strong inversion
but also in subthreshold region for devices from deep to
ultra-deep submicron regime. Thus the new subthreshold
model is valuable in reliability prediction of devices and
its simplicity is desirable for circuit simulation.
6. Conclusions
This work proposes an improved model of eective gate
overdrive voltage V
gte
with a novel denition of the sub-
threshold swing n. This leads to a simple subthreshold cur-
rent model that includes a linear-dependence of n on the
drain bias voltage and an negativel-exponential depen-
dence of n on eective channel length, both of which are
experimentally proved by extraction from ultra-thin gate
oxide LDD MOSFETs with the gate lengths ranging from
90 nm to 0.35 lm on 90 nm CMOS technology. With this
concise model, the degradation of subthreshold character-
istics in sub-100 nm devices is well predicted, which is
important in reliability analysis of ultra-deep submicron
devices and circuits. The comparison between simulations
and measurements shows that the improved IV model is
suitable for devices from deep to ultra-deep submicron
regimes. Furthermore, this model avoids the complicated
V
gte
modeling and another subthreshold current model
employed in some existing models, thus reduces the calcu-
lations of the single-equation IV compact model for whole
the bias voltage region which is valuable for circuit
simulations.
0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7
1x10
1x10
10
10
10
10
10
Symbol: measurement
Solid line: simulation
W/L
mask
= 6/0.09m
V =0.05V
V =0.55V
V =1.05V
V =1.50V
D
r
a
i
n

C
u
r
r
e
n
t
,

I
d
s

(
m
A
)
Gate Voltage, V
gs
(V)
Fig. 5. Measured and simulated subthreshold currents of 90 nm LDD
NMOSFETs at dierent drain biases.
0.0 0.4 0.8 1.2 1.6
0
1
2
3
4
(V
gs
=0.6 V)
Symbol : measurement
Solid line : simulation
(V
gs
=1.2 V)
L
mask
=0.13m
0.16m
0.22m
0.28m
0.35m
D
r
a
i
n

C
u
r
r
e
n
t
,

I
d
s

(
m
A
)
Drain Voltage, V
ds
(V)
0.2 0.6 1.0 1.4
Fig. 6. Measured and simulated output drain current of LDD NMOS-
FETs with mask gate lengths ranging from 0.13 lm to 0.35 lm.
0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7
10
10
10
10
1x10
1x10
10
10
10
10
10
L
mask
=0.09m
0.13m
0.16m
0.22m
0.28m
0.35m
Symbol: measurement
Solid line: simulation
Gate Voltage, V
gs
(V)
D
r
a
i
n

C
u
r
r
e
n
t
,

I
d
s

(
m
A
)
(V =50mV)
Fig. 7. Measured and simulated I
ds
V
gs
characteristics of LDD NMOS-
FETs with mask gate lengths from 0.09 lm to 0.35 lm at V
ds
= 50 mV.
0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7
10
10
10
10
1x10
1x10
10
10
10
10
10
Symbol: measurement
Solid line: simulation
L
mask
=0.09m
0.13m
0.16m
0.22m
0.28m
0.35m
(V =1.5V)
D
r
a
i
n

C
u
r
r
e
n
t
,

I
d
s

(
m
A
)
Gate Voltage, V
gs
(V)
Fig. 8. Measured and simulated I
ds
V
gs
characteristics of LDD NMOS-
FETs at V
ds
= 1.5 V.
346 L.-A. Yang et al. / Microelectronics Reliability 48 (2008) 342347
Acknowledgements
The project is supported by the National Natural Sci-
ence Foundation of China (Grant No. 60376024). The
LDD MOSFETs on 90 nm CMOS technology were fabri-
cated at Semiconductor Manufacturing International Cor-
poration, Shanghai.
References
[1] Sheu BJ et al. BSIM: Berkeley short-channel IGFET model for MOS
transistors. IEEE J. Solid-State Circuits 1987;SC-22:55865.
[2] Cheng Y et al. A physical and scalable IV model in BSIM3V3 for
analog/digital circuit simulation. IEEE Trans. Electron. Devices
1997;44(2):27787.
[3] Liu WD et al. BSIM4v1 MOSFET Model Manual. Berkeley: Uni-
versity of California; 2000.
[4] Arora N. MOSFET Models for VLSI Circuit Simulation Theory and
Practice. Springer-Verlag; 1993.
[5] Cheng Y et al. A unied MOSFET Channel charge model for device
modeling in circuit simulation. IEEE Trans. CAD Integrat. Circuits
Syst. 1998;17(8):6414.
[6] Chen MJ, Ho JS. A three-parameters-only MOSFET subthreshold
current CAD model considering back-gate bias and process variation.
IEEE Trans. CAD Integrat. Circuits Syst. 1997;16(4):34352.
[7] Lim KY, Zhou X. MOSFET subthreshold compact modeling with
eective gate overdrive. IEEE Trans. Electron. Devices 2002;49(1):
1969.
[8] Terada K et al. Comparison of MOSFET-threshold-voltage extrac-
tion methods. Solid-State Electron. 2001;45:3540.
[9] Zhou X, Lim KY. Unied MOSFET compact IV model formula-
tion through physics-based eective transformation. IEEE Trans.
Electron Devices 2001;48(5):88796.
[10] Hao Y, Yang LA, Yu CL. An optimization technique for parameter
extraction of ultra-deep submicron LDD MOSFETs. Solid-State
Electron. 2006;50:15405.
L.-A. Yang et al. / Microelectronics Reliability 48 (2008) 342347 347