Analog Integr Circ Sig Process (2010) 64:3944 DOI 10.

1007/s10470-009-9358-y

A broadband folded Gilbert cell CMOS mixer

Marko Krcmar Georg Boeck

Received: 19 December 2008 / Revised: 4 May 2009 / Accepted: 28 July 2009 / Published online: 13 August 2009 Springer Science+Business Media, LLC 2009

Abstract A folded Gilbert cell mixer was implemented in 0.13 lm complementary metal oxide semiconductor (CMOS) technology. The downconversion mixer is designed for 56 GHz radio frequency (RF) band and an intermediate frequency (IF) of 500 MHz. A voltage conversion gain (CG) of 9 dB, a noise gure (NF) of 11 dB and an IIP3 of 2 dBm were demonstrated experimentally under very low power consumption conditions, only 4.2 mW for the mixer core. Considering the overall performance of the circuit, this paper shows that the folded mixer architecture is one of the most interesting frequency converter solutions for low-power mobile applications. Keywords Folded Gilbert cell CMOS Low power Mobile communications Broadband

1 Introduction The reduction of supply voltage in modern receivers is one of the most restrictive issues while choosing a suitable architecture in an radio frequency (RF) front-end design. This is mostly valid for mixers, since the traditional topologies imply three stacked transistors, i.e., the Gilbert cell [1]. On the other hand constraints concerning conversion gain (CG), noise and linearity are getting more and

M. Krcmar (&) G. Boeck Berlin Institute of Technology, Einsteinufer 25, 10587 Berlin, Germany e-mail: krcmar@mwt.ee.tu-berlin.de G. Boeck e-mail: boeck@tu-berlin.de

more challenging and therefore it is necessary to nd solutions that can t all these contrasting specications: low supply voltage, low power consumption, low noise gure (NF), high gain and high linearity. Several different solutions have been published in past years: a modied Gilbert cell mixer without current tail transistor [2, 3] a low voltage high gain complementary metal oxide semiconductor (CMOS) mixer [4], a folded switching mixer with current reuse [5], and a single-balanced mixer with current reuse [6]. A very good comparison between low voltage Gilbert cell mixer and mixer with current boosting is presented in [7]. The main drawback in the solutions presented in [2, 3, 57] is the large number of implemented transistors which imply additional noise and higher power consumption. Implementing the mixer without current tail allows lower supply voltages but still causes large noise contribution of the local oscillator (LO) switches, due to the high current owing through the devices, and requires large driving voltages to turn the transistors completely on and off. A very efcient implementation of current boosting with resonating inductor is presented in [8], but it still shows several limits in terms of low supply voltage and circuit complexity. The need for a topology without stacked components and a completely separated biasing is evident. Starting from a mixer core introduced in [9], we present a folded 0.13 lm CMOS double-balanced mixer which operates with 1.2 V supply voltage within a bandwidth from 5 to 6 GHz with a maximum voltage CG of 9 dB and a single sideband NF of 11 dB, consuming only 4.2 mW in the mixer core. These measured results show the suitability of this mixer topology for low-power receivers with large bandwidth. In this rst version of the mixer the RF bandwidth includes both the wireless local area network (WLAN) 802.11a/n band and the industrial, scientic, medical (ISM) band centered in 5.8 GHz.

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Fig. 1 NMOS Gilbert cell mixer

2 Concept considerations
Fig. 2 Current bleeding technique

In order to appreciate the advantages of a folded structure we should rst introduce the traditional Gilbert cell mixer. This double balanced structure is shown in Fig. 1. It is well known that the fully differential structure, with respect to both RF and LO signal, has a signicantly lower common mode noise and second order distortion and a very high LO to intermediate frequency (IF) and LO to RF isolation (4060 dB) if the circuit layout is perfectly symmetrical. The standard performances of a Gilbert cell are: voltage CG of around 10 dB, NF about 15 dB and IIP3 around 0 dBm, consuming *10 mW. However three stacked transistors imply quite high voltage supplies in the order of 2.5 V. This is a serious drawback of this architecture with respect to power consumption. But a reduction of the supply voltage leads to worse linearity performance. A second issue is the voltage CG, given by [10]. Vif 2 % g m RL Vrf p 1

under the supposition of perfect switching behavior of the LO transistors. In order to increase the mixer gain there are only two or three possibilities: to increase the current owing through the transconductors or to increase the load impedance or both of them. At a given current there is a limitation for increasing the load resistors because of the voltage drop along these resistors. On the other hand, higher current through the transconductors improves the gain and the linearity of the mixer but forces more current owing through the LO switches. The latter effect causes a non ideal switching, which means that both switching transistors are

simultaneously in on state for a longer time. Thus more and more RF current is lost as a common-mode signal. For a given LO amplitude, the switching transition time of the transistors can be reduced by reducing the drain current owing through them. This can be achieved by the current bleeding technique [11]. In that principle a certain amount of current is bypassed through a parallel connected current source. Figure 2 depicts the single-balanced version of this architecture. The Ibleed bypass current reduces the DC current through the switches and allows at the same time an increase of load resistors, thus improving the CG for a given LO signal amplitude. The noise contribution of the switching stage is also reduced, because of the lower DC current owing through the switches. This solution has its biggest drawback in the noise contribution of the current bleeding circuit. This is mostly the case when the bleeding source is realized with active devices. The alternative is to use inductive-capacitive (LC)-tanks, but this represents higher costs in terms of chip area and has a narrowband behavior. Thus, in order to achieve the best CG, noise and linearity performance, it is necessary to nd a way to bias the transconductors and the LO switches independently from each other. This is made possible by a folded structure. Figure 3 depicts a folded Gilbert cell mixer with grounded RF transconductors, which means without a common current tail.

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Fig. 4 Simplied schematic of one switching quad with Cp

Fig. 3 Simplied schematic of the folded Gilbert cell mixer

an important factor considered during the choice of the transistor width. Larger transistors require smaller inductors for matching which reduces the chip area. g2 2lCox m Wopt ID L 3

3 Mixer design The DC voltage of 1.2 V is applied using two inductors. These inductors have been designed to resonate with the parasitic source capacitances of the switching transistors at the central frequency, which is 5.5 GHz. This improves conversion efciency and noise performance of the mixer, since the parasitic capacitances of the switching stage do not shunt the signal current if neutralized by inductors at the desired frequency. The RF transistors are grounded in order to use the maximum of the voltage headroom and therefore improve the linearity of the mixer. An LC tank as current source would achieve a higher common-mode rejection [12] and a higher common-mode noise suppression, but for the price of a higher chip area. For this reason particular attention was dedicated to the symmetry of the layout. The inductive degeneration provides both stability and a real part at the input of the gates. The input 50 X matching is provided by serial inductors connected to the gates of the transistors. The inductors are the most bulky elements in the circuit, but are necessary in this early part of design. Through integration with other components the source and the gate inductors of the input transistors will not be implemented reducing dramatically the chip area and therefore the costs. In order to dene the dimensions of the input transistors we calculated rst the optimal width [13] for minimum noise using Eq. 2: Wopt % 1 3x LC ox Rgen 2

The LO switches were biased with an overdrive voltage close to zero (where the threshold voltage is about Vt = 0.4 V). The current owing through them is some tens of microampere in the off state. The impedance seen from the transconductor is *1/gm, which is also dened by (3). Large transistors show a lower on-resistance and therefore improve matching and linearity. However, they incorporate higher parasitic capacitances (Cp) and worsen the overall noise of the mixer and the driving requirements. Figure 4 shows a simplied schematic of one switching quad with Cp and an inductor resonating at fRF. The inductor must resonate out Cp for all the RF frequencies in order to avoid that the signal current ows through the parasitic capacitances causing signal losses. Due to the large RF bandwidth a resonator with a low Q had to be designed. For this reason a very narrow conductor has been used for the spiral with higher ohmic losses. A minimum width of 5 lm was chosen. At the resonance frequency (4), which we set to 5.5 GHz, the expression of the ideal impedance is Zin is shown in (5). 1 xres p L Cp Zin 1 gm;3 gm;4 4 5

The value was successively modied in order to meet also gain, linearity and power consumption constraints, using the Eqs. 1 and 3 and targeting a current consumption of less than 10 mA. Input matching was also

Since a very low biasing current is owing through the switches, a large transistor width is required in order to achieve a lower on-resistance and avoid linearity degradation. The width and the number of ngers are limited by Cp. Thus the dimensions of the switches need to be chosen as a tradeoff between linearity and noise [14].

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Fig. 6 Simulated (solid line) and measured (symbols) CG and NF versus LO amplitude Fig. 5 Die micrograph

Finally, the output of the mixer is buffered with source followers in order to realize 50 X output impedances. The buffers are only for measurement reasons and not required later on for the completely integrated transceiver.

4 Measurement results The mixer was designed and manufactured in IBM CMOS 8RF 0.13 lm process technology. The dimensions of the die without pads are 1024 9 788 lm2. Figure 5 shows the die micrograph. Firstly the measurements have been performed directly on-wafer at several chips. 180 hybrid combiners/dividers have been used at coaxial level providing the differential signals and the Agilent E4440A spectrum analyzer as receiver for signal and noise measurements. A large discrepancy between the simulated and measured results was observed concerning the noise. We expected to predict properly the experimental results by means of accurate electromagnetic (EM) simulations of the layout interconnections, input and output pads and spiral inductors. This EM-schematic cosimulation led to an accurate prediction in terms of CG, but not in case of NF. There are three main reasons for this discrepancy. The rst one concerns the design: insufciant on-chip ltering of the power supply leads to a signicantly higher noise in the circuit. Its contribution can be quantied in about 12 dB. Another 1 dB uncertanty is given by the measurement method: the YFactor method. And nally a 0.51 dB uncertanty is given by the transistor models as well. Anyway, the main reason for the observed discrepancy is the dirty power supply which is not ltered properly on chip. For this reason we desgined a printed circuit board (PCB) on a Rogers 4003 substrate in order to enhance the measurement setup. After

bonding the chip on the board, several blocking capacitors were added on the power supply lines as close as possible to the die. Different capacitance values have been used in order to lter out a large frequency band. The measurements shown that adding this blocking capacitors improved drammatically the mixer performance in terms of noise as we expected. The following gures show an excellent matching between measurements and simulations in terms of CG and a discrepancy of *1 dB for NF due to the measurement setup. The mixer was designed for 0.5 V LO voltage amplitude, but with a larger voltage swing even better results can be achieved as shown in Fig. 6. A supply voltage of 1.2 V has been applied and an overall current of *8 mA has been observed owing through the die. The circuit has been tested over a large value of supply voltages, from 1 to 1.5 V, showing a very good performance also under low power supply conditions.

Fig. 7 Simulated (solid line) and measured (symbols) CG and NF versus RF frequency with VDD as parameter increasing from 1 to 1.5 V

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Fig. 8 Simulated (solid line) and measured (symbols) CG and NF versus RF frequency at VDD = 1.2 V

Fig. 9 Input matching S11

This can be seen in Fig. 7: also with VDD = 1 V the mixer shows 7.5 dB measured CG and 11.4 dB NF. Figure 8 depicts the measured voltage CG and the NF over the input RF frequencies, where the IF of the mixer is 500 MHz. The broadband mixer shows a CG of *9 dB with less than 1 dB variation for the RF bandwidth. The gain maximum is achieved between 5.3 and 5.5 GHz corresponding to the resonance frequency between the DC-feed inductors and parasitic capacitances at the source of the switching transistors. The single sideband NF was measured at the xed IF frequency of 500 MHz. The minimum value of 11 dB has been achieved for 5.5 GHz RF frequency. The input matching is shown in Fig. 9: a broadband characteristic is demonstrated with an input return loss better than -8 dB from 5 to 6 GHz. The power consumption of the mixer core is 4.2 mW. The output buffers show high power consumption, 5.4 mW, that can be actually neglected: on a higher level of integration no 50 X output matching will be needed. Output buffers have also a low pass ltering function achieving 40 dB of LOIF isolation. On the other hand 30 dB LORF isolation was achieved through high layout symmetry. Measured input 1 dB compression point and input third order interception point (IIP3) are -6 dBm and ?2 dBm, respectively. This performance were demonstrated with
Table 1 Comparison with other works fRF (GHz) This work [5] [8] [15] [16] 5.5 2.4 5.2 5.8 5.7 CG (dB) 9 16 16.2 17 -4.5 NF (dB) 11 12.9 9.8 8.5 14.6

Fig. 10 Simulated (solid line) and measured (symbols) IIP3 versus LO amplitude

VLO = 0.5 V approximately. The linearity of the mixer can be improved as well with a larger LO swing as shown in Fig. 10. Table 1 compares the achieved mixer performance with already published works for the same RF frequency (except from [5]). As it can be observed, a good CG and a very low NF with an excellent linearity where achieved under extremely low power consumption compared to the other works.

IIP3 (dBm) 2 1 -5 -6 -15

Chip area (mm2) 0.8 0.03 0.76 0.66 0.25

Technology (lm) 0.13 CMOS 0.18 CMOS 0.18 CMOS 0.18 BiCMOS 0.18 CMOS

PDC (mW) 4.2 8.1 7 18 10.4

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Analog Integr Circ Sig Process (2010) 64:3944 10. Razhavi, V. (1977). RF microelectronics (p. 189). NJ: Prentice Hall PTR. 11. MacEachern, L. A., & Manku, T. (1998). A charge-injection method for Gilbert-cell biasing. IEEE Canadian Conference on Electrical and Computer Engineering, 1, 365368. 12. Lee, S. G., & Choi, J. K. (2000). Current-reuse bleeding mixer. IEEE Electronics Letters, 36(8), 696697. 13. Manstretta, D., et al. (2003). Second-order intermodulation mechanisms in CMOS downconverters. IEEE Journal of SolidState Circuits, 38(3), 394406. 14. Manku, T. (1999). Microwave CMOS-device physics and design. IEEE Journal of Solid-State Circuits, 34(3), 277285. 15. Krcmar, M., Subramanian, V., Deen, M. J., & Boeck, G. (2008). High gain low noise folded CMOS mixer. In Proc. EuWiT conference, October 2008 (pp. 1316). 16. Chu, Y.-K., Liao, C.-H., & Chuang, H.-R. (2003). 5.7 GHz 0.18 lm CMOS gain-controlled LNA and mixer For 802.1la WLAN applications. In IEEE radio frequency integrated circuits symposium, June 2003 (pp. 221224).

5 Conclusion Several CMOS mixer architectures have been proposed during the last years. In this work pros and cons of currently interesting solutions are discussed. The consequences of transistor and voltage supply downscaling have been addressed. Finally, the concept of a folded doublebalanced mixer has been analyzed and a circuit based on this principle was developed. The measurement results we presented show the potentiality of the folded mixer architecture for low voltage applications. The mixer achieves a voltage CG of 9 dB, 11 dB NF and an IIP3 of ?2 dBm. These results are demonstrated under very low power consumption, only 4.2 mW for the mixer core. Discrepancies between measurements and simulations have been observed and analyzed.
Acknowledgements The research leading to these results has received funding from the European Communitys Six Framework Program (FP6/20022006) under Grant Agreement No. 026851 (RESOLUTION). Moreover, the authors would like to thank all the project partners for their valuable contributions.

References
1. Gilbert, B. (1968). A precise four-quadrant multiplier with subnanosecond response. IEEE Journal of Solid-State Circuits, 3, 365373. 2. Lee, T. H., et al. (2002). 5-GHz CMOS wireless LANs. IEEE Transactions on Microwave Theory and Techniques, 50(1), 268 280. 3. Baki, R. A., & El-Gamal, M. N. (2004). RF CMOS fully-integrated heterodyne front-end receivers design technique for 5 GHz applications. IEEE Proceedings of the International Symposium on Circuits and Systems, 1, 960963. 4. Liu, Lu, & Wang, Zhihua. (2005). A new high gain low voltage 1.45 GHz CMOS mixer. IEEE International Symposium on Circuits and Systems, 5, 50235026. 5. Vidojkovic, V., et al. (2005). A low-voltage folded-switching mixer in 0.18 lm CMOS. IEEE Journal of Solid-State Circuits, 40(6), 12591264. 6. Myoung, N. G., et al. (2006) Low-voltage, low-power and highgain mixer based on unbalanced mixer cell. In Proceedings of EuMC, September 2006 (pp. 395398). 7. Kivekas, K., et al. (2001) Design of low-voltage active mixer for direct conversion receivers. In IEEE proceedings of ISCAS, May 2001 (Vol. IV, pp. 382385). 8. Park, J., Lee, C., Kim, B., & Laskar, J. (2006). Design and analysis of low icker-noise CMOS mixers for direct-conversion receivers. IEEE Transactions on Microwave Theory and Techniques, 54(12), 43724380. 9. Lin, M., et al. (2003). A 5-GHz CMOS front-end circuit with low power, low noise and variable gain for WLAN applications. In International symposium on VLSI technology, systems and applications, April 2003 (pp. 280283).

Marko Krcmar was born in Sarajevo, Bosnia Herzegovina, in 1981. He received the B.Sc. and M.Sc. degree from the University of Milano, Italy, in 2003 and 2005, respectively. During his thesis work he studied SiGe HBTs behavioural at very high frequencies. He is currently pursuing the Ph.D. degree at Berlin Institute of Technology, Germany. His main research interests are in the eld of wireless CMOS front-end and local positioning. Georg Boeck received the Dr.-Ing, degree in Electrical Engineering from the Berlin Institute of Technology, Berlin, Germany, in 1984. In 1984, he joined the Siemens Research Labs in Munich, Germany, where his research areas were ber optics and GaAs electronics. Since 1991, he has been the chair of the Microwave Engineering Lab at the Berlin Institute of Technology, Berlin, Germany. His main areas of research are characterization, modeling and design of microwave semiconductor devices, MICs, and MMICs up to the 100 GHz regime. His special interest during the last years has been the development of RF-CMOS integrated circuits for wireless communications. He is a worldwide IEEE Distinguished Microwave Lecturer for the years 20062008 in the eld of Design of RF CMOS Integrated Circuits. In November 2008 he was elevated to Fellow of IEEE.

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