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DESCRIPTION
The LTC2364-16 is a low noise, low power, high speed 18-bit successive approximation register (SAR) ADC. Operating from a 2.5V supply, the LTC2364-16 has a 0V to VREF pseudo-differential unipolar input range with VREF ranging from 2.5V to 5.1V. The LTC2364-16 consumes only 3.4mW and achieves 0.75LSB INL maximum, no missing codes at 16 bits with 94.7dB SNR. The LTC2364-16 has a high speed SPI-compatible serial interface that supports 1.8V, 2.5V, 3.3V and 5V logic while also featuring a daisy-chain mode. The fast 250ksps throughput with no cycle latency makes the LTC2364-16 ideally suited for a wide variety of high speed applications. An internal oscillator sets the conversion time, easing external timing considerations. The LTC2364-16 automatically powers down between conversions, leading to reduced power dissipation that scales with the sampling rate.
L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks and SoftSpan is a trademark of Linear Technology Corporation. All other trademarks are the property of their respective owners. Protected by U.S. Patents, including 7705765.
250ksps Throughput Rate 0.75LSB INL (Max) Guaranteed 16-Bit No Missing Codes Low Power: 3.4mW at 250ksps, 3.4W at 250sps 94.7dB SNR (Typ) at fIN = 2kHz 120dB THD (Typ) at fIN = 2kHz Guaranteed Operation to 125C 2.5V Supply Pseudo-Differential Unipolar Input Range: 0V to VREF VREF Input Range from 2.5V to 5.1V No Pipeline Delay, No Cycle Latency 1.8V to 5V I/O Voltages SPI-Compatible Serial I/O with Daisy-Chain Mode Internal Conversion Clock 16-Lead MSOP and 4mm 3mm DFN Packages
APPLICATIONS
n n n n n n
Medical Imaging High Speed Data Acquisition Portable or Compact Instrumentation Industrial Process Control Low Power Battery-Operated Instrumentation ATE
TYPICAL APPLICATION
32k Point FFT fS = 250ksps, fIN = 2kHz
2.5V 10F VREF 0V 1.8V TO 5V 0.1F AMPLITUDE (dBFS) OVDD 0 20 40 60 80 100 120 140 160 180 0 25 50 75 FREQUENCY (kHz) 100 125 SNR = 94.7dB THD = 121dB SINAD = 94.7dB SFDR = 125dB
+
LT6202
10 10nF
VDD IN+
SAMPLE CLOCK
2.5V TO 5.1V
236416 TA01b
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Supply Voltage (VDD) ...............................................2.8V Supply Voltage (OVDD) ................................................6V Reference Input (REF).................................................6V Analog Input Voltage (Note 3) IN+, IN .........................(GND 0.3V) to (REF + 0.3V) Digital Input Voltage (Note 3) .......................... (GND 0.3V) to (OVDD + 0.3V) Digital Output Voltage (Note 3) .......................... (GND 0.3V) to (OVDD + 0.3V)
Power Dissipation .............................................. 500mW Operating Temperature Range LTC2364C ................................................ 0C to 70C LTC2364I .............................................40C to 85C LTC2364H .......................................... 40C to 125C Storage Temperature Range .................. 65C to 150C
PIN CONFIGURATION
TOP VIEW CHAIN VDD GND IN
+
1 2 3 4 5 6 7 8 17 GND
TOP VIEW CHAIN VDD GND IN+ IN GND REF REF 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 GND OVDD SDO SCK RDL/SDI BUSY GND CNV
DE PACKAGE 16-LEAD (4mm 3mm) PLASTIC DFN TJMAX = 150C, JA = 40C/W EXPOSED PAD (PIN 17) IS GND, MUST BE SOLDERED TO PCB
ORDER INFORMATION
LEAD FREE FINISH LTC2364CMS-16#PBF LTC2364IMS-16#PBF LTC2364HMS-16#PBF LTC2364CDE-16#PBF LTC2364IDE-16#PBF TAPE AND REEL LTC2364CMS-16#TRPBF LTC2364IMS-16#TRPBF LTC2364CDE-16#TRPBF LTC2364IDE-16#TRPBF PART MARKING* 236416 236416 23646 23646 PACKAGE DESCRIPTION 16-Lead Plastic MSOP 16-Lead Plastic MSOP 16-Lead Plastic MSOP 16-Lead (4mm 3mm) Plastic DFN 16-Lead (4mm 3mm) Plastic DFN TEMPERATURE RANGE 0C to 70C 40C to 85C 40C to 125C 0C to 70C 40C to 85C
LTC2364HMS-16#TRPBF 236416
Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container. Consult LTC Marketing for information on non-standard lead based finish parts. For more information on lead free part marking, go to: http://www.linear.com/leadfree/ For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/
236416f
LTC2364-16
The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. (Note 4)
SYMBOL VIN+ VIN VIN+ VIN IIN CIN CMRR PARAMETER Absolute Input Range (IN+) Absolute Input Range (IN) Input Differential Voltage Range Analog Input Leakage Current Analog Input Capacitance Input Common Mode Rejection Ratio Sample Mode Hold Mode fIN = 125kHz CONDITIONS (Note 5) (Note 5) VIN = VIN+ VIN
l l l l
ELECTRICAL CHARACTERISTICS
TYP
UNITS V V V A pF pF dB
45 5 80
The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. (Note 4)
SYMBOL PARAMETER Resolution No Missing Codes Transition Noise INL DNL ZSE FSE Integral Linearity Error Differential Linearity Error Zero-Scale Error Zero-Scale Error Drift Full-Scale Error Full-Scale Error Drift (Note 7)
l
CONVERTER CHARACTERISTICS
CONDITIONS
l l
MIN 16 16
TYP
MAX
0.75 0.5 4 20
DYNAMIC ACCURACY
SYMBOL PARAMETER SINAD SNR
The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C and AIN = 1dBFS. (Notes 4, 8)
CONDITIONS fIN = 2kHz, VREF = 5V fIN = 2kHz, VREF = 5V, (H-Grade) Signal-to-Noise Ratio fIN = 2kHz, VREF = 5V fIN = 2kHz, VREF = 2.5V fIN = 2kHz, VREF = 5V, (H-Grade) fIN = 2kHz, VREF = 2.5V, (H-Grade) THD SFDR Total Harmonic Distortion Spurious Free Dynamic Range 3dB Input Bandwidth Aperture Delay Aperture Jitter Transient Response Full-Scale Step fIN = 2kHz, VREF = 5V fIN = 2kHz, VREF = 2.5V fIN = 2kHz, VREF = 5V
l l l l l l l l l
MAX
UNITS dB dB dB dB dB dB
102 102
dB dB dB MHz ps ps s
103
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The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. (Note 4)
CONDITIONS (Note 5) (Note 9)
l l
MIN 2.5
TYP 0.12
UNITS V mA
The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. (Note 4)
SYMBOL PARAMETER VIH VIL IIN CIN VOH VOL IOZ ISOURCE ISINK High Level Input Voltage Low Level Input Voltage Digital Input Current Digital Input Capacitance High Level Output Voltage Low Level Output Voltage Hi-Z Output Leakage Current Output Source Current Output Sink Current IO = 500A IO = 500A VOUT = 0V to OVDD VOUT = 0V VOUT = OVDD
l l l
MIN
l l
TYP
UNITS V V A pF V
VIN = 0V to OVDD
V A mA mA
POWER REQUIREMENTS
SYMBOL VDD OVDD IVDD IOVDD IPD IPD PD PARAMETER Supply Voltage Supply Voltage Supply Current Supply Current Power Down Mode Power Down Mode Power Dissipation Power Down Mode Power Down Mode
The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. (Note 4)
CONDITIONS
l l
UNITS V V mA mA A A mW W W
250ksps Sample Rate 250ksps Sample Rate (CL = 20pF) Conversion Done (IVDD + IOVDD + IREF, VREF > 2V) Conversion Done (IVDD + IOVDD + IREF, VREF > 2V, H-Grade) 250ksps Sample Rate Conversion Done (IVDD + IOVDD + IREF, VREF > 2V) Conversion Done (IVDD + IOVDD + IREF, VREF > 2V, H-Grade)
l l l
The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. (Note 4)
CONDITIONS
l l
TYP
UNITS ksps s s ns s ns
l l l l
4 20 13 20 20
l l l
ns ns ns
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The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. (Note 4)
CONDITIONS (Notes 11, 12)
l l l l l l l l l l l
MIN 10 4 4 4 1 13.5
TYP
MAX
UNITS ns ns ns ns ns ns
9.5 1 5 16 13
ns ns ns ns ns
Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may effect device reliability and lifetime. Note 2: All voltage values are with respect to ground. Note 3: When these pin voltages are taken below ground or above REF or OVDD, they will be clamped by internal diodes. This product can handle input currents up to 100mA below ground or above REF or OVDD without latch-up. Note 4: VDD = 2.5V, OVDD = 2.5V, REF = 5V, fSMPL = 250kHz. Note 5: Recommended operating conditions. Note 6: Integral nonlinearity is defined as the deviation of a code from a straight line passing through the actual endpoints of the transfer curve. The deviation is measured from the center of the quantization band.
Note 7: Zero-scale error is the offset voltage measured from 0.5LSB when the output code flickers between 0000 0000 0000 0000 and 0000 0000 0000 0001. Full-scale error is the deviation of the last code transition from ideal and includes the effect of offset error. Note 8: All specifications in dB are referred to a full-scale 5V input with a 5V reference voltage. Note 9: fSMPL = 250kHz, IREF varies proportionately with sample rate. Note 10: Guaranteed by design, not subject to test. Note 11: Parameter tested and guaranteed at OVDD = 1.71V, OVDD = 2.5V and OVDD = 5.25V. Note 12: tSCK of 10ns maximum allows a shift clock frequency up to 100MHz for rising capture.
tWIDTH 50%
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LTC2364-16
fSMPL = 250ksps, unless otherwise noted. Integral Nonlinearity vs Output Code
1.0 0.8 0.6 DNL ERROR (LSB) INL ERROR (LSB) 0.4 0.2 0.0 0.2 0.4 0.6 0.8 1.0 0 16384 32768 49152 OUTPUT CODE 65536
236416 G01
DC Histogram
100000 90000 80000 70000 COUNTS 60000 50000 40000 30000 20000 10000 0 = 0.5
0.1 0.0 0.1 0.2 0.3 0.4 0.5 0 16384 32768 49152 OUTPUT CODE 65536
236416 G02
32676
32677
32678 CODE
32679
32680
236416 G03
160
25
75 50 FREQUENCY (kHz)
100
125
236416 G06
100 105
SNR
SINAD
110 115 120 125 130 135 140 145 THD 2ND 3RD
93.0 40
30
0
236416 G07
90 2.5
3.5
5
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150 2.5
5
236416 G09
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INL/DNL vs Temperature
145 55 35 15
1.0 55 35 15
0.15
90 CMRR (dB) 85 80 75 70
0.10
0.05
2.5
5
236416 G18
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IN+ IN
+
16-BIT SAMPLING ADC
SPI PORT
BUSY
TIMING DIAGRAM
Conversion Timing Using the Serial Interface
CHAIN, RDL/SDI = 0 CNV
BUSY HOLD
CONVERT ACQUIRE
POWER-DOWN
SCK
D2 D1 D0
236416 TD01
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UNIPOLAR ZERO
1 LSB
ANALOG INPUT The analog inputs of the LTC2364-16 are pseudo-differential in order to reduce any unwanted signal that is common to both inputs. The analog inputs can be modeled by the equivalent circuit shown in Figure 3. The diodes at the input provide ESD protection. In the acquisition phase, each input sees approximately 45pF (CIN) from the sampling CDAC in series with 40 (RON) from the on-resistance of the sampling switch. The IN+ input draws a current spike while charging the CIN capacitor during acquisition. During conversion, the analog inputs draw only a small leakage current.
REF RON 40 CIN 45pF
IN+
REF IN RON 40
CIN 45pF
BIAS VOLTAGE
236416 F03
Figure 3. The Equivalent Circuit for the Differential Analog Input of the LTC2364-16
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High quality capacitors and resistors should be used in the RC filters since these components can add distortion. NPO and silver mica type dielectric capacitors have excellent linearity. Carbon surface mount resistors can generate distortion from self heating and from damage that may occur during soldering. Metal film surface mount resistors are much less susceptible to both problems. Pseudo-Differential Unipolar Inputs For most applications, we recommend the low power LT6202 ADC driver to drive the LTC2364-16. With a low noise density of 1.9nV/Hz and a low supply current of 3mA, the LT6202 is flexible and may be configured to convert signals of various amplitudes to the 0V to 5V input range of the LTC2364-16. To achieve the full distortion performance of the LTC2364-16, a low distortion single-ended signal source driven through the LT6202 configured as a unity-gain buffer as shown in Figure 4 can be used to get the full data sheet THD specification of 120dB. The LT6202 can also be used to buffer and convert large true bipolar signals which swing below ground to the 0V to 5V input range of the LTC2364-16. Figure 5a shows the LT6202 being used to convert a 10V true bipolar signal for use by the LTC2364-16. In this case, the LT6202 is configured as an inverting amplifier stage, which acts to attenuate and level shift the input signal to the 0V to 5V input range of the LTC2364-16. In the inverting configuration, the single-ended input signal source no longer directly drives a high impedance input. The input impedance is instead set by resistor RIN. RIN must be chosen carefully based on the source impedance of the signal source. Higher values of RIN tend to degrade both the noise and distortion of the LT6202 and LTC2364-16 as a system. Table 1 shows the resulting SNR and THD for several values of RIN, R1, R2, R3 and R4 in this configuration. Figure 5b shows the resulting FFT when using the LT6202 as shown in Figure 5a.
+
LT6202
IN+ LTC2364-16
Another filter network consisting of LPF2 should be used between the buffer and ADC input to both minimize the noise contribution of the buffer and to help minimize disturbances reflected into the buffer from sampling transients. Long RC time constants at the analog inputs will slow down the settling of the analog inputs. Therefore, LPF2 requires a wider bandwidth than LPF1. A buffer amplifier with a low noise density must be selected to minimize degradation of the SNR.
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ADC REFERENCE
3
R4 402
+
LT6202 1
5V 0V
R1 499 200pF
236416 F05a
The LTC2364-16 requires an external reference to define its input range. A low noise, low temperature drift reference is critical to achieving the full data sheet performance of the ADC. Linear Technology offers a portfolio of high performance references designed to meet the needs of many applications. With its small size, low power and high accuracy, the LTC6655-5 is particularly well suited for use with the LTC2364-16. The LTC6655-5 offers 0.025% (max) initial accuracy and 2ppm/C (max) temperature coefficient for high precision applications. The LTC6655-5 is fully specified over the H-grade temperature range and complements the extended temperature operation of the LTC2364-16 up to 125C. We recommend bypassing the LTC6655-5 with a 47F ceramic capacitor (X5R, 0805 size) close to the REF pin. The REF pin of the LTC2364-16 draws charge (QCONV) from the 47F bypass capacitor during each conversion cycle. The reference replenishes this charge with a DC current, IREF = QCONV/tCYC. The DC current draw of the REF pin, IREF, depends on the sampling rate and output code. If the LTC2364-16 is used to continuously sample a signal at a constant rate, the LTC6655-5 will keep the deviation of the reference voltage over the entire code span to less than 0.5LSBs. When idling, the REF pin on the LTC2364-16 draws only a small leakage current (< 1A). In applications where a burst of samples is taken after idling for long periods as shown in Figure 6, IREF quickly goes from approximately 0A to a maximum of 0.2mA at 250ksps. This step in DC current draw triggers a transient response in the reference that must be considered since any deviation in the reference output voltage will affect the accuracy of the output
236416 F05b
Figure 5b. 32k Point FFT Plot with fIN = 2kHz for Circuit Shown in Figure 5a Table 1. SNR, THD vs RIN for 10V Input Signal
RIN () 2k 10k 100k R1 () 499 2.49k 24.9k R2 () 499 2.49k 24.9k R3 () 2k 10k 100k R4 () 402 2k 20k SNR (dB) 94.6 94.4 92.4 THD (dB) 99.2 93.8 93.7
CNV
236416 F06
IDLE PERIOD
IDLE PERIOD
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REF
VDD
LTC2364-16
25
50 75 FREQUENCY (kHz)
100
125
236416 F08
Figure 7. A Schottky Diode Between REF and VDD Maintains REF > 2V for Applications Where the Reference May Be Powered Down
Total Harmonic Distortion (THD) Total Harmonic Distortion (THD) is the ratio of the RMS sum of all harmonics of the input signal to the fundamental itself. The out-of-band harmonics alias into the frequency band between DC and half the sampling frequency (fSMPL/2). THD is expressed as: THD= 20log V22 + V32 + V42 ++ VN2 V1
DYNAMIC PERFORMANCE Fast Fourier Transform (FFT) techniques are used to test the ADCs frequency response, distortion and noise at the rated throughput. By applying a low distortion sine wave and analyzing the digital output using an FFT algorithm, the ADCs spectral content can be examined for frequencies outside the fundamental. The LTC2364-16 provides guaranteed tested limits for both AC distortion and noise measurements. Signal-to-Noise and Distortion Ratio (SINAD) The signal-to-noise and distortion ratio (SINAD) is the ratio between the RMS amplitude of the fundamental input frequency and the RMS amplitude of all other frequency components at the A/D output. The output is band-limited to frequencies from above DC and below half the sampling frequency. Figure 8 shows that the LTC2364-16 achieves a typical SINAD of 94.7dB at a 250kHz sampling rate with a 2kHz input. Signal-to-Noise Ratio (SNR) The signal-to-noise ratio (SNR) is the ratio between the RMS amplitude of the fundamental input frequency and
where V1 is the RMS amplitude of the fundamental frequency and V2 through VN are the amplitudes of the second through Nth harmonics. POWER CONSIDERATIONS The LTC2364-16 provides two power supply pins: the 2.5V power supply (VDD), and the digital input/output interface power supply (OVDD). The flexible OVDD supply allows the LTC2364-16 to communicate with any digital logic operating between 1.8V and 5V, including 2.5V and 3.3V systems. Power Supply Sequencing The LTC2364-16 does not have any specific power supply sequencing requirements. Care should be taken to adhere
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new conversion is initiated on the rising edge of CNV. During power down, data from the last conversion can be clocked out. To minimize power dissipation during power down, disable SDO and turn off SCK. The auto power-down feature will reduce the power dissipation of the LTC2364-16 as the sampling frequency is reduced. Since power is consumed only during a conversion, the LTC2364-16 remains powered down for a larger fraction of the conversion cycle (tCYC) at lower sample rates, thereby reducing the average power dissipation which scales with the sampling rate as shown in Figure 9.
1.6 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0 1 50 IOVDD 100 150 200 SAMPLING RATE (kHz) IREF 250
236416 F09
CNV Timing The LTC2364-16 conversion is controlled by CNV. A rising edge on CNV will start a conversion and power up the LTC2364-16. Once a conversion has been initiated, it cannot be restarted until the conversion is complete. For optimum performance, CNV should be driven by a clean low jitter signal. Converter status is indicated by the BUSY output which remains high while the conversion is in progress. To ensure that no errors occur in the digitized results, any additional transitions on CNV should occur within 40ns from the start of the conversion or after the conversion has been completed. Once the conversion has completed, the LTC2364-16 powers down and begins acquiring the input signal. Acquisition A proprietary sampling architecture allows the LTC2364-16 to begin acquiring the input signal for the next conversion 527ns after the start of the current conversion. This extends the acquisition time to 3.460s, easing settling requirements and allowing the use of extremely low power ADC drivers. (Refer to the Timing Diagram.) Internal Conversion Clock The LTC2364-16 has an internal clock that is trimmed to achieve a maximum conversion time of 3s. Auto Power-Down The LTC2364-16 automatically powers down after a conversion has been completed and powers up once a
IVDD
DIGITAL INTERFACE The LTC2364-16 has a serial digital interface. The flexible OVDD supply allows the LTC2364-16 to communicate with any digital logic operating between 1.8V and 5V, including 2.5V and 3.3V systems. The serial output data is clocked out on the SDO pin when an external clock is applied to the SCK pin if SDO is enabled. Clocking out the data after the conversion will yield the best performance. With a shift clock frequency of at least 20MHz, a 250ksps throughput is still achieved. The serial output data changes state on the rising edge of SCK and can be captured on the falling edge or next rising edge of SCK. D15 remains valid till the first rising edge of SCK. The serial interface on the LTC2364-16 is simple and straightforward to use. The following sections describe the operation of the LTC2364-16. Several modes are provided
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CONVERT CNV CHAIN LTC2364-16 BUSY SDO SCK CLK DIGITAL HOST IRQ DATA IN
RDL/SDI
CONVERT
CONVERT
tCNVL
BUSY
tQUIET
tDSDO D13 D1 D0
236416 F10
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15
CHAIN
CHAIN
BUSY SDO
CONVERT
POWER-DOWN ACQUIRE
CONVERT
tCNVL
RDL/SDIB tSCK SCK 1 2 3 tHSDO SDO Hi-Z tEN D15A D14A D13A tDSDO D1A tDIS D0A Hi-Z D15B D14B D13B D1B D0B Hi-Z
236416 F11
tSCKH 14 15 16 tSCKL 17 18 19 30 31 32
tQUIET
Figure 11. Normal Mode With Multiple Devices Sharing CNV, SCK and SDO
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number of converters. Figure 12 shows an example with two daisy-chained devices. The MSB of converter A will appear at SDO of converter B after 16 SCK cycles. The MSB of converter A is clocked in at the SDI/RDL pin of converter B on the rising edge of the first SCK.
DIGITAL HOST
CONVERT
POWER-DOWN ACQUIRE
CONVERT
tCYC tCNVL
CNV tHOLD BUSY tBUSYLH tSCKCH SCK 1 2 3 tSSDISCK tHSDISCK SDOA = RDL/SDIB D15A tDSDOBUSYL SDOB D15B D14B D13B D1B D0B D15A D14A D1A D0A
236416 F12
tCONV
tQUIET
14
15
D14A
D13A
D1A
D0A
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19
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R1 33 +3.3V C2 0.1F +3.3V C3 0.1F 1 +3.3V R46 C56 0.1F 3 JP6 FS 1 2 3 +3.3V C13 0.8VREF 0.1F VREF R8 33 DC590 DETECT TO CPLD U3 NL17SZ74 5 3 DB17 DB16 J2 CON-EDGE 40-100 CLR\ Q\ PR\ Q 6 5 4 R4 7 33 4 CP GND 8 D VCC 2 +3.3V C4 0.1F 5 2 C11 0.1F R31 OPT +3.3V C7 0.1F C20 47F 6.3V 0805 4 U4 NC7SVU04P5X 2 CNVST_33 FROM CPLD 9V TO 10V
+3.3V
R2 1k
+3.3V C1 0.1F
BOARD LAYOUT
J1 CLKIN
R5 49.9 1206
U2 R6 3 U8 3 NC7SZ04P5X NC7SVU04P5X 1k
U20 LTC6655AHMS8-5 8 SHDN GND 7 VIN OUT_F 6 GND OUT_S 5 GND GND
JP1 HD1X3-100
COUPLING AC DC
R15 OPT
R9 OPT
VREF/2
EXT C63 10F 6.3V C43 0.1F C44 1F C60 0.1F 9V TO 10V C59 1F
E7
EXT_CM
HD1X3-100
C46 1F
R40 OPT
COUPLING AC DC
JP5 HD1X3-100
R39 0
R41 OPT
+
HD1X3-100 U6 OPT NC7SZ66P5X 5 C39 CNV VCC 0.01F R16 9 2 B A 1 0 4 NPO CNV 13 SCK IN+ SCK OE 4 C65 14 SDO SDO OPT R19 LTC2364-16 GND 11 BUSY BUSY 0805 NPO 0 3 IN 12 RD RDL/SDI C40 5 R58 OPT R7 +3.3V NPO R38 1k OPT U9 C15 NC7SZ04P5X 5 0.1F 2 4 3 R17 R13 2k 1k J3 DC590 R10 4.99k SDO 1 3 5 7 9 11 13 2 4 6 8 10 12 14 U7 C14 0.1F 8 24LC025-I/ST VCC SCL SCK SDA WP CNV ARRAY A2 EEPROM A1 A0 VSS 4 6 5 7 3 2 1
AIN+ OUT1 1
R14 0
C17 10F R32 0 C6 10F 6.3V DB0 DB1 DB2 DB3 DB4 DB5 DB6 DB7 DB8 DB9 DB10 DB11 DB12 DB13 DB14 DB15
V+ U15 5 LT6202CS5 V+
39 37 35 33 31 29 27 25 23 21 19 17 15 13 11 9 7 5 3 1
40 38 36 34 32 30 28 26 24 22 20 18 16 14 12 10 8 6 4 2
R11 4.99k
R12 4.99k
236416 BL
LTC2364-16
21
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0.70 0.05 3.60 0.05 2.20 0.05 3.30 0.05 1.70 0.05 PACKAGE OUTLINE 0.25 0.05 0.45 BSC 3.15 REF RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED
4.00 0.10 (2 SIDES) R = 0.05 TYP 3.00 0.10 (2 SIDES) PIN 1 TOP MARK (SEE NOTE 6) 0.200 REF 0.75 0.05
R = 0.115 TYP
0.40 0.10 16
3.30 0.10 1.70 0.10 PIN 1 NOTCH R = 0.20 OR 0.35 45 CHAMFER 1 0.23 0.05 0.45 BSC 3.15 REF
(DE16) DFN 0806 REV
0.00 0.05
NOTE: 1. DRAWING PROPOSED TO BE MADE VARIATION OF VERSION (WGED-3) IN JEDEC PACKAGE OUTLINE MO-229 2. DRAWING NOT TO SCALE 3. ALL DIMENSIONS ARE IN MILLIMETERS 4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE 5. EXPOSED PAD SHALL BE SOLDER PLATED 6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE
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0.254 (.010)
GAUGE PLANE
0.18 (.007)
SEATING PLANE
1234567 8
NOTE: 1. DIMENSIONS IN MILLIMETER/(INCH) 2. DRAWING NOT TO SCALE 3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.006") PER SIDE 4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS. INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE 5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX
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Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
23
R4 402
10F
R3 2k
LTC2364-16
3V
RELATED PARTS
PART NUMBER DESCRIPTION COMMENTS ADCs LTC2379-18/LTC2378-18 18-Bit, 1.6Msps/1Msps/500ksps/250ksps Serial, Low 2.5V Supply, Differential Input, 101.2dB SNR, 5V Input Range, LTC2377-18/LTC2376-18 Power ADC DGC, Pin-Compatible Family in MSOP-16 and 4mm 3mm DFN-16 Packages LTC2380-16/LTC2378-16 16-Bit, 2Msps/1Msps/500ksps/250ksps Serial, Low 2.5V Supply, Differential Input, 96.2dB SNR, 5V Input Range, DGC, LTC2377-16/LTC2376-16 Power ADC Pin-Compatible Family in MSOP-16 and 4mm 3mm DFN-16 Packages LTC2383-16/LTC238216-Bit, 1Msps/500ksps/250ksps Serial, Low 2.5V Supply, Differential Input, 92dB SNR, 2.5V Input Range, Pin16/LTC2381-16 Power ADC Compatible Family in MSOP-16 and 4mm 3mm DFN-16 Packages LTC2393-16/LTC239216-Bit, 1Msps/500ksps/250ksps Parallel/Serial ADC 5V Supply, Differential Input, 94dB SNR, 4.096V Input Range, Pin16/LTC2391-16 Compatible Family in 7mm 7mm LQFP-48 and QFN-48 Packages LTC1864/LTC1864L 16-Bit, 250ksps/150ksps 1-Channel Power ADC 5V/3V Supply, 1-Channel, 4.3mW/1.5mW, MSOP-8 Package LTC1865/LTC1865L 16-Bit, 250ksps/150ksps 2-Channel Power ADC 5V/3V Supply, 2-Channel, 4.3mW/1.3mW, MSOP-10 Package DACS LTC2757 18-Bit, Single Parallel IOUT SoftSpan DAC 1LSB INL/DNL, Software-Selectable Ranges, 7mm 7mm LQFP-48 Package 1LSB INL/DNL, MSOP-8 Package, 0V to 5V Output LTC2641 16-Bit/14-Bit/12-Bit Single Serial VOUT DACs SC70 6-Pin Package, Internal Reference, 1LSB INL (12 Bits) LTC2630 12-Bit/10-Bit/8-Bit Single VOUT DACs References LTC6655 Precision Low Drift Low Noise Buffered Reference 5V/2.5V, 5ppm/C, 0.25ppm Peak-to-Peak Noise, MSOP-8 Package LTC6652 Precision Low Drift Low Noise Buffered Reference 5V/2.5V, 5ppm/C, 2.1ppm Peak-to-Peak Noise, MSOP-8 Package Amplifiers Single/Dual 100MHz Rail-to-Rail Input/Output Noise 1.9nVHz, 3mA Maximum, 100MHz Gain Bandwidth LT6202/LT6203 Low Power Amplifiers LT6200/LT6200-5/ 165MHz/800MHz/1.6GHz Op Amp with Low Noise Voltage: 0.95nV/Hz (100kHz), Low Distortion: 80dB at LT6200-10 Unity Gain/AV = 5/AV = 10 1MHz, TSOT23-6 Package
236416f
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