Common Source Amplifier

Aim: Design Common Source Amplifier by calculating the resistor & capacitor values for given specifications. Check the operation in Software and Hardware. Specifications: Transistor: 2N5459 VCC = 24 V RL = 120K ID = 1.5mA IDSS = 16mA VGS(off) = 8V f = 100Hz

For Software Execution Components Required: 1. P-IV Configured Computer System with Windows Xp 2. Tina Software For Hardware Execution Components Required: S. No. 1 2 3 4 5 6 7 8 9 Components Regulated Power Supply Function Generator Resistors Capacitors Transistor CRO CRO Probes Connection Wires Bread Board Single Strand 2N5459 (0-20)MHz 1 1 2 Required 1 Specification (0-32)V (0-1)MHz Quantity 1 1

Theory: The design of FET bias circuits is just as simple as the design of BJT bias circuits. One major difference is that FET circuit design normally uses a graphical approach involving the drawing of a bias line on the device transfer characteristics, as in the case of FET circuit analysis. If the type number of the FET to be used in the circuit is known, the maximum and minimum transfer characteristics are available or can be plotted. A maximum drain current (ID(max)) is selected at a point on the maximum transfer characteristic and bias line is drawn through this point. As will be explained, this procedure applies to all types of bias circuits. The selected level of I D(max) is used to calculate the values of resistors connected to the drain and source terminals. Instead of using the maximum transfer characteristics, suppose that the minimum characteristics, or some characteristic between the maximum and minimum, is used in the circuit design. Now if the FET happens to have the maximum transfer characteristic for the device type

number, ID will be larger than the design value. Consequently, the resistor voltage drops (IDRD and IDRS) will be greater than the intended. In this case VDS will be smaller than its design level, the FET may be forced into the channel ohmic region of its characteristics, and the circuit is unlikely to its characteristics, and the circuit is unlikely to function correctly. Therefore, always use the device maximum transfer characteristic when designing a FET bias circuit. As already explained, a FET has a very high input resistance, so high-value bias resistors can be used at the gate terminal. However there are disadvantages to using extreme high resistance values. A charge accumulated at the gate can take a long time to leak off through a very high resistance. In this case, the gate voltage might not be a stable quantity, and consequently, the drain current could be unpredictable. High-value bias resistors also generate unwanted thermal noise and them readily pick-up stray radio-frequency signals. For these reasons, 1M is normally a reasonable upper limit for bias resistors. Design Calculations:

U1 24

R3 4.7M

R4 6.8k

C3 150n C1 20n T1 2N5459 R5 120k + VG1

VF1

VF2

R2 6.8k

R6 600

C2 10u

R1