INTRODUCTION

Processor simply meant for a calculator. A processor includes both user-visible registers and control/status registers. The former may be referenced, implicitly or explicitly, in machine instructions. User-visible registers may be general purpose or have a special use, such as fixedpoint or floating-point numbers, address, indexes and segments pointers. Control and status registers are used to control the operation of the CPU. One obvious example is the program counter. Processors make use of instruction pipelining g to speed up execution. In essence, pipelining involves breaking u the instruction cycle into a number of separate stages that occur in sequence, such as fetch instruction, decode instruction, operand addresses, fetch operands, execute instruction, and write operand result. This design processor represents the first layout for a microprocessor that we have done. The 8BIT Processor is an Accumulator based 8-bit microprocessor that is intended to be used as the CPU in microcomputer. Its ALU, internal registers and its instructions have designed to work with 8-bit words. The 8-BIT Processor have 8-bit common data/address buses, so it can read data from or write data to memory and ports 8bit at a time.

OBJECTIVES
To design an 8-bit processor. To familiarize with the basic operation of processor and its interface with memory. To Acquaintance with different sets of instructions and their use in the design of processor To use RTL with different instruction sets.

GENERAL PARTS OF MICROPROCESSOR:

The microprocessor can be divided into three segments: - Arithmetic/logic unit (ALU) - register array - Control unit Arithmetic/logic unit: This is the area of the microprocessor where various computing functions are performed on data. The ALU unit performs such arithmetic operations as addition and subtraction, and such logic operations as AND, OR, and exclusive OR. COA lab Report Page 1

Register array: This area of the microprocessor consists of various registers. These registers are primarily used to store data temporarily during the execution of a program and are Accessible to the user through instructions. Control unit: The control unit provides the necessary timing and control signals to all the operations. It controls the flow of data between the microprocessor and memory and peripherals.

MICROPROCESSOR ALU Register Array INPUT/OUTPUT

SYSTEM BUS

Control
ROM
Memory

R/WM

FIGURE:MICROPROCESSOR-BASED SYSTEM WITH BUS ARCHITECTURE

ADDRESSING MODES:
The address field or fields in a typical instruction format are relatively small. We would like to be able to reference a large range of locations in main memory. To achieve this objective, a variety of addressing techniques has been employed. The various formats of specifying the operands are called the addressing modes. We are going to include, as far as possible, the following addressing modes in the instruction set of our microprocessor. 1. Immediate Addressing 2. Direct Addressing 3. Register Addressing 4. Indirect Addressing 5. Register indirect addressing COA lab Report Page 2

Immediate addressing: The simplest form of addressing is immediate addressing, in which the operand is actually present in the instruction. This mode can be used to define and use constants or set initial values of variables. The advantage of immediate addressing is that no memory reference other than the instruction fetch is required to obtain the operand, thus saving one memory cycle in the instruction cycle. Instructions like ANI 60H, ORI 60H, and MVI 60 H fall under this category. Direct Addressing: A very simple form of addressing is direct addressing, in which the address field contains the effective address of the operand. It requires only one memory reference and no special calculation. Instructions like LDA 2000H, STA 2000H fall under this category. Register Addressing: Register addressing is similar to direct addressing. The only difference is that the address field refers to a register rather than a memory address. The advantages of register addressing are that (1) only a small address field is needed in the instruction and (2) no memory references are required. Instructions like ADD B, SUB B, INCR B, MOV A, B fall under this category. Indirect Addressing: With direct addressing, the length of the address field is usually less than the word length, thus limiting the address range. One solution is to have the address field refer to the address of a word in memory, which in turn contains a full-length address of the operand. This is known as indirect addressing. Register Indirect Addressing: Register indirect addressing is analogous to indirect addressing. The only difference is whether the address field refers to a memory location or a register. The instruction LDAX B falls under this category. This instruction moves the content of the memory location stored in register B to the Accumulator.

Registers:
Memory buffer register (MBR): Contains a word to be stored in memory, or is used to receive a word from memory. Memory addresses register (MAR): Specifies the address in memory of the word to be written from or read into the MBR Instruction registers (IR): Contains the 8-bit opcode instruction being executed. Program counter (PC): Contains the address of the next instruction-pair to be fetched from memory. COA lab Report Page 3

Accumulator (A): Employed to hold temporarily operands and results of ALU operation.

Processor Organization:
To understand the organization of the CPU, Let us consider the requirement plead on the CPU, the things that it must do: Fetch instruction: The CPU reads an instruction from memory. Interrupts instruction: The instruction is decoded to determine what Action is required. Fetch data: The execution of an instruction may require reading data from memory or I/O module Process data: The execution of an instruction may require performing some arithmetic or logical on data. Write data: The results of an execution may require writing data to memory or an I/O module.

Instructions:
The microprocessor will be performing the instructions of following 5 groups: 1) Arithmetic Group 2) Logical Group 3) Data Transfer Group 4) Branching Group
S.No. [A] 1. 2. 3. 4. Operation ARITHMETIC ADD SUB INR DCR B B C B 1 1 1 1 Adds content of register to the content of A & stores the result in A. Subtracts the content of register to the content of A & stores the result in A. Increase the content of register by 1. Decrease the content of register by 1. Opcode Operand No. of Bytes Description

COA lab Report

Page 4

SUI

8-Bit Address

Subtracts the content of specified address to the content of A & stores the result in A. Logically ANDs the contents of register with content of A and store the result in A. Logically ORs the contents of register with content of A and store the result in A. Logically Exclusive ORs the contents of register with content of A and store the result in A. Complements the bits of Accumulator. Copies data from source register to destination register. Loads 8-bits data of specified memory address into the Accumulator. Load Accumulator Direct. The content of memory location specified by 8-bit address in the operand are copied to the Accumulator. Example: LDA 02H. Adds the 8-bit data to the contents of the Accumulator. Contents of Accumulator are copied into memory location specified. The contents of register B are exchanged with the contents of register C. The contents of A are copied to memory location pointed by SP The contents of memory location pointed by SP is copied to A Jump to Program Control unconditionally. Jump to Program Control conditionally.

[B] 6. 7. 8.

LOGICAL AND ORA XRA B B B 1 1 1

9. [C] 10. 11.. DATA TRANSFER

CMA MOV MVI B,C A,#8-bit Address 8-Bit Address

1 1 2

12.

LDA

13. 14. 15. [D] 16. 17. [E] 18. 19. STACK OPERATION

ADI STA XCHG

8-bit data 8-Bit Address B

2 2 1

PUSH POP PROGRAM TRANSFER JMP CALL

A A

1 1

8-Bit Address 8-Bit Address

2 2

COA lab Report

Page 5

20.

RET

None

Jump to Program Control after completing the subroutine.

Register Transfer Language:

1. ADI 8-bit t1: MAR t2: MBR PC t3: t4: t5: t6: t7: t8: IR (PC) (MEM) PC+1 MBR PC (MEM) (A) + MBR (Temp)

MAR MBR Temp A Reset

2. ADD B, 8-bit t1 : MAR (PC) t2 : MBR (Mem) PC PC + 1 t3 : IR (MBR) t4 : Temp (A) + (B) t5 : A (Temp) t6 : Reset 3. SUB B, 8-bit t1 : MAR (PC) t2 : MBR (Mem) PC PC + 1 t3 : IR (MBR) t4 : Temp (A) B t5 : A (Temp) t6 : Reset 4. INR C t1 : MAR (PC) t2 : MBR (Mem) COA lab Report Page 6

t3 t4 t5 t6

: : : :

PC PC + 1 IR (MBR) Temp (C) + 1 B (Temp) Reset

5. DCR B t1 : MAR (PC) t2 : MBR (Mem) PC PC + 1 t3 : IR (MBR) t4 : Temp (B) 1 t5 : B (Temp) t6 : Reset 6. AND B t1 : MAR (PC) t2 : MBR (Mem) PC PC + 1 t3 : IR (MBR) t4 : Temp (A) AND (B) t5 : A (Temp) t6 : Reset 7. ORA B t1 : MAR (PC) t2 : MBR (Mem) PC PC + 1 t3 : IR (MBR) t4 : Temp (A) OR (B) t5 : A (Temp) t6 : Reset 8. XORA B t1 : MAR (PC) t2 : MBR (Mem) PC PC + 1 t3 : IR (MBR) t4 : Temp (A) XOR (B) t5 : A (Temp) t6 : Reset 9. CMA t1 : MAR (PC) Page 7

COA lab Report

t2 : t3 t4 t5 t6 : : : :

MBR (Mem) PC PC + 1 IR (MBR) Temp Complement (A) A (Temp) Reset

10. MOV B, C t1 : MAR (PC) t2 : MBR (Mem) PC PC + 1 t3 : IR (MBR) t4 : B (C) t5 : Reset 1. MVI A,8-bit t1 : MAR (PC) t2 : MBR (Mem) PC PC + 1 t3 : IR (MBR) t4 : MAR (PC) t5 : MBR (Mem) PC PC + 1 t6 : A (MBR) t7 : Reset

12. LDA, 8-bit t1 : MAR (PC) t2 : MBR (Mem) PC PC + 1 t3 : IR (MBR) t4 : MAR (PC) t5 : MBR (Mem) PC PC + 1 t6 : MAR (MBR) t7 : MBR (Mem) t8 : A (MBR) t9 : Reset 13. STA 8-bit t1 : MAR (PC) t2 : MBR (Mem) COA lab Report Page 8

t3 : t4 : t5 : t6 t7 t8 t9 : : : :

PC PC + 1 IR (MBR) MAR (PC) MBR (Mem) PC PC + 1 MAR (MBR) MBR (A) Mem (MBR) Reset

14. XCHG B t1 : t2 : t3 t4 t5 t6 t7 : : : : : MAR (PC) MBR (Mem) PC PC + 1 IR (MBR) temp B B (A) A (temp) Reset

15. JMP 8 -bit t1 : MAR (PC) t2 : MBR (Mem) PC PC + 1 t3 : IR (MBR) t4 : MAR (PC) t5 : MBR (Mem) t6 : PC (MBR) t7 : Reset 16. CALL 8- bit t1 : MAR (PC) t2 : MBR (Mem) PC PC + 1 t3 : IR (MBR) t4 : MAR (PC) t5 : MBR (Mem) PC PC + 1 t6 : Temp2 (MBR) t7 : Temp SP + 1 t8 : SP (Temp) MAR (Temp) t9 : MBR (PC) COA lab Report Page 9

t10 : t11 : t12 : 17. RET t1 : t2 : t3 t4 t5 t6 t7 t8 t9 : : : : : : :

Mem (MBR) PC (Temp2) Reset

MAR (PC) MBR (Mem) PC PC + 1 IR (MBR) MAR (SP) MBR (Mem) Temp SP - 1 SP (Temp) PC (MBR) Reset

18. PUSH A t1 : MAR (PC) t2 : MBR (Mem) PC PC + 1 t3 : IR (MBR) t4 : Temp1 (PC) t5 : Temp(SP)+1 t6 : SPTemp t7 : MAR SP t8 : MBR (A) t9 : Mem (MBR) t10 : PC (Temp1) t11 : Reset 19. POP A t1 : MAR (PC) t2 : MBR (Mem) PC PC +1 t3 : MAR (MBR) t4 : Temp1PC t5 : PC (SP) t6 : MAR (PC) t7 : MBR (MEM) t8 : A (MBR) t9 : Temp (SP) -1 COA lab Report Page 10

t10 : t11 : t12 :

Sp Temp PC (Temp1) Reset

20. SUI, 8-BIT t1 : MAR (PC) t2 : MBR (Mem) PC PC + 1 t3 : IR (MBR) t4 : MAR (PC) t5 : MBR (MEM) PC PC + 1 t6: TEMP (A) (MBR) t7 : (A) TEMP t8 : Reset

COA lab Report

Page 11