A novel Realtime Time-domain EMI Measurement System based on Field Programmable Gate Arrays

Stephan Braun, Mohammed Al-Qedra and Peter Russer

Munich University of Technology, Institute for High-Frequency Engineering, Munich, Germany, stephan.braun@tum.de
Abstract In the past and now measurements are carried out by EMI-Receivers operating in frequency-domain. By a time-domain EMI (TDEMI) measurement system the measurement time can be reduced by several orders of magnitude. In this paper a novel real-time TDEMI measurement system that uses a direct hardware implementation of the Short Time Fast Fourier Transform (STFFT) and the detector modes is described. The hardware implementation on Field Programmable Gate Arrays (FPGAs) allows to process the input signal in realtime. By the continuous processing via the STFFT the IF-Signal for selectable frequency can be provided as requested by CISPR 16-1-1. By simulations on a proposed FPGA it is shown that the measurement time can be reduced by a factor of about 2000 in comparison to conventional EMI Receivers. The dynamic range of a xed point FFT has been investigated and it has been shown that a 16-Bit xed point arithmetic is sufcient to fulll the requirements according to the international EMC standards. EMI Signals have been recorded and processed by a hardware model. The results have been compared with measurements obtained with a conventional EMI Receiver in the frequency range 30 MHz - 1 GHz.

I. I NTRODUCTION EMC and EMI measurement equipment which allows to extract comprehensive and accurate information within short measurement times will reduce the costs and improve the quality in circuit and system development. Today EMI receivers require long measurement times up to several hours for a frequency band from 30 1000 MHz. Spectral estimation via time-domain recording the complete signal and Fast Fourier Transformation (FFT) allows reducing the measurement time by orders of magnitude. The block diagram of a TDEMI Measurement System is shown in Fig. 1. The EMI Signal is received
Multiresolution TDEMI Measurement System

LP

Floating Point ADC

Digital Signal Processing

Amplitude Spectrum

solved by various algorithms. An algorithm that allows to perform measurements under the peak, average and rms detector modes have been presented in [1]. The EMI-signal is processed in a non-continuous way, by calculating the actual spectrum and a comparison to a already stored signal. The stored spectrum is updated by the spectrum that is calculated from both spectra. In the peak detector mode the maxima of both spectra is calculated. The steps are performed a selectable number of times. The detectors that estimate the disturbance of transient signals like that quasi-peak detector are simulated by an algorithm that has been presented in [2]. This algorithm creates a statistical model of the EMISignal. This signal is transformed via Short-time Fast Fourier Transform (STFFT) in the frequency domain. The evaluation of the spectrum in the quasi-peak detector mode is performed by a digital quasi-peak detector. In [3] it has been shown, that a time-domain EMI Measurement System can fulll almost all requirements that are given by current international standards. However the CISPR16-1-1 requires the analogue output of the IF-Signal which cannot be realized with such systems. A continuous analogue IF-Signal can only be provided by a system that works in realtime. The implementation of the FFT on hardware is presented and it is shown that by the algorithm presented in [1] implemented on a Field Programmable Gate Arrays (FPGA) will reduce the measurement time by a factor of 2000. In the following a novel TDEMI measurement system is presented that allows via hardware Implementation of the STFFT to process the signal in realtime. The EMI signal is digitized by a multiresolution ADC. In order to allow continuous processing the clock frequency has to be reduced to the clock frequency of the FFT hardware. The reduction of the data rate is performed by a digital band-pass lter followed by a downsampling block.

LISN

Fig. 1.

Multiresolution Time Domain EMI Measurement System

II. S PECTRAL E STIMATION PERFORMED BY F IELD P ROGRAMMABLE G ATE A RRAYS Digital spectral estimation is achieved via the Discrete Fourier Transform (DFT). Algorithms for DFT computations that exploit symmetry and repetition properties of the DFT are dened as Fast Fourier Transform (FFT). The DFT formulation considers periodic repetition of the time domain signal and is given as follows:
N 1

via a logarithmic periodic biconical antenna. By a multiresolution Analog-to-Digital Converter (ADC) system a oating point analog-to-digital conversion is performed. The data is processed via digital signal processing and the amplitude spectrum is shown. But due to the high data rate of several GS/s and the limited depth of high speed digital memory the record time is limited to several microseconds. At has been shown in several publications that this drawback can be

X[k] =
n=0

x[n]e

j2kn N

(1)

17th International Zurich Symposium on Electromagnetic Compatibility, 2006

501

17th International Zurich Symposium on Electromagnetic Compatibility, 2006

A. Overview For FPGAs Intellectual Property (IP) cores that can perform the FFT within microseconds range [4] are available. The number of samples per transform N is directly related to the sampling rate of the signal and the frequency binwidth by the following: N = fs f (2)

Inserting (4) and (5) into (8) and considering manipulations written in (6) and (7), we obtain the nal equations of the desired output as follows: {R[k]} = 1 1 1 (a + c) (a c) sin(p) + (b d) cos(p) 2 2 2 (9) 1 1 1 (b + d) (a c) cos(p) (b d) sin(p) 2 2 2 (10)

Since the maximum frequency of interest is 1 GHz and according to Nyquist criterion, this entails a sampling rate of at least 2 GS/s. As a consequence, we need for a binwidth of 50 kHz a FFT which processes at least 40000 samples. The currently available FFT IP-core for FPGAs has a maximum clock frequency of 250 MHz and a point size of N = 65536. We consequently obtain an execution time for a single FFT of 262 s. B. Real Valued FFT FFT calculations are performed to complex signals. The EMI Signal that is digitized by the mulitresolution ADC is a real signal and shows a symmetric amplitude spectrum. 50 % of the calculations can be saved when we use a (N/2)-FFT and separate the even and odd samples and provide them respectively as real and imaginary part of a complex signal to the FFT. In the following the mathematical derivition is shown. First, we separate the input signal into its even- and odd-indexed signal streams and feed the even-indexed sequence x1 [n] into the real channel and the odd-indexed sequence x2 [n] into the imaginary channel as follows: q[n] = x1 [n] + jx2 [n] (3)

{R[k]} =

where p = 2k/N . Implementing (9) and (10) as a network after the FFT core will reduce the required calculation by about 50%. By this way the sampling rate of the input signal may be increased by a factor of 2. In Fig. 2 the network of (9) and (10) is shown.

sin(p)

cos(p) -1

-(a-c) a+c

0.5

x1

c FFT-IP Core N/2point a b Flip(a) d Flip(-b)

x2

b+d Im{R(k)} 0.5 cos(p)

b-d -1 sin(p)

-1

The DFT of the input sequences can be written in terms of the output sequence as follows: DF T {q[n]} + DF T {q[n] } X1 [k] = 2 DF T {q[n]} DF T {q[n] } X2 [k] = 2j
Fig. 2. Network Architecture for 50% FFT Resource Reduction

(4) C. Recongurability (5) FPGAs provide the opportunity to load another hardware conguration during their operation. Typically the FFT hardware is optimized for a xed number of points. By loading different hardware congurations different operation modes can be loaded into the FPGA. D. Dynamic Range The dynamic range of a time-domain EMI Measurement system, considering the Analog-to-Digital Conversion has been investigated in [6]. In the following the effects of the quantization of the signal during the digital signal processing is investigated. It is supposed that the number of bits in time-domain is the same as in frequency domain. 1) Time Domain: The quantization noise of a digital signal is given by [5]: SN R = PSignal PN oise (11)

At the output of the FFT-IP core, we obtain the following result:

N 1
j2nk N

Q[k] = DF T {q[n]} =
n=0

q[n]e

(6)

{Q[k]} + j {Q[k]} = a + jb where a and b are the real and imaginary output spectra respectively. The DFT of q[n] is computed as follows: DF T {q[n] } = {
N 1

q[n]e
n=0

j2[N k]n N

} =

(7)

Q[N k] = c + jd.

From the Decimation-In-Time (DIT) algorithm, the DFT is found as follows [5]: R[k] = Re [k] + e
j2k N

while the power of the signal is given by (12):

2 PSignal = s = (x(t) x(t) )2

Ro [k]

(8)
502

(12)

17th International Zurich Symposium on Electromagnetic Compatibility, 2006

The power of the quantization noise is given by (13) (13) 12 with as the quantization step. The relation between the quantization error and the number of bits is given by: ba = log2 ( ) (14)
2 PN oise = e = 2

B. Estimated Measurement Time Table I outlines a comparison of the measurement time between the TDEMI system on FPGAs and EMI Receivers for a scan time of 100 ms in Band C and D. The result is a reduction of the measurement time by a
A/D Conversion Calculation time approx. Measurement time Realtime TDEMI 100 ms 400 ms <1s EMI Receiver 33 min

2) Frequency Domain: In this section the theoretically achievable measurement accuracy and the dynamic range of a FPGA based TDEMI Measurement System is investigated. The relation between the maximum measurement is given by: error Xer,dB and the quantization error = 10(
Xer,dB 20

TABLE I C OMPARISON OF THE MEASUREMENT TIME

(15)

factor about 2000. IV. R EALTIME S PECTRAL E STIMATION An overview of the digital signal processing blocks are presented in Fig. 3.

With (15) and (14) we obtain ba = log2 10(

Xer,dB 20

(16)

For our example we consider that we need an accuracy of 1 dB. Thus we would need 3 bits for quantization. The requirements for achieving a sufcient dynamic range is given by: XSF DR (17) bd = 6dB The total number of bits bt needed by the system is given by: (18) bt = bd + b a Thus an ideal system using 16 Bit resolution in frequency domain, and a required accuracy of 1 dB shows a dynamic range of 78 dB. III. N ON - CONTINUOUS
OPERATION

Fig. 3.

Realtime Digital Signal Processing

A. Digital Down Conversion We reduce the data rate to about 250 MS/s by applying a band-pass lter with a followed down-sampling. In order to reduce the hardware requirements we use a structure of 8 parallel FIR lters which run at a frequency of 250 MS/s. This structure is called polyphase decimator [5]. The polyphase decimator is depicted in Fig. 4. The

In a TDEMI measurement system for the frequency range 30 MHz - 1 GHz the sampling rate of the ADC has to be more than 2 GS/s to fulll the Nyquist criterium. However FFT engines on FPGAs provide only a maximum clocking frequency of 250 MS/s. Thus a continuous processing via a direct connection between the ADC and the FFT engine is currently not possible. But for the statistical detector modes Peak, Average and RMS a non continuous processing can be performed as presented in [1]. The signal is stored temporarily and processed afterwards. With each calculation of the FFT the current spectrum can be updated. A. Detector Modes The peak detector formulation is obtained by: Xp = M AX{X[n]|n {1...N }} The formulation of the average detector is given by: Xavg 1 = N
N 1

Fig. 4.

The Polyphase Decimator

(19)

frequency range 30 MHz - 1 GHz is divided into 10 subsprectra. By the presented Polyphase Decimator one subspectra is processed. The switching between the 10 subspectra is performed by an update of the FIR Filter coefcients. B. Short Time Fast Fourier Transform

X[n]
n=0

(20)

The formulation of the rms detector is given by: Xrms = 1 N

N 1

X 2 [n]
n=0

(21)

We calculate from the signal that has been obtained by the Digital-Down-Conversion a continuous spectrogram. This spectrogram shows a disctretization in frequency and time. The resolution in frequency is described by the binwidth f . The resolution in time is described by a time step TsBB . The inverse of the time-step is called baseband sampling frequency fsbb . The spectrogram is calculated
503

17th International Zurich Symposium on Electromagnetic Compatibility, 2006

by a Short-Time FFT (STFFT). The STFFT calculates as follows:

N 1

100 Matlab Simulation FPGA Based TDEMI System 80

X[t, k] =
n=0

x[n + t]w[n]e

j2kn N

(22)
Magnitude / dB
60 40 20 0 100
Fig. 6.
50 45 40

where w[n] is a gaussian window function that models the IF-lter of an EMI-Receiver [2]. The signal at each discrete frequency is processed by a quasi-peak detector. The digital simulation of a quasi-peak detector requires a sampling rate of about 250 kHz [2]. Thus we have to use also a fsbb of 250 kHz during the STFFT. The overlapping factor is given by: fsbb 250 kHz = =5 (23) f 50 kHz Each FFT can process the data stream of about 250 MS/s in realtime. In order to process the signal with an overlapping factor of 5 we need 5 parallel FFT processors. A proposed block diagram is shown in Fig 5.

150 Frequency / MHz

200

Dynamic Range of Two-tone signal

Magnitude / dBV

35 30 25 20 15 10 5 EMI Receiver FPGA based TDEMI System 200 400 600 Frequency / MHz 800 1000

Fig. 5.

Short Time Fast Fourier Transform

C. Detector Modes and IF-Signal The peak, average and rms detector mode are implemented as shown in III-A. The quasi-peak detector mode is implemented as presented in [2]. The IF-Signal can be provided for one frequency by extracting the complex result X[t, fsel ] where fsel is the selected frequency. The signal may be mixed to a xed IF frequency by a multiplication with e2fIF and provided as analogue IF-output. V. S IMULATIONS AND M EASUREMENT R ESULTS A simulation of a FPGA hardware has been performed with an ideal two-tone sinusoidal input signal. A 16-Bit FFT hardware, the window function and the Peak Detector mode have been implemented. The results obtained by the hardware simulation are compared with the results on the conventional PC based TDEMI Measurement System as shown in Fig. 6. A dynamic range of 61 dB has been achieved when we permit a maximum measurement error of 1 dB. CISPR 16-1-1 requires 40 dB dynamic range and 1 dB accuracy. When we consider that the signal in frequency domain has been 16 dB below the full scale value we see that we would have a maximum dynamic range of 77 dB which is in agreement to the values obtained in section II-D.2. The emission measurement of a laptop is shown in Fig. 7. The measurement has been performed with an EMI Receiver and compared with the results obtained by the FFT on a FPGA in the peak detector mode. The maximum difference is 2 dB.
504

Fig. 7.

Emission of Laptop

VI. C ONCLUSION In has been shown that a hardware implementation of the FFT can reduce the measurement time by a factor of 2000 in comparison to EMI Receivers. Further it has been shown that a xed point implementation of 16 Bit is sufcient. By processing the signal in realtime via bandpass ltering, digital downconversion and Short-time FFT a virtual IF-Signal can be generated. By the sufcient dynamic range of the multiresolution system and realtime processing the current CISPR 16-1-1 can be fullled. R EFERENCES
[1] F. Krug, T. Hermann, and P. Russer, Signal Processing Strategies with the TDEMI Measurement System, 2003 IEEE Instrumation and Measurement Technology Conference Proceeding, May 2022, Vail, USA, pp. 832837, 2003. [2] S. Braun, F. Krug, and P. Russer, A Novel Automatic Digital Quasi-Peak Detector for a Time Domain Measurement System, in 2004 IEEE International Symposium On Electromagnetic Compatibility Digest, August 914, Santa Clara, USA, vol. 3, pp. 919924, Aug. 2004. [3] S. Braun, M. Aidam, and P. Russer, Development of a Multiresolution Time-Domain EMI Measurement System that Fulls CISPR 16-1, in 2005 IEEE International Symposium On Electromagnetic Compatibility, Chicago, USA, 2005. [4] XILINX, Fast Fourier Transform v3.1. Data sheet, November 2004. [5] A. V. Oppenheim and R. W. Schafer, DiscreteTime Signal Processing. ISBN 0-13-214107-8, Prentice-Hall, 1999. [6] S. Braun and P. Russer, The dynamic range of a Time-Domain EMI Measurement System using several parallel Analog to Digital Converters, in 16th International Zurich Symposium on Electromagnetic Compatibility,February 13-18,Zrich, Switzerland, 2005.