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5. SMITH, D. J. HDL Chip Design. Madison, AL: Doone Publications, 1996. 6. PELLERIN, D. AND D. TAYLOR. VHDL Made Easy! Upper Saddle River, NJ: Prentice Hall PTR, 1997. 7. STEFAN, S. AND L. LINDH. VHDL for Designers. London: Prentice Hall Europe, 1997. 8. YALAMANCHILI, S. VHDL Starter's Guide, 2nd ed. Upper Saddle River, NJ: Pearson Prentice Hall, 2005. 9. IEEE Standard Description Language Based on the Verilog Hardware Description Language (IEEE Std 1364-1995). New York: The Institute of Electrical and Electronics Engineers, 1995. 10. PALNITKAR, S. Verilog HDL: A Guide to Digital Design and Synthesis, 2nd ed. Upper Saddle River, NJ: Pearson Prentice Hall, 2003. 11. BHASKER, J. A Verilog HDL Primer, 2nd ed. Allentown, PA: Star Galaxy Press, 1999. 12. THOMAS, D. AND P. MOORBY. The Verilog Hardware Description Language, 5th ed. NewYork: Springer, 2002. 13. CILETTI, M. Advanced Digital Design with Verilog HDL, Upper Saddle River, NJ: Pearson Prentice Hall, 2003. 14. CILETTI, M. Starter's Guide to Verilog 2001. Upper Saddle River, NJ: Pearson Prentice Hall, 2004.

PROBLEMS
The plus (+) indicates a more advanced problem and the asterisk (*) indicates that a solution is available on the Companion Website for the text. '4-1. Design a combinational circuit that forms the 2-bit binary sum SiSQ of two 2-bit numbers A^AQ and #i#0 and has both a carry input C0 and carry output C2. Design the entire circuit implementing each of the three outputs with a two-level circuit plus inverters for the input variables. Begin the design with the following equations for each of the two bits of the adder:

+ ABC
Ci+1= 4-2. *The logic diagram of the first stage of a 4-bit adder, as implemented in integrated circuit type 74283, is shown in Figure 4-28. Verify that the circuit implements a full adder. 4-3. *Obtain the Is and 2s complements of the following unsigned binary numbers: 10011100,10011101,10101000,00000000, and 10000000.

4-4. Perform the indicated subtraction with the following unsigned binary numbers by taking the 2s complement of the subtrahend:

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D FIGURE 4-28 Circuit for Problems 4-2,4-27, and 4-41

(a) 11010 - 10001 (b) 11110 - 1110

(c) 1111110 - 1111110 (d) 101001 - 101

4-5. Repeat Problem 4-4, assuming the numbers are 2s complement signed numbers. Use extension to equalize the length of the operands. Indicate whether overflow occurs during the complement operations for any of the given subtrahends. Indicate whether overflow occurs overall for any of the given subtractions.
^Perform the arithmetic operations (+36) + (-24) and (-35) - (-24) in binary using signed 2s complement representation for negative numbers.

The following binary numbers have a sign in the leftmost position and, if negative, are in 2s complement form. Perform the indicated arithmetic operations and verify the answers.

(a) 100111 + 111001 (b) 001011 + 100110

(c) 110001 - 010010 (d) 101110 - 110111

Indicate whether overflow occurs for each computation.


4-8. +Design two versions of the combinational circuit whose input is a 4-bit number and whose output is the 2s complement of the input number, for each of the following cases using AND, OR, and NOT gates:

(a) The circuit is a simplified two-level circuit, plus inverters as needed for the input variables. (b) The circuit is made up of four identical two-input, two-output cells, one for each bit. The cells are connected in cascade, with lines similar to a carry between them. The value applied to the rightmost carry bit is 1.

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(c) Calculate the gate input costs for the designs in (a) and (b) and determine which is the better design in terms of gate input cost.
Use contraction beginning with a 4-bit adder with carry out to design a 4-bit increment-by-3 circuit with carry out that adds the binary value 0011 to its 4bit input. The function to be implemented is S = A + 0011. 4-10. Use contraction beginning with an 8-bit adder-subtractor without carry out to design an 8-bit circuit without carry out that increments its input by 00000010 for input S = 0 and decrements its input by 00000010 for input S = 1. Perform the design by designing the distinct 1-bit cells needed and indicating the type of cell use in each of the eight bit positions.

4-11. Design a combinational circuit that compares two 4-bit unsigned numbers A and B to see whether B is greater than A. The circuit has one output X, so that X = 1 if A < B and X = 0 if A^B.
/

4-12. +Repeat Problem 4-11 by using three-input, one-output circuits, one for each of the four bits. The four circuits are connected together in cascade by carry-like signals. One of the inputs to each cell is a carry input, and the single output is a carry output.
4-13. Repeat Problem 4-11 by applying contraction to a 4-bit subtracter and using the borrow out as X.

Design a combinational circuit that compares 4-bit unsigned numbers A and B to see whether A = B or A > B. Use an iterative circuit as in Problem 4-12. 4-15. +Design a 5-bit signed-magnitude adder-subtractor. Divide the circuit for design into (1) sign generation and add-subtract control logic, (2) an unsigned number adder-subtractor using 2s complement of the minuend for subtraction, and (3) selective 2s complement result correction logic.
/4-16. *The adder-subtractor circuit of Figure 4-7 has the following values for input select S and data inputs A and B:

B
0111 0111 1010 1010 1000

(a) (b) (c) (d) (e)

1 1
0

0111 0100 1101 0111 0001

Determine, in each case, the values of the outputs 53,52,5l5 50, and C4.

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Combinational Circuit 1: Structural VHDL Description library ieee, lcdf_vhdl ; use ieee.std_logic_1164.all, lcdf_vhdl. f unc_prims. all ; entity comb__ckt_l is port(xl, x2, x3, x4 : in std_logic;
f : out std_logic) ; end cortib_ckt_l ;

architecture structural_l of comb__ckt_l is component NOT1 port(inl: in std_logic;


outl: out std_logic); end component; component AND2 port (inl, in2 : in std_logic; outl: out std_logic) ; end component; component OR3 port(inl, in2, in3 : in std_logic; outl: out std_logic); end component; signal nl, n2, n3, n4, n5, n6 : std_logic; begin gO: NOT1 port map (inl => xl, outl => nl); gi: NOT1 port map (inl => n3, outl => n4); g2: AND2 port map (inl => x2, in2 => nl, outl => n2); g3: AND2 port map (inl => x2, in2 => x3,
outl => n3); g4: AND2 port map (inl => x3, in2 => x4,

outl => n5);


g5: AND2 port map (inl => xl, in2 => n4,

outl => n6);


g6: OR3 port map (inl => n2, in2 => n5,

in3 => n6, outl => f);

end structural_l;

D FIGURE 4-29 VHDL for Problem 4-20

All HDL files for circuits referred to in the remaining problems are available in ASCII form for simulation and editing on the Companion Website for the text. A VHDL or Verilog compiler/simulator is necessary for the problems or portions of problems requesting simulation. Descriptions can still be written, however, for many problems without using compilation or simulation.

Problems

201

D FIGURE 4-30
Circuit for Problems 4-21,4-24,4-36, and 4-38

4-17. Compile and simulate the 2-to-4-line decoder with enable in Figure 4-12 for sequence 000, 001, 010, Oil, 100, 101, 110, 111 on E_n, AO, Al. Verify that the circuit functions as a decoder. You will need to compile library lcdf_vhdl. f unc_prims first, since it is used in the simulation. 4-18. Rewrite the VHDL given in Figure 4-12 for the 2-to-4-line decoder using (1) std_logic_vector notation instead of std_logic notation for A and D_n and (2) implicit specification of the component input and output names by their order in package func_prims in library lcdf_vhdl given in the Companion Website. See Figure 4-13 and accompanying text for these concepts. Compile and simulate the resulting file as in Problem 4-17. 4-19. Compile and simulate the 4-to-l-line multiplexer in Figure 4-13 for the sequence of all 16 combinations of 00,10,01,11 on S and 1000,0100,0010,0001 on D.You will need to compile library lcdf_vhdl. f unc_prims first, since it is used in the simulation. Verify that the circuit functions as a multiplexer.

4-20. *Find a logic diagram that corresponds to the VHDL structural description in Figure 4-29. Note that complemented inputs are not available.

4-21. Using Figure 4-13 as a framework, write a structural VHDL description of the circuit in Figure 4-30. Replace X, Y, and z with X (0 : 2 ) . Consult package func_prims in library lcdf_vhdl for information on the various gate components. Compile func_prims and your VHDL, and simulate your VHDL for all eight possible input combinations to verify your description's correctness.
4-22. Using Figure 4-12 as a framework, write a structural VHDL description of the circuit in Figure 4-31. Consult package func_jprims in library lcdf_vhdl for information on the various gate components. Compile f unc__prims and your VHDL, and simulate your VHDL for all 16 possible input combinations to verify your description's correctness.

4-23. Find a logic diagram representing minimum two-level logic needed to implement the VHDL dataflow description in Figure 4-32. Note that complemented inputs are available.

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D FIGURE 4-31
Circuit for Problems 4-22 and 4-35

4-24. *Write a dataflow VHDL description for the circuit in Figure 4-30 by using the Boolean equation for the output R 4-25. +Write a dataflow VHDL description for the priority encoder in Figure 3-24 using the "when-else" dataflow concept from Figure 4-15. Compile and simulate your description with a set of input vectors that are a good test for the priority function it performs. 4-26. Write a dataflow VHDL description for an 8-to-l-line multiplexer using the "with-select" dataflow concept from Figure 4-16. Compile and simulate your description with a set of input vectors that are a good test for the selection function it performs.
4-27. Using Figure 4-13 as a guide, write a structural VHDL description for the full-adder circuit in Figure 4-28. Compile and simulate your description. Apply all eight input combinations to check the correction function of your description.

Combinational Circuit 2: Dataflow VHDL Description library ieee; use ieee.std_logic_1164.all; entity comb_ckt_2 is port (a, b, c, d, a_n, b_n, c_n, d_n: in std_logic;

f, g : out std_logic); a_n, b_n, ... are complements of a, b, ... , respectively. end comb_ckt_2;
architecture dataflow_l of comb_ckt_2 is begin f <= b and (a or (a_n and c)) or (b_n and c and d_n) ; g <= b and (c or (a_n and c_n) or (c_n and d_n)); end dataflow_l;

D FIGURE 4-32 VHDL for Problem 4-23

Problems

203

4-28. Compile and simulate the 4-bit adder in Figure 4-17 and 4-18. Apply combinations that check out the rightmost full adder for all eight input combinations; this also serves as a check for the other full adders. Also, apply combinations that check the carry chain connections between all full adders by demonstrating that a 0 and a 1 can be propagated from CO to C4. 4-29. * Compile and simulate the behavioral description of the 4-bit adder in Figure 4-19. Assuming a ripple carry implementation, apply combinations that check out the rightmost full adder for all eight input combinations. Also apply combinations that check the carry chain connections between all full adders by demonstrating that a 0 and a 1 can be propagated from CO to C4. 4-30. +Using Figure 4-19 as a guide and a "when-else" on S from Figure 4-15, write a high-level behavior VHDL description for the adder-subtractor in Figure 4-8 (see Figure 4-7 for details). Compile and simulate your description. Assuming a ripple carry implementation, apply combinations that check out one of the full adder-subtractor stages for all 16 possible input combinations. Also, apply combinations to check the carry chain connections in between the full adders by demonstrating that a 0 and a 1 can be propagated from CO to C4. Check the overflow signals as well. 4-31. * Compile and simulate the 2-to-4-line decoder Verilog description in Figure 4-20 for sequence 000, 001, 010, Oil, 100, 101, 110, 111 on E, AO, Al. Verify that the circuit functions as a decoder. 4-32. Rewrite the Verilog description given in Figure 4-20 for the 2-to-4-line decoder using vector notation for inputs, outputs, and wires. See Figure 4-21 and accompanying text for these concepts. Compile and simulate the resulting file as in Problem 4-31.
4-33. Compile and simulate the 4-to-l-line multiplexer in Figure 4-21 for the sequence of all 16 combinations of 00,10, 01,11 on S and 1000, 0100, 0010, 0001 on D. Verify that the circuit functions as a multiplexer.

4-34. *Find a logic diagram that corresponds to the Verilog structural description in Figure 4-33. Note that complemented inputs are not available.

4-35. Using Figure 4-20 as a framework, write a structural Verilog description of the circuit in Figure 4-31. Compile and simulate your Verilog for all 16 possible input combinations to verify your description's correctness. 4-36. Using Figure 4-33 as a framework, write a structural Verilog description of the circuit in Figure 4-30. Replace X, Y, and Z with input [ 2 : 0 ] X. Compile and simulate your Verilog for all eight possible input combinations to verify your description's correctness.

4-37. Find a logic diagram representing minimum 2-level logic needed to implement the Verilog dataflow description in Figure 4-34. Note that complemented inputs are available.

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/ / Combinational Circuit 1: Structural Verilog Description module comb_ckt_l (xl, x2, x3, x 4 , f ) ;
input xl, x2, x3, x4; output f ;

wire nl, n2, n3, n4, n5 f n6;

not go(nl, xl) ,


gl(n4, n3);

and
g2(n2, g3(n3, g4(n5, g5(n6, x2, x2, x3, xl, nl) , x3) , x4),); n4),) ;

or
g 6 ( f , n2, n5, n 6 ) ,

endmodule

D FIGURE 4-33 Verilog for Problems 4-34 and 4-36

4-38. *Write a dataflow Verilog description for the circuit in Figure 4-30 by using the Boolean equation for the output F and using Figure 4-23 as a model.

4-39. By using the conditional dataflow concept from Figure 4-24, write a Verilog dataflow description for an 8-to-l-line multiplexer. Compile and simulate your description with a set of input vectors that are a good test for the selection function it performs.
4-40. +Write a dataflow description for the priority encoder in Figure 3-24 using the binary decision dataflow concept from Figure 4-25. Compile and simulate your description with a set of input vectors that are a good test for the priority function it performs.
// Combinational Circuit 2: Dataflow Verilog Description module comb_ckt_l (a, b, c, d, a_n, b_n, c_n, d_n, f , g) ; / / a__n, b_n, . . . are complements of a, b, . . . , respectively. input a, b, c, d, a_n, b_n, c__n, d_n; output f , g;

assign f = b & (a (a_n & c ) ) | (b_n & c & d_n) ; assign g = b & (c | (a_n & c_n) I (c_n & d_n) ) ; endmodule

D FIGURE 4-34 Verilog for Problem 4-37

Problems

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4-41. Using Figure 4-21 as a guide, write a structural Verilog description for the full-adder circuit in Figure 4-28. Compile and simulate your description. Apply all eight input combinations to check the correction function of your description.
4-42. Compile and simulate the 4-bit adder in Figure 4-26. Apply combinations that check out the rightmost full adder for all eight input combinations; this also serves as a check for the other full adders. Also, apply combinations that check the carry chain connections between all full adders by demonstrating that a 0 and a 1 can be propagated from CO to C4.

4-43. * Compile and simulate the behavioral description of the 4-bit adder in Figure 4-27. Assuming a ripple carry implementation, apply all eight input combinations to check out the rightmost full adder. Also, apply combinations to check the carry chain connections between all full adders by demonstrating that a 0 and a 1 can be propagated from CO to C4.
4-44. Using Figure 4-27 as a guide and a "binary decision" on S from Figure 4-25, write a high-level behavior Verilog description for the adder-subtractor in Figure 4-7. Compile and simulate your description. Assuming a ripple carry implementation, apply input combinations to your design that will (1) cause all 16 possible input combinations to be applied to the full adder-subtractor stage for bit 2, and (2) simultaneously cause the carry output of bit 2 to appear at one of your design's outputs. Also, apply combinations that check the carry chain connections between all full adders by demonstrating that a 0 and a 1 can be propagated from CO to C4.

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