A 10MHz to 100MHz Bandwidth Scalable, Fully Differential Current Feedback Amplifier

Nihit Bajaj, Bert Vermeire and Bertan Bakkaloglu

School of Electrical, Computer and Energy Engineering Arizona State University Tempe, AZ 85287, USA Email: nihit@asu.edu
Abstract A technique for power-bandwidth scaling of a current feedback amplifier (CFA) is presented. By employing current gain, instead of the feedback resistance, to alter the closed-loop bandwidth of the CFA, the proposed approach is shown to provide 30% quiescent power savings for a bandwidth variation of 10MHz to 100MHz. Parasitic extracted simulations are performed in a 0.18m CMOS process with a power supply of 3.3V and a load capacitance of 1.5pF. A closed-loop gain range of 0-20dB, slew rate of 200V/s, settling time of 33ns and total harmonic distortion of 73dB is achieved at a quiescent power consumption range of 3mW to 4.4mW.

resistance to vary the bandwidth, we utilize the current gain to do the same, keeping power scaling in mind. Fig. 1 shows the top-level test bench of a first-order CFA model in the conventional non-inverting gain configuration. The voltage at node Y (Vin for this configuration) is first copied to node X through a buffer, which is modeled as a unity-gain block with a series resistance, rb1. The current through node X also the error current for any CFA feedback configuration is then mirrored with finite current gain, Ai (equal to one in most CFA architectures), to an internal high impedance node, Z. The voltage at Z is buffered, through a unity-gain buffer similar to the one at the input, to the output node, Vo. This output node voltage is finally converted to a current through a resistance, Rf, to complete the feedback loop. Rg, is used to vary the closed-loop gain setting. A first order analysis of the circuit yields the following

I.

INTRODUCTION

Current feedback amplifier (CFA) based circuit architectures have gained increased attention in the recent past owing to superiority over their voltage-mode counterparts in terms of speed, linearity, slew rate and bandwidth [1], [2]. These advantages have also led to CFAs being used in a variety of applications including buffers, filters, oscillators and regulators [3]-[7]. Unlike voltage-feedback opamps, which are inherently limited by a constant gain-bandwidth product, CFAs can be used to independently control gain and bandwidth, albeit at the expense of reduced loop gain and hence, reduced accuracy. Moreover, to achieve gainbandwidth independence, a very low output-impedance is usually desired from the input buffer of a CFA [8] - [10]. This is one of the key reasons - along with better current drive capability - why BJTs are preferred over CMOS transistors in most practical designs [11], [12]. Nevertheless, a number of CMOS alternatives have been published in the recent years. Most of these, however, focus on particular performance parameters, including offset compensation [13], highfrequency [14] and low-voltage operation [15], [16]. In this paper, we focus on the complementary source follower cascade current feedback amplifier published in [17] and propose a more generic, modified architecture to accommodate field-programmable closed-loop gain and bandwidth settings. While most CFA designs use the feedback

Figure 1. System-level model of a CFA in the non-inverting configuration

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expression for the voltage transfer function,

II.

TRANSISTOR-LEVEL DESIGN

Rf 1 + Rg Vo = Vi Rf rb1 1 + Rg 1 + sCZ Ai

(1)

+ Rf

Ignoring the effect of rb1, the closed loop dc voltage gain, AV, and closed loop 3-dB bandwidth, fCL, can be written as

AV = 1 +
f CL =

Rf Rg

(2) (3)

Ai 2R f C Z

The transistor-level schematic of the proposed CFA, shown in Fig. 2, is based on the classic complementary source follower cascade architecture presented in [17], as mentioned earlier. In the circuit, while transistors M1-M4 form the input unity-gain buffer, transistors M13-M16 form the buffer at the output. M7-M8 and M9-M10 help mirror the fed-back current from node X to node Z. M8 and M10 are split into four programmable devices to allow for selection from four bandwidth settings 10MHz, 33MHz, 66MHz and 100MHz. Gain-boosting is also employed to increase the impedance at node Z and hence, to increase the loop gain and settling accuracy. A P-input differential amplifier is designed, as shown in Fig. 3, for the NMOS current mirror since the drain terminals of M9 and M10 sit close to ground. A similar reasoning explains the use of an N-input amplifier (Fig. 4) for the PMOS current mirror. In contrast, low impedance is ensured at node X to help reduce bandwidth variations with closed-loop gain, given by (1), and at node Vo to lower the output impedance of the overall current feedback amplifier. The scaling of transistors M8 and M10 is achieved through switches S3, S2, S1 and S0. A small aspect ratio for M8 and M10 would yield a lower Ai and according to (3), a lower closed-loop bandwidth along with the obvious advantage of lower current flowing through the M8-M11-M12-M10 branch. A point to note here is that transistors M11 and M12, being cascode devices, need not be scaled in the same proportion as their rail-counterparts for bandwidth variation and so, their aspect ratios are kept constant for this design. Another key merit of this architecture is the ability to improve the amplifier bandwidth - at the expense of some extra power - for higher closed loop gain settings by adding extra branches to

It can be seen from (3) that if Ai is used to alter fCL (with Rf and CZ fixed), quiescent power can be saved. Adopting this technique, we show in this paper that scaling the bandwidth from 10MHz to 100MHz leads to 30% savings in power. Keeping Rf constant also means that AV can now be varied using Rg only. Section II describes the transistor-level schematic of the circuit while Section III presents simulation results with the CFA driving a pipeline ADC. Using the CFA for this particular application meant that a fully-differential version of the circuit was required and this resulted in the doubling of area and power requirements. Conclusions are provided in Section IV.

Figure 3. Local N-input gain-boosting amplifier

Figure 2. Transistor-level schematic of the proposed CFA

Figure 4. Local P-input gain-boosting amplifier

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TABLE I.

TRANSISTOR ASPECT RATIOS OF CFA Transistor W/L(m/m) 120/0.54 108/0.54 360/0.54 36/0.54 240/0.54 40/0.54 240/0.54 72/0.54 12/0.54 72/0.54 160/0.72 48/0.72 Figure 6. Power- Bandwidth scaling in the proposed CFA

M1, M5, M13, M17 M2, M6, M14, M18 M3, M15 M4, M16 M7, M19 M8 M9, M20 M10 M11 M12

transistors M8 and M10, a point that will become clear in the next section. III. RESULTS

differential circuit. And as is evident from Fig. 6, which is the bandwidth-power plot for the same set of points as in Fig. 5, 30% of this power is saved when the amplifiers bandwidth requirements are reduced to 10MHz. The small signal AC magnitude response of the CFA for four different values of gain 0dB, 6dB, 12dB and 20dB (achieved by having the resistor, Rg, as a ladder network) can be seen in Fig. 7. Although the bandwidth for a closed loop gain of 20dB is about half of its corresponding 0dB value, it is still five times higher than what could be achieved with a conventional voltage feedback structure. This reduction in bandwidth for the CFA is due largely to the non-zero output impedance of the input buffer stage as can be derived from (1). As hinted earlier, at higher closed loop gain settings, the bandwidth can be improved at the cost of some extra power instead of adopting the conventional technique of further lowering the output resistance of the input buffer. The solution is to add more branches to transistors M8 and M10 and increase Ai to values greater than 1. An example of this scheme is presented in Fig. 8 where the closed-loop bandwidth, for a closed-loop gain setting of 20dB, improves from 48MHz to 100MHz by simply increasing Ai from 1 to 2. The extra power burnt in the process is 1.55mW, only 35% of the total power. Fig. 9 shows the amplifiers response to a 1V differential step input. The slew-rate is noted to be greater than 200V/s and the 0.05% settling time, 33ns. With the CFA in the unity gain configuration and Rf = 2k, pss simulations reveal a total

The current feedback amplifier was used as a buffer for a pipeline ADC with an input capacitance of 1.5pF. Simulations were performed after parasitic extraction in the JAZZ 0.18m CMOS process with a power supply of 3.3V. To achieve a 4V peak-to-peak differential swing, 1.8V-devices were used everywhere in the circuit except for switch implementation. Transistor dimensions are summarized in Table I. The feedback resistor was fixed at 2k and the capacitance, CZ, at 1.5pF. Fig. 5 serves as proof of the proposed concept by plotting closed-loop bandwidth (fCL) vs. current gain (Ai). The plot has four data points corresponding to the four branches of transistors M8 and M10 in Fig. 2. The figure appears to be deviate slightly from the linear dependence between these two parameters expressed in (3). The reasoning lies in the addition of extra poles due to the unity-gain buffers and the current mirrors at the transistor level. The closed-loop system is no longer first-order, which is seen by adding a high-frequency current mirror pole to the system-level model presented in Fig. 1 [18]. The quiescent power required to obtain the maximum desired bandwidth of 100MHz is 4.4mW for the fully-

Figure 5. Bandwidth vs. Current gain plot for the CFA

Figure 7. Closed-loop bandwidth of the CFA for four closed loop gain settings 0dB, 6dB, 12dB and 20dB

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TABLE II.

KEY PERFORMANCE PARAMETERS OF CFA Parameter Technology (m) Power Supply (V) Value 0.18 3.3 10-100 3.0-4.4 1.5 200 33 0-20 73 68

Closed-loop Bandwidth (MHz) (in four steps) Power Dissipation (mW) Load Capacitance (pF) Slew Rate (V/s) Figure 8. CFA Bandwidth improvement by adding extra current branches (AV = 20dB) Settling time (ns) Closed-loop Gain (dB) (in ten steps of 2dB each) THD @ 1MHz 2Vpp in unity gain with Rf = 2k (dB) IMD @ 1MHz 1Vpp, 2MHz 1Vpp in unity gain with Rf = 2k (dB) [4]

[5]

[6] Figure 9. Step response of CFA to 1V differential step [7]

harmonic distortion (THD) of 73dB for a 1MHz, 2V peak-topeak input signal and an inter-modulation distortion (IMD) of 68dB between 1V peak-to-peak signals of 500kHz and 1MHz. Table II summarizes the key performance parameters of the proposed current feedback amplifier. IV. CONCLUSION

[8] [9]

A current feedback amplifier employing current gain to alter the closed-loop bandwidth has been proposed. The technique is shown to save 30% of power when the bandwidth is scaled from 10MHz to 100MHz. Through simulations performed in the 0.18m process, the circuit is also shown to provide programmable gain setting from 0-20dB, a slew rate of 200V/s, a settling time of 33ns and a total harmonic distortion of 73dB. REFERENCES
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