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Digital baseband controller

DB3370 and DB3430



Data sheet

1424-LZN 901 2501/1 Uen Rev G 2010-11-02

LZN 901 2501/1 R2B

Copyright ST-Ericsson 2009, 2010. All rights reserved. COMPANY CONFIDENTIAL





Digital baseband controller Data sheet Abstract
DB3370 and DB3430



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Copyright ST-Ericsson 2009, 2010. All rights reserved. COMPANY CONFIDENTIAL

Abstract
This data sheet defines the electrical and physical specifications for the DB3370, and
DB3430 digital baseband controllers in SCP, as well as the PoP versions. It also defines
the available variants, describes the component marking, and shows the mechanical
drawings.
The primary target audiences for this document are electronic hardware engineers and
designers working with the design and development of ME, based on ST-Ericsson
platforms.
In order to optimize the design and supply of this device, ST-Ericsson reserves the right to
make changes at any time.
IMPORTANT!
This data sheet is valid for DB3370 and DB3430; the specification is the same for both. In
this document, some figures, tables, and text only refer to DB3370, but are to be
considered valid for DB3430.

Digital baseband controller Data sheet Legal information
DB3370 and DB3430



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Legal information
Copyright ST-Ericsson 2009, 2010. All rights reserved.
Disclaimer
The contents of this document are subject to change without prior notice. ST-Ericsson
makes no representation or warranty of any nature whatsoever (neither expressed nor
implied) with respect to the matters addressed in this document, including but not limited
to warranties of merchantability or fitness for a particular purpose, interpretability or
interoperability or, against infringement of third party intellectual property rights, and in no
event shall ST-Ericsson be liable to any party for any direct, indirect, incidental and or
consequential damages and or loss whatsoever (including but not limited to monetary
losses or loss of data), that might arise from the use of this document or the information in
it.
ST-Ericsson and the ST-Ericsson logo are trademarks of the ST-Ericsson group of
companies or used under a license from STMicroelectronics NV or Telefonaktiebolaget
LM Ericsson.
All other names are the property of their respective owners.
Trademark list
All trademarks and registered trademarks are the property of their respective owners.
AMBA

AMBA is a trademark of ARM Limited.


ARM

ARM is a registered trademark of ARM Limited.


ARM926EJ-S

ARM926EJ-S is a trademark of ARM Limited.


Bluetooth

The Bluetooth word mark and logos are owned by the


Bluetooth SIG, Inc. and any use of such marks by ST-
Ericsson is under license.
CEVA

CEVA is a trademark of CEVA, Inc.


CEVA-X1622

CEVA-X1622 is a trademark of CEVA, Inc.


ECOPACK2

ECOPACK2 is a registered trademark of


STMicrolelectronics.
Embedded

Trace

Macrocell

Embedded Trace Macrocell is a trademark of ARM


Limited.
ETM9

ETM9 is a trademark of ARM Limited.


IC

IC is a trademark of NXP B.V.


IS

IS is a trademark of NXP B.V.


IrDA

IrDA is a registered trademark of Infrared Data


Association.
Memory

Stick

PRO

Memory Stick PRO is a trademark of Sony.



Digital baseband controller Data sheet Legal information
DB3370 and DB3430



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Copyright ST-Ericsson 2009, 2010. All rights reserved. COMPANY CONFIDENTIAL

MMC

MMC is a trademark of the MultiMediaCard Association.


Philips

Philips is a registered trademark of NXP B.V.


SD

SD is a trademark of Toshiba Corporation.


ST

The ST logo is a registered trademark of


STMicroelectronics

Digital baseband controller Data sheet Contents
DB3370 and DB3430



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Copyright ST-Ericsson 2009, 2010. All rights reserved. COMPANY CONFIDENTIAL

Contents
1 About this document 11
1.1 Purpose 11
1.2 Audience 11
1.3 Revision information 12
1.4 Reference list 13
2 Introduction 14
2.1 General description 14
3 Hardware architecture 15
3.1 Block diagram 16
3.1.1 Access subsystem 16
3.1.2 Application subsystem 17
4 Functional requirements 18
4.1 Access CPU subsystem 18
4.1.1 ARM926 subsystem 18
4.1.2 AHB matrix 18
4.1.3 DMA 19
4.1.4 Boot ROM 19
4.1.5 AAIF 19
4.2 Access peripherals subsystem 19
4.2.1 INTCON 19
4.2.2 SIMIF 20
4.2.3 SYSCON 20
4.2.4 GPIO 20
4.2.5 Timer 20
4.2.6 Watchdog 21
4.2.7 UART 21
4.2.8 SPI 21
4.2.9 IrDA 21

Digital baseband controller Data sheet Contents
DB3370 and DB3430



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4.2.10 USB 22
4.2.11 I
2
S/PCM 23
4.2.12 GPRS crypto 23
4.2.13 WCDMA cipher and integrity 23
4.2.14 I
2
C interface 23
4.2.15 ETX 23
4.2.16 EDC 23
4.2.17 Bus Trace 23
4.2.18 EventHist 24
4.2.19 CableDetect 24
4.2.20 MMC/SD/SDIO host controller 24
4.3 DSP subsystem 24
4.3.1 External memories 24
4.3.2 Peripherals 24
4.4 EGG subsystem 25
4.5 WCDMA subsystem 25
4.6 Application CPU subsystem 25
4.6.1 ARM926 subsystem 26
4.6.2 DMA 27
4.6.3 AAIF 27
4.6.4 NAND flash IF 27
4.6.5 SEMIF 27
4.6.6 Application EMIF 27
4.6.7 Boot ROM 28
4.7 XGAM subsystem 28
4.8 Camera data synchronizer 28
4.9 Camera image signal processor 28
4.10 Video encoder 28
4.11 Application peripherals subsystem 29
4.11.1 RTC 29
4.11.2 I
2
C interface 29
4.11.3 I
2
S/PCM interface 29
4.11.4 SPI 29
4.11.5 GPIO 29
4.11.6 Timer 30
4.11.7 Watchdog 30

Digital baseband controller Data sheet Contents
DB3370 and DB3430



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4.11.8 SYSCON 30
4.11.9 Keypad 30
4.11.10 INTCON 31
4.11.11 UART 31
4.11.12 MMC/SD/SDIO host controller 31
4.11.13 Memory Stick PRO 31
4.11.14 Bus Trace 31
4.11.15 EventHist 31
4.11.16 Dynamic memory use counters 31
4.12 APEX 31
4.13 Analog cells 32
4.13.1 PLL 26 to 208 MHz 32
4.13.2 PLL 26 to 48/60 MHz 32
4.13.3 PLL 32 kHz to 13 MHz 32
4.13.4 PLL 13 MHz to 208 MHz 32
4.13.5 Random noise generator 32
4.13.6 DAC 32
4.13.7 ADC 32
4.13.8 General purpose ADC 32
4.13.9 Fuses 33
4.14 Chip level control 34
4.14.1 CHIPCON 34
4.14.2 Pad MUX 34
4.15 Test IP structure 34
4.15.1 TAP controllers 34
4.15.2 MemBIST controller 34
4.15.3 MemBIST 34
4.15.4 Fuse controller 34
4.15.5 Scan combiners (gates) 34
4.15.6 Test vector compression/decompression (gates) 35
5 Interfaces 36
5.1 DB3370 R1A 36
5.2 Unused IOs 36

Digital baseband controller Data sheet Contents
DB3370 and DB3430



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Copyright ST-Ericsson 2009, 2010. All rights reserved. COMPANY CONFIDENTIAL

6 Revisions and variants 37
6.1 DB3370 and DB3430 revisions and variants 37
7 Packaging the SCP 38
7.1 Package outline assembly 38
7.2 Package mechanical drawing: SCP 39
8 Packaging the 12 12 PoP 40
8.1 Package outline assembly 40
8.2 Package mechanical drawing: PoP 12 12 42
8.2.1 Top view 42
8.2.2 Bottom view 43
9 Packaging the 14 14 PoP 44
9.1 Package outline assembly 2L substrate 44
9.2 Package mechanical drawing: PoP 14 14 46
9.2.1 Top view 46
9.2.2 Bottom view 47
10 Component identification 48
10.1 Component markings: SCP 48
10.2 Component markings: PoP 49
11 Electrical characteristics 50
11.1 Absolute maximum ratings 50
11.2 Normal operating conditions 51
11.2.1 Characteristics 51
11.3 IO characteristics 52
11.3.1 Input clock MCLK 52
11.3.2 Input clock RTCCLKIN 52
11.3.3 Output clock SYSCLK [2:0] 53
11.3.4 Bidirectional buffer 2 mA 1.8 V 53
11.3.5 Bidirectional buffer 4 mA 1.8 V 55
11.3.6 Bidirectional buffer 8 mA 1.8 V 56

Digital baseband controller Data sheet Contents
DB3370 and DB3430



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Copyright ST-Ericsson 2009, 2010. All rights reserved. COMPANY CONFIDENTIAL

11.3.7 Bidirectional buffer 1.8 V 58
11.3.8 subLVDS buffer 1.8 V 61
11.4 I
2
C Input/Output cell 63
11.4.1 I
2
C bidirectional buffer 1.8/2.75 V 63
11.5 PLL 64
11.5.1 PLL_26x 64
11.5.2 PLL_416x_A 65
11.5.3 PLL_240x 66
11.6 Analog pads 68
11.7 Converters 68
11.7.1 WCDMA I and Q Sigma-Delta ADC 68
11.7.2 WCDMA I/Q 10 bit D/A converters and smoothing filters 70
11.7.3 General purpose ADC 73
11.7.4 Band gap reference voltage generator and central bias current generator 77
11.8 Random noise generator 78
11.9 IO cell requirements 79
11.10 Operation modes 79
11.10.1 Clock frequencies 79
11.11 Power-on sequence 80
12 Test modes 81
12.1 Chip modes 81
12.2 Production test mode 82
12.3 JTAG emulation mode 82
13 Definitions 83
13.1 Jitter 83
13.1.1 Sigma 83
13.2 Duty cycle 83
13.3 Timing 83
13.3.1 Rise and fall time 83
13.3.2 Other timing 83

Digital baseband controller Data sheet Contents
DB3370 and DB3430



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Glossary 84


Digital baseband controller Data sheet About this document
DB3370 and DB3430



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Copyright ST-Ericsson 2009, 2010. All rights reserved. COMPANY CONFIDENTIAL

1 About this document
1.1 Purpose
This data sheet defines the electrical and physical specifications for the DB3370 and
DB3430 digital baseband controllers in Single Chip Package (SCP), as well as the
Package on Package (PoP) versions.
The data sheet also defines the available variants, describes the component marking, and
shows the mechanical drawings.
IMPORTANT!
This data sheet describes both DB3370 and DB3430, the specification is the same for
both. In this document, some figures, tables, and text only refer to DB3370, but are to be
considered valid for DB3430.
1.2 Audience
The primary target audiences for this document are electronic hardware engineers and
designers working with the design and development of Mobile Equipment (ME), based on
ST-Ericsson platforms.
It is assumed that the reader has a reasonable understanding of the concepts associated
with mobile communications, combined with an appreciation of hardware design
techniques.

Digital baseband controller Data sheet About this document
DB3370 and DB3430



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1.3 Revision information
The revision history of this document is listed below.
Table 1 Revision history
Date Rev. Comments
2009-05-28 A Original version
2009-07-09 B Leakage values and corresponding footnotes corrected in
Table 7
Adjusted unused IO leakage recommendations in Unused IOs
section.
Input capacitance of IOs changed to 3,5 pF and placed in last
row of Characteristics table in Normal operating conditions
section. (Same value for all buffers and including package
cap.) (Values was 4-5 pF excluded package cap)
I
IL
and

I
IH
of BDSCARyQP buffer changed from 2 to 1 A in
Bidirectional buffer 8 mA 1.8 V characteristics table.
Updated Boot ROM section.
2009-11-24 C Added watermark information.
Updated package information.
2010-01-14 D Updated for DB 3430.
2010-04-13 E Removed Ericsson prefix to digital baseband controller
names.
Ericsson Mobile Platform replaced by ST-Ericsson
platforms.
Digital baseband controller names converted to DBxxxx from
DB xxxx
New chapter added: Chapter 6 Revisions and variants
2010-10-08 F Removed PRELIMINARY watermark.
Minor layout changes.
2010-11-02 G Updated Revision and variants chapter.

Digital baseband controller Data sheet About this document
DB3370 and DB3430



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1.4 Reference list
[1] USB 2.0 Specification http://www.usb.org
[2] Philips I2C specification version 2.1 http://www.nxp.com
[3] MMC Version 4.0 Specification http://www.mmca.org
[4] CE-ATA version 1.0 Specification http://www.ce-ata.org
[5] SD Specification 1.01 http:///www.sdcard.org
[6] Digital baseband controller, DB3370 and DB3430, Pinout
description*


* See the Delivery Note (1212-APX xxx xxx), supplied with the platform release, for current document
number and revision.

Digital baseband controller Data sheet Introduction
DB3370 and DB3430



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2 Introduction
2.1 General description
The DB3370 is a highly-integrated digital baseband controller that includes Global System
for Mobile Communication (GSM), General Packet Radio Services (GPRS), Enhanced
Data Rate for GSM Evolution (EDGE), and Wideband Code Division Multiple Access
(WCDMA).
The DB3370 also includes High-speed Downlink Packet Access (HSDPA) class 8
functionality and High-speed Uplink Packet Access (HSUPA) class 4 functionality.
The DB3370 includes support for the following:
NAND flash with on-die ECC, support of ECC with 4 KiByte page size. The DB3350
supports 4 KiByte in Strict mode.
Improved USB timing margins.
SPI Slave mode.
In this document, the term digital baseband controller is used to refer to the DB3370 and
DB3430, unless otherwise stated.

Digital baseband controller Data sheet Hardware architecture
DB3370 and DB3430



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3 Hardware architecture
The hardware architecture consists of the following two distinct subsystems:
Access subsystem
- Access CPU subsystem ARM926EJ-S

, Joint Test Action Group (JTAG),


Embedded Trace Module (ETM), Instruction and Data (I&D)-cache, and I&D-
Tightly Coupled Memory (TCM)
- Access peripheral subsystems SIM interface, IrDA

, USB, Universal
Asynchronous Receiver/Transmitter (UART), and so on
- Digital Signal Processor (DSP) subsystem CEVA-X1622

, JTAG, Static
Random Access Memory (SRAM), and Program Data Read Only
Memory (PDROM)
- EDGE/GSM/GPRS (EGG) subsystem EGG hardware accelerators
- WCDMA subsystem WCDMA hardware accelerators
Application subsystem
- Application CPU subsystem containing ARM926EJ-S, JTAG, ETM, I&D-cache,
and I&D-TCM
- Application peripheral subsystems I
2
C

, keypad, UART, and so on


- Graphics subsystem XGAM subsystem
- Audio Processing Execution (APEX) and video encoder subsystems
In addition to the two subsystems above, there is also a test block, chip control block, and
a pad multiplexing block residing at the top level.

Digital baseband controller Data sheet Hardware architecture
DB3370 and DB3430



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3.1 Block diagram
3.1.1 Access subsystem
WCDMAsubsystem
EGGAccessHW DataComHW AAInterfaceHW BasicHW
AHB1(Data)
AHBMaster
AHB-Lite
AHB-Lite AHB2(DMA1)
AHB4(DSP)
AHB-Lite
DSPsubsystem
AHBMaster
PDROM
464kB
SSRAM
332kB
AHBSlave
JTAG
SYSCON
GPIO
SIMIF
AHBMatrix52MHz
8
16
3
8
I
2
C0
54
SPI
UART2
RS232
IRDA
3
4
16
8
16
BTUART
I
2
S/PCM
(BT)
4
4 16
UART0
4 16
AAIF
AHB
Master
EDC
ETX
32
32
AHB
IF
ARB
APBBridge
(Slow)
ARB
Access-
ApplicationIF
ToEMIF
arbiter
GPRS
CRYPTO
32
16
26
MHz
DMA
58Channels
54Requests
WatchDog
16 6
AHB2APB
(Fast)
8 2
26
MHz
AHB
IF
AHBIF
AHB
Master
16 Cable
Detect
EventHist
16
BusTracer
16
MSL
AHB-Lite
ARB
AHB
IF
AHB3(DMA2)
CEVA-
X1622
AHBM
GPIO ICU PMU
CRU Timer0 Timer1
XpertCEVA
64kB
IRAM
128kB
DRAM
104MHz
208MHz
PLL
26->208MHz
USBPLL
26->48/60MHz
Randomnoise
generator
EGGsubsystem
EGGHWaccelerators
3
4
RF-CTRL
26MHz
1
ANTSW
RX/TX
26MHz
TXADC
APBBridge AHBIF
1
GPSSTART
3
26/52MHz
Timer
8
Accessslowperipheralssubsystem Accessfastperipheralssubsystem
LEGEND
WCDMAHWaccelerators
52/104MHz
3
10
3
10
AHBS
ARB ARB ARB
ADCI&Q
12x3.84MHz
DACI/Q
12x3.84MHz
1Vpp
2Vpp
1Vpp
2Vpp
AHB
IF
WCDMAAccessHW
WCDMA
CIPHER0
32
AHB
IF
AHB
IF
AHBSlave AHBSlave AHBSlave AHBSlave AHBSlave
AccessARM926subsystem
D
Cache
32kB
I
Cache
32kB
AHB
Master
MMU
IMem
Control
DMem
Control
ARM9EJ-S
TLB
DTCM
8kB
ITCM
26kB
ETMIF
ETM9
JTAGDEBUG TCMIF
EICE
AHB
Master
13
JTAG
AHBBUSIF
AHB0(Inst)
INTCON
2 32
BootROM
32
52
MHz
AHBperipheralssubsystem
DMA
AHBr
A
R
B
DMAC
GeneralPurpose
ADC
2.35
Vpp 10
USB
12 32
AHB2AHB
3
3
ADCI&Q
12x3.84MHz
1Vpp
1Vpp
WCDMA
INTEGRITY
32
WCDMA
CIPHER1
32
PPM 32
5
RF-CTRLGP
4
RFANTSW
?
RF-CTRLSTRB
MMC0
6 32
1
PA_ENABLE
MMC1
6 32

Figure 1 Access subsystem architecture

Digital baseband controller Data sheet Hardware architecture
DB3370 and DB3430



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3.1.2 Application subsystem
EMIF AHB
Slave
SDRAMIF
ISP
ApplicationCPUsubsystem
APPBUS
APPDMAC
CDS
SEMIF
APEX+
ARM926SM
ARM926EJ-S
D
Cache
32kB
I
Cache
32kB
AHB4(Inst)
AHB5(Data)
JTAG
SDRAMIF
APEX
MMU
IMem
Control
DMem
Control
ARM9_CORE
TLB
ETMIF
ETM9
SDRAM/NOR
DataComHW
MMHW
AAInterfaceHW
BasicHW
JTAGDEBUG TCMIF
EICE
AAIF
AHB
Slave
Acc-Applink
AHB0(DMA0)
AHB2(XGAM)
AHB
Slave
AHB
Master
AHB
Slave
AHB
Slave
ETM
Intel
MSL
AHB
Slave
PSRAM/NOR/NAND
APEX
RAM
APEX
ROM
AHB1(DMA1)
55
55
55
FromAccesssystem
VideoEncoder
AHB3(VEnc)
VideoEncoder
ARB ARB
EMIFArbiter
SDRAM/NOR
A
H
B

p
e
r
i
p
h
e
r
a
l
s
INTCON
32 2
MSPRO
8 32
BootROM
5k*32bit
32
AHB2AHB
ARB
5
2
M
H
z
AAIF
RAM
AAIF
RAM
VENC
RAM0
VENC
RAM1
NOR/
PSRAM/
NANDIF
ARB
AHB
Slave
ARB
AHB
Slave
ARB
AHB
Slave
AHB
Master
AHB
Slave
ARB
DMACORE
40Channels
and31Requests
AHBBUSIF
AHB
Master
AHB
Slave
AHB
Master
52MHz
APBSLOW
KEYPAD
GPIO
1
3
M
H
z
32
TIMER0
16
32
11
16 56
WDOG
32
SYSCON
16
UART0
AHB
Slave
4
RTC
16
BUSTR
32
EventH
32
AHB2APB
(Slow)
TIMER1
32
APBFAST
I2C0
32
2
6
M
H
z
MMC/SD
9 32
AHB2APB
(Fast)
I2S/PCM0
16
AHB
Slave
4
2
I2C1
32 2
I2S/PCM1
16 4
SPI
16 6
ARB
XGAM
CDI
PDI
P
A
R
/S
S
I
AHB
Slave
GAMCON
PDI
AHB
Master
MCiDCT
(Video)
PDICON
CDICON
D
A
T
A
C
P
U
GAMEACC
(3D)
GRAM
64kbyte
ISP
CDI
CDS
AHB
Slave
ARB
32
EMIF
32
ISP
AHB
Periferals
AHB
Slave
AHB
Periferals
PPM
32
ARB
VENC
OCRAM
VENC
TRAM
VENC
DRAM
UART1
16 4
DTCM
8kB
ITCM
8kB

Figure 2 Application subsystem architecture

Digital baseband controller Data sheet Functional requirements
DB3370 and DB3430



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4 Functional requirements
4.1 Access CPU subsystem
The digital baseband controller includes an Access CPU subsystem, which includes the
submodules described in Subsections 4.1.1-4.1.5.
4.1.1 ARM926 subsystem
The ARM926EJ-S includes the following components:
32 KiB I-cache
32 KiB D-cache
Page table
Memory Management Unit (MMU)
JTAG
ETM9


26 KiB I-TCM
8 KiB D-TCM
4.1.1.1 ARM926EJ-S
The CPU is an ARM926EJ-S core with a cache configuration of 32 KiB instruction and
32 KiB data.
The CPU can be clocked at 26, 104, and 208 MHz. The ARM926EJ-S includes an MMU
with at least 32 entries.
4.1.1.2 TCM
The DB3370 includes a 26 KiB instruction TCM, and an 8 KiB data TCM. The data TCM is
accessible by the Direct Memory Access (DMA). The instruction TCM is accessed at
208 MHz and the data TCM is accessed at 208 MHz.
4.1.1.3 ETM9
The ARM9 subsystem includes an Embedded Trace Macrocell

9 medium+.
4.1.2 AHB matrix
The ARM High-speed Bus (AHB) architecture in the access part is clocked at either
13 MHz or 52 MHz.

Digital baseband controller Data sheet Functional requirements
DB3370 and DB3430



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The AHB architecture includes five AHBs. The bus architecture implements AHB-Lite,
which allows only one AHB master on each AHB. All other devices that share an AHB
with a master are slaves. The AHB is programmable to operate at 13 MHz or 52 MHz.
The five AHBs are defined as follows:
AHB0 CPUI_AHB (CPU instruction bus is the only master)
AHB1 CPUD_AHB (CPU data bus is the only master)
AHB2 DSP_AHB (DSP is the only master)
AHB3 DMA_AHB (DMA is the only master)
AHB4 DMA_AHB (DMA is the only master)
4.1.3 DMA
The DMA controller is Random Access Memory (RAM)-based and supports 54 DMA
requestors and 58 DMA channels, where each channel supports unidirectional transfer.
Both single and burst DMA requests are supported. The burst sizes are programmable for
1, 2, 4, 8, 12, or 16 words and the DMA controllers support 8, 16, and 32-bit wide
transactions. The DMA controller is configured through its AHB slave interface. Accesses
are 8, 16, or 32-bit on this interface.
4.1.4 Boot ROM
The Boot Read-only Memory (ROM) is 48 KiB. The boot code supports booting from the
NAND flash or the USB.
In DB3370, NAND FLASH with on-die Error Code Correction (ECC) is supported. ECC of
4 KiByte page size is also supported.
4.1.5 AAIF
The Application to Access Interface (AAIF) block provides a high-speed flexible interface
between the access and the Application parts of the digital baseband controller. It
operates at up to 52 MHz, supports seven transmit and seven receive channels, and
handles burst sizes between 1 and 64 bytes.
4.2 Access peripherals subsystem
4.2.1 INTCON
The Interrupt Controller (INTCON) provides up to 64 prioritized interrupts. Each of the 64
interrupts is routed to either of the two interrupts of the ARM core that is the Fast Interrupt
Request (FIQ) or the low priority Interrupt Request (IRQ). The interrupt inputs are active
low sensitive. All 64 prioritized interrupts are maskable.

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4.2.2 SIMIF
The Subscriber Identity Module Interface (SIMIF) connects to the SIM, through an
external voltage level shifter module. The SIMIF block consists of three hardware
lines (simrst, simclk, and simio). The data line (simio) is bi-directional and is used to
transfer data to and from the SIM. The output clock (simclk) defines the data transfer
rates and can be disabled when necessary. The data rate can be altered without having
to reset the SIM card. The clock rate is selectable to either 26/8 MHz or 26/24 MHz. The
data rate is the clock rate divided by a programmable value between 372 and 32. The
clock to the SIM card can be switched off under software control.
The SIMIF includes a 24-byte First In, First Out (FIFO) for buffering received data from
the SIM card. This data can be received with the Most Significant Bit (MSB) first or last, as
well as inverted or non-inverted.
The data is transferred from the CPU to the SIMIF in 1 byte (8-bit) bursts. There is no
FIFO buffering of transmit data within the SIMIF. Therefore, the block indicates to the
CPU when it can send the next byte.
4.2.3 SYSCON
The System Controller (SYSCON) is responsible for clock generation and clock and reset
distribution within the digital baseband controller, as well as to external devices.
The digital baseband controller chip-ID number is readable from the SYSCON.
The block is a slave peripheral under control of the ARM

processor. The programming of


the SYSCON controls the fundamental modes of operation within the digital baseband
controller. Individual blocks can also be reset and their clocks held inactive by accessing
the appropriate control registers.
A register in the SYSCON includes support for a dedicated interrupt from the ARM
processor to the DSP for GSM radio signal processing-related functions (manipulated by
the appropriate ARM software module). This enables the communication channel to be
used for communication of speech coder data.
4.2.4 GPIO
The General Purpose Input/Output (GPIO) block operates as a general input and output
port to the digital baseband controller external pins.
Each GPIO pin can be independently set as either input or output. The output type is
push-pull or a pseudo form of open-drain or open-source output drive, selectable under
software control. All ports are set as input after reset.
The GPIO block is able to generate interrupts, when configured as input, on either falling
or rising edge.
4.2.5 Timer
The timer supports two OS timers using the 32.768 kHz clock and two general purpose
timers running at not less than 1 MHz.

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4.2.6 Watchdog
The watchdog timer resets the CPU, if the CPU does not feed it before it times out. The
timer has a default time-out period of 0.5 s.
4.2.7 UART
The DB3370 provides three UARTs in the access part to provide asynchronous interfaces
to external devices. The size of receive and transmit FIFO is 16 bytes.
Table 2 UART description
UART # Use Alternative use Comment
UART0 Accessory control bus Debug There must be at least one debug
connection.
UART2 RS232 The RS232 bus uses the UART2 to
communicate with external devices on
the system connector.
BT UART Bluetooth

Application Engine
Video Bus
Can be used for the bridge interface, if
the Bluetooth solution is handled in the
Application chip.
4.2.8 SPI
The Serial Peripheral Interface (SPI) has support for Master mode and word lengths from
4 to 32 bits. It supports programmable bit rate, polarity, phase, and up to three slaves in
Master mode.
4.2.9 IrDA
Infrared Data Association (IrDA) supports Slow Infrared (SIR), Medium Infrared (MIR),
and Fast Infrared (FIR) when running on the 48 MHz clock.
The IrDA block is able to perform SIR detect at 9600 baud. It operates at 26 MHz when
waiting for SIR (or SIP) pulses, which allows idle low power.
The block handles speeds up to 115,200 baud in UART mode, when clocked at 26 MHz.

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4.2.10 USB
The digital baseband controller USB function blocks both have a full speed transceiver
interface and a ULPI 1.1 Single Data Rate (SDR) interface used for high speed USB
transceivers. The interface selection is controlled by the SYSCON and the pinout
selection in the pad MUX.
The transceiver is external to the platform. The type of external transceiver used
determines the USB hardware capability of the product. The transceiver interface
supports the following external transceiver types:
High speed PHY with SDR USB Low Pin Interface (ULPI). The ULPI mode consists of
12 signals (eight (SDR) data, clock, next, stop, and direction). Both full speed
USB operation and high speed USB operation is possible. USB/UART multiplexing is
possible by selecting the appropriate external ULPI transceiver with the built-in
multiplexer.
Full speed PHY using a standard 4-pin differential interface with DP/DM/OE and RCV
and sideband signaling for USBVbus detect, PullUpEnable, and suspend. This mode
only supports USB full speed device operation. USB/UART multiplexing is possible by
selecting the appropriate external full speed transceiver with the built-in multiplexer.
Full speed PHY using a standard 3-pin single-ended interface with DAT/SE0/OE or
full speed PHY using a standard 4-pin differential interface with DP/DM/OE and RCV,
both with sideband signaling using I
2
C.
The transceiver interface works with standard transceivers from multiple major
manufacturers. The transceiver interface allows the type of external transceiver to be
signaled or detected so that the USB boot code and main software can set up the
transceiver interface accordingly.
The USB function block uses a 60 MHz clock for the Full Speed modes. The internal
60 MHz clock mode takes the clock signal from the internal 48/60 MHz Analog
Phase-locked Loop (APLL). The 60 MHz APLL clock is used for the USB function block
and the full speed PHY interface.
For High Speed modes, an external 60 MHz clock is required. This is generated by the
ULPI transceiver, based on an external Crystal (XTAL) or SYSCLK from the platform.
The USB function block supports a Low-power Suspend mode with automatic wake-up on
resume signaling.
It is possible to initiate remote wake-ups from the USB function block when operating as a
device.
The USB function block has seven in and ten out endpoints with sufficient endpoint FIFO
sizes and DMA capability to fulfill the currently defined use cases for the USB, as well as
some future USB use cases.
The USB function block supports operation as either a USB device or a USB host using
either high speed or full speed signaling rates. All transfer types (control, interrupt, bulk,
and isochronous) are supported. The USB host operation is according to the USB On-the-
Go (OTG) supplement to the USB 2.0 specification, see Reference [1]. When operating
as a USB host, the USB function block supports multiple devices.
Note: Special USB transceivers are needed for USB host and OTG
operation. There is currently no software support for operation as
a USB host or OTG.

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4.2.11 I
2
S/PCM
The Integrated Interchip Sound (I
2
S

) supports both master and Slave Transmitter and


Receiver modes. Both transmit and the receive paths contain two logical channels each.
Each logical channel supports 16-bit data words. It supports two audio transmit and two
audio receive channels.
4.2.12 GPRS crypto
The GPRS crypto block is a dedicated hardware accelerator for GPRS encryption,
decryption, and Cyclic Redundancy Check (CRC).
4.2.13 WCDMA cipher and integrity
The WCDMA cipher and integrity block is a dedicated hardware accelerator for WCDMA
ciphering and integrity functionality.
4.2.14 I
2
C interface
The digital baseband controller includes one I
2
C Interface (I
2
CIF) block in the access part
to provide communication with a power management device. The interface is compliant
with Reference [2]. The interface operates in Multi-master Transmitter, Slave Transmitter,
Multi-master Receiver, and Slave Receiver mode. The interface supports both the
Standard mode and the Fast mode.
4.2.15 ETX
The Enable Transmission (ETX) block provides a level of security by protecting
proprietary data within the digital baseband controller, such as the contents of the flash
memory. It also ensures that the operation of the system is enabled only after the
validation of certain parameters.
The ETX contains two electrically programmable values, one 64-bit and one 128-bit,
residing in on-chip fuse farms, and programmed during wafer fabrication and set-up, with
random offsets of the digital baseband controller die-ID fuse values. This allows each
digital baseband controller to have unique ETX fuse values.
4.2.16 EDC
The digital baseband controller includes the ST-Ericsson Discretix Crypto Cell (EDC),
which provides encryption/decryption functionality. The EDC block can retrieve a random
number from the analog cell Random Noise Generator (RNG).
4.2.17 Bus Trace
The Bus Trace block is a set of counters that counts the number of accesses on the
different AHBs during two seconds. The CPU can read the collected numbers and the
counters can be reset.

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4.2.18 EventHist
The EventHist block is a FIFO in which a CPU can post an 8-bit code that is tagged by a
time stamp. The CPU can read out the contents of the FIFO and get both the code and
the time stamp. The time stamp field is 32 bits and it is updated with a time resolution of
approximately 100 s. The event history is available for the ARM926.
4.2.19 CableDetect
The CableDetect block is able to detect whenever a cable is connected to the external
interface of the UART and then it requests the system clock and sends an interrupt to the
CPU.
4.2.20 MMC/SD/SDIO host controller
The digital baseband controller includes two MMC

/SD

/SDIO interfaces.
4.3 DSP subsystem
The Digital Signal Processor Subsystem (DSPSUB) includes a DSP megacell, which
contains the DSP CPU together with a TCM. The DSP is the CEVA-X1622 core with a
64 KiB instruction RAM and a 128 KiB data RAM. It also contains debug logic and
interfaces. In addition to the megacell, the DSPSUB includes external memories,
peripheral units, and interfaces. The DSP megacell is clocked at 208 MHz.
The DSPSUB includes an AHB master and an AHB slave interface. The AHB master
provides a direct access to the Internal Random Access Memory (IRAM) in the EGG core
through the AHB. The AHB slave interface allows the CPU and the DMA to access in the
program and data RAM residing in the DSPSUB.
4.3.1 External memories
The external memories consist of a 464 KiB ROM and a 332 KiB RAM. The external
memory operates at 104 MHz.
4.3.2 Peripherals
The DSP has the following internal peripherals:
DSP GPIO
Timers
Code Replacement Unit (CRU)
Interrupt Controller Unit (ICU)
Power Management Unit (PMU)

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4.3.2.1 DSP GPIO
The digital baseband controller DSUB includes an 8-bit DSP GPIO. Its signals are routed
and multiplexed to the digital baseband controller GPIO.
4.3.2.2 Timers
There are two timers attached as DSP peripherals.
4.3.2.3 CRU
The CRU enables easy patching when executing software from the ROM.
4.3.2.4 ICU
The ICU handles interrupts from internal and external peripherals, and from the ARM
CPU.
4.3.2.5 PMU
The PMU performs clock control and power management.
4.4 EGG subsystem
The EGG subsystem incorporates a GSM modem and an interface to the GSM radio
together with memory control and an internal single port RAM. The GSM core has two
AHB slave interfaces, the GSM peripherals are accessible through the IO bridge and the
IRAM is accessible through the other AHB.
The EGG subsystem is handled and provided by ST-Ericsson.
4.5 WCDMA subsystem
The digital baseband controller WCDMA subsystem incorporates a WCDMA modem and
an interface to the WCDMA together with memory control and an internal single port
RAM. The WCDMA subsystem has three AHB slave interfaces.
The DB3370 also includes HSDPA class 8 functionality and HSUPA class 4 functionality.
The WCDMA subsystem is handled and provided by ST-Ericsson.
4.6 Application CPU subsystem
The digital baseband controller includes an Application CPU subsystem, which includes
the submodules described in Subsections 4.6.1-4.6.7.

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4.6.1 ARM926 subsystem
The ARM926EJ-S includes the following components:
32 KiB I-cache
32 KiB D-cache
Page table
MMU
JTAG
ETM9
8 KiB I-TCM
8 KiB D-TCM
4.6.1.1 ARM926EJ-S
The CPU is an ARM926EJ-S core with a cache configuration of 32 KiB instruction and
32 KiB data.
The CPU has the capability to be clocked at 13, 52, 104, and 208 MHz. The ARM926EJ-S
includes an MMU with 32 entries.
4.6.1.2 TCM
The digital baseband controller includes an 8 KiB instruction TCM and an 8 KiB data
TCM. The data TCM is accessible by the DMA.
4.6.1.3 ETM9
The ARM9 subsystem includes an ETM9 medium+.
4.6.1.4 AHB
The AHB architecture in the application part is clocked at 6.5, 26, or 52 MHz.
The AHB architecture includes six AHBs. The bus architecture implements Advanced
Microprocessor Bus Architecture (AMBA

)-Lite, which allows only one AHB master on


each AHB. All other devices that share an AHB with a master are slaves. The AHB is
programmable to operate at 6.5, 26, or 52 MHz.
The six AHBs are defined as follows:
AHB0 DMA0_AHB (DMA is the only master)
AHB1 DMA1_AHB (DMA is the only master)
AHB2 XGAM_AHB (XGAM is the only master)
AHB3 Venc_AHB (Video encoder is the only master)
AHB4 CPUI_AHB (CPU instruction bus is the only master)
AHB5 CPUD_AHB (CPU data bus is the only master)

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4.6.2 DMA
The DMA controller is RAM-based and supports 40 DMA requestors and 40 DMA
channels, where each channel supports unidirectional transfer. Both single and burst
DMA requests are supported and the burst sizes are programmable for 1, 4, 8, or 16
words. The DMA controller is configured through its AHB slave interface. All accesses are
8, 16, or 32-bit on this interface.
4.6.3 AAIF
The AAIF block provides a high-speed flexible interface between the access and the
application parts of the digital baseband controller. It operates up to 52 MHz, supports
seven transmits and seven receive channels, and handles burst sizes between 1 and 64
bytes.
4.6.4 NAND flash IF
The NAND flash interface is the port from the Application subsystem to an external NAND
flash device. The NAND flash holds the software code during power off and, if required, it
can hold some applications.
A complete page access support is handled using page sizes of 512 bytes or 2 KiB.
The block contains support for automatic error encoding and decoding using Hamming
ECC, which can be turned on and off.
4.6.5 SEMIF
The CPU, Direct Memory Access Controller (DMAC), Graphics Hardware
Subsystem (XGAM), and Video Encoder access the Shared External Memory
Interface (SEMIF) through the AHBs.
The SEMIF supports dynamic memory sizes up to a total of 1 GiB (two banks of 512 MiB).
There is only limited support for static memories when the application External Memory
Interface (EMIF) is not active. The EMIF is shared between the Access and the
Application subsystem and has functions for handling this arbitration. To ensure
synchronous access from the AHB to the RAM, the SEMIF can run on both the clock used
in the Access subsystem, and the clock used in the Application system. The clock of the
system accessing the RAM is multiplexed and used in the SEMIF.
The SEMIF support for burst read and write is configurable for 1, 2, 4, and 8 words
towards external memories. The SEMIF has a 16-bit data interface for read and write, and
supports access rates up to 104 MHz.
4.6.6 Application EMIF
The CPU, DMAC, or XGAM accesses the EMIF through the AHBs. It supports both static
and dynamic memories.
The EMIF supports asynchronous read and writes to the Synchronous Dynamic Random
Access Memory (SDRAM) and burst read and write is configurable for 1, 2, 4, and 8
words towards the SDRAM.

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The EMIF has a 16-bit data interface for read and write, and supports access rates up to
104 MHz.
The application EMIF is a general interface for communication with an external SDRAM,
NOR flash, NAND flash, companion chips, and so on. The application EMIF can be set in
several different modes to support different types of memory combinations. The EMIF
modes are as follows:
SDRAM (1-2 units), NAND flash (8-16 bits)
SDRAM (1-2 units), NOR
SDRAM (1-2 units), NAND flash (8-16 bits) (plus NOR flash, if the camera interface is
used)
Extended SEMIF. Complete NOR flash support brought out from the SEMIF block.
A NOR flash can be an SRAM, companion chip, or similar.
4.6.7 Boot ROM
The Boot ROM is 20 KiB.
4.7 XGAM subsystem
The XGAM subsystem is a graphics acceleration module that provides hardware support
in the creation of visual imagery and the transfer of this data to a display. The XGAM also
provides support for connecting a Camera module. The visual data can be graphics, still
images, or video.
The XGAM subsystem is handled and provided by ST-Ericsson.
4.8 Camera data synchronizer
The Camera Data Synchronizer (CDS) subsystem provides an interface to the camera
modules outside the DB3370 with both parallel CCIR-656 types and serial SMIA/CCP2
type sensors. The CDS passes the data on to either the XGAM subsystem or the Camera
Integrated Signal Processing (CAMISP) block.
4.9 Camera image signal processor
The CAMISP is a third-party Intellectual Property (IP) handled by ST-Ericsson.
4.10 Video encoder
The video encoder provides hardware acceleration for video encoding, capable of H.264
video encoding.
The video encoder is a third-party IP and handled by ST-Ericsson.

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4.11 Application peripherals subsystem
4.11.1 RTC
The Real Time Clock (RTC) block in the digital baseband controller is only a shadow
register of the RTC register in the power management device, keeping track of time and
date.
Alarms can also be programmed to generate interrupts to the CPU upon reaching a
programmable count.
4.11.2 I
2
C interface
The digital baseband controller includes two I
2
CIF blocks in the application part to allow
for easier product development. One of the I
2
C buses can connect the digital baseband
controller to a power management device and the other to any other suitable device, for
example, a camera. Both I
2
CIFs are identical (except for the addressing).
The interfaces are compliant with Reference [2]. The interfaces operate in Multi-master
Transmitter, Slave Transmitter, Multi-master Receiver, and Slave Receiver mode. The
interfaces support both Standard mode and Fast mode.
4.11.3 I
2
S/PCM interface
The digital baseband controller includes two I
2
S interface blocks to provide a standardized
communication interface for audio between the digital baseband controller and an
external audio device.
The I
2
S blocks support both master and Slave Transmitter and Receiver modes. Both the
transmit and the receive path contain two logical channels each. Each logical channel
supports 16-bit data words. The blocks support two audio transmit and two audio receive
channels. The I
2
S blocks support DMA access and ST-Ericsson simple PCM Master and
Receiver mode.
The DB3370 supports SPI slave mode by using the PCM/I2S #1 interface.
4.11.4 SPI
The SPI block has support for Master mode and word lengths from 4 to 32 bits. It
supports programmable bit rate, polarity, phase, and up to three slaves in Master mode.
The DB3370 supports SPI slave mode by using the PCM/I2S #1 interface.
4.11.5 GPIO
The GPIO block operates as a general input and output port to the digital baseband
controller external pins.

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Each GPIO pin can be independently set as either input or output. The output type is
push-pull or a pseudo form of open-drain or open-source output drive, selectable under
software control. All ports are set as input after reset.
The GPIO block is able to generate interrupts, when configured as input, on either falling
or rising edge.
4.11.6 Timer
The timer supports two OS timers using the 32.768 kHz clock and two general-purpose
timers running at not less than 1 MHz.
4.11.7 Watchdog
The watchdog timer resets the CPU, if the CPU does not feed it before it times out. The
timer has a default time-out period of 0.5 seconds.
4.11.8 SYSCON
The SYSCON resides at the top level of the circuit architecture and is responsible for
clock generation and clock and reset distribution within the digital baseband controller, as
well as to external devices.
The block is a slave peripheral under control of the ARM processor. The programming of
the SYSCON controls the fundamental modes of operation within the digital baseband
controller. Individual blocks can also be reset and their clocks held inactive by accessing
the appropriate control registers.
4.11.9 Keypad
The keypad interface block supports up to 30 keys with 65 columns and 6 rows and
operates in both Scan and Idle mode.
The keypad scan is performed by software. Any transition in the state of the column
inputs is written directly to the register. The keypad interface differentiates between single
key presses, simultaneous presses of any keys with a function key, and any key releases.
The period between successive scans is programmable over the range 5 ms to 80 ms, in
5 ms steps.
During Scan mode, the keypad generates an interrupt whenever a valid keypad state
change occurs (including a release of any pressed keys). The scan function is disabled
during system power-up.
The keypad can detect at least four simultaneous key presses. Not all combinations are
supported.

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4.11.10 INTCON
The INTCON block provides up to 64 prioritized interrupts. Each of the 64 interrupts is
routed to either of the two interrupts of the ARM core that is FIQ or IRQ. The interrupt
inputs are active low sensitive. All 64 prioritized interrupts are maskable.
4.11.11 UART
The digital baseband controller provides two UARTs in the application part to provide an
asynchronous interface to an external device. The size of receive and transmit FIFO is
16 bytes.
4.11.12 MMC/SD/SDIO host controller
The digital baseband controller includes the MMC/SD host controller. The width of the
data interface is configurable to 1, 4, or 8 bits. MMC version 4.0 (see Reference [3]), CE-
ATA ver. 1.0 (see Reference [4]) and SD version 1.0.1 (see Reference [5]) are supported.
4.11.13 Memory Stick PRO
The Memory Stick PRO

block supports a 4-bit data bus with a maximum clock frequency


of 34.6 MHz.
4.11.14 Bus Trace
The Bus Trace block is a set of counters that counts the number of accesses on the
different AHBs during two seconds. The CPU can read the collected numbers and the
counters can be reset.
4.11.15 EventHist
The EventHist block is a FIFO in which a CPU can post an 8-bit code tagged by a time
stamp. The CPU can read out the contents of the FIFO and get both the code and the
time stamp. The time stamp field is 32 bits and updated with a time resolution of
approximately 1 ms.
4.11.16 Dynamic memory use counters
The Dynamic Memory Use Counters (DMUCs) keep track of current, minimum, and
maximum memory use, based on the delta values that are the result of allocating and
freeing memory.
4.12 APEX
The APEX block creates Music Industry Digital Interface (MIDI) tones from wave tables
using sinc. interpolation and performs re-sampling.

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4.13 Analog cells
4.13.1 PLL 26 to 208 MHz
This Phase-locked Loop (PLL) provides the Access subsystem with the system clock in
active mode of operation.
4.13.2 PLL 26 to 48/60 MHz
This PLL provides the clock to the USB (60 MHz) and to the IrDA (Fast IrDA 48 MHz).
4.13.3 PLL 32 kHz to 13 MHz
The PLL provides the Application subsystem with a system clock in Idle and Active mode
operation.
4.13.4 PLL 13 MHz to 208 MHz
This PLL provides the Application subsystem with a system clock in Active mode
operation.
4.13.5 Random noise generator
The random noise generator block generates random numbers for the EDC block.
4.13.6 DAC
The DAC block is a WCDMA Digital to Analog Converter (DAC). The I and Q channels
have 10-bit inputs at 52 MHz and the differential output 2 V
pp
.
4.13.7 ADC
The ADC block is a WCDMA sigma delta Analog to Digital Converter (ADC). The I and Q
channels have the input differential 1 V
pp
and 3-bit outputs at 46.08 MHz. Two identical
ADCs are used to support RxDiversity.
4.13.8 General purpose ADC
The General Purpose ADC block is a general purpose ADC for measurement of TX
power. The input full range is 2.35 V and 10 bits.

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4.13.9 Fuses
The digital baseband controller contains several E-fuses for various functions. Some are
related to security, some for disabling functionality in product devices, and some for
memory repair and for customer use.
The E-fuses in the DB3370 are divided in the following groups, depending on their
function:
Security
Memory redundancy
Quality
Configuration
4.13.9.1 Security E-fuses
The security group of E-fuses is used for setting a seed to the security blocks inside the
digital baseband.
The security E-fuses must be programmed at wafer level, as they are not accessible at
package level.
4.13.9.2 Memory redundancy E-fuses
The memory redundancy E-fuses must be programmed at wafer level, as they are not
accessible at package level.
4.13.9.3 Quality E-fuses
Quality bits are used for traceability. They contain the following information:
Lots
Wafer number
Die ID
Wafer site
The quality E-fuses are programmed at wafer level. Readout signal is bounded at
package level.
4.13.9.4 Configuration E-fuses
The configuration group of E-fuses is used for customer One Time Programmable (OTP),
disable debug functionality or reconfigure functionality in the digital baseband.
As they are fused at ME production, they need to be covered by ECC. The solution for
this is to have a software ECC covering everything that is not directly used by the
hardware.
The configuration E-fuses are programmable at wafer level, package level, and in ME
production.
Write operations are not possible when the lock bit has been fused. The hardware checks
theses bits after hardware reset using a Finite State Machine (FSM). If any of the four lock
bits is set, it becomes impossible to change the programming of any fuses.

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4.14 Chip level control
4.14.1 CHIPCON
The CHIPCON block handles the clock generation and is controlled from the Application
SYSCON, the Access SYSCON, or the transferred account procedure controller.
4.14.2 Pad MUX
The digital baseband controller includes a pad MUX block, which is used to control
multiplexing of all signals used for test, such as: scan, analog Parallel Multiplexed
Test (PMT), and Built-in Self Test (BIST). The multiplexers are controlled by signals from
the CHIPCON, Application SYSCON, Access SYSCON, and TAP_REGS.
For details of the pad MUX, see Reference [6].
4.15 Test IP structure
4.15.1 TAP controllers
The TAP controllers provide control through the standard JTAG interface. Each of the
CPUs, that is, the two ARM cores and the DSP, has a TAP controller which controls
debugger functions. The TAP controller at chip level controls the pin MUX and CHIPCON.
4.15.2 MemBIST controller
The Memory BIST (MemBIST) controller block controls all MemBISTs and combination of
MemBIST results.
4.15.3 MemBIST
For efficient production memory test, each memory has a MUX collar and a test circuit for
pattern generation and comparison. The test circuit can be shared among memories with
the same word depth.
4.15.4 Fuse controller
The fuse controller block burns fuses and reads out the fuse values at startup.
4.15.5 Scan combiners (gates)
The scan combiner block combines scan chains if sharing input/output pins. This block is
inserted at the net list/gate level.

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4.15.6 Test vector compression/decompression (gates)
To reduce the test time and so as not to exceed the tester capacity, test vector
compression is applied.

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5 Interfaces
5.1 DB3370 R1A
See Reference [6].
5.2 Unused IOs
All digital pins on the IC are implemented with bidirectional pads. Even if a pin is assigned
to an output signal, the pad actually includes an input driver, and vice versa for a pin
assigned to an input signal. This means that care must be taken to configure all unused
pins in order to minimize the pad leakage.
The following guideline is used to minimize total leakage in unused digital pins:
The lowest leakage is achieved with a tristated output driver, and either internal or
external pull-up (100 k).
Enabling the output driver and driving a 1 slightly increases the leakage, but has the
signal integrity benefit of acting as a noise barrier between neighboring pins.
The output driver of an unused pin must not be tristated without a pull resistor, since
this may cause significant short circuit currents in the input driver stage of the pad.

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6 Revisions and variants
This chapter defines all revisions and variants of the DB3370, and DB3430 digital
baseband controllers.
The digital baseband controllers are available in several revisions and variants. Functional
differences are separated by revisions.
The devices are available in three package types, SCP, PoP 12x12 and PoP 14x14. Each
package type is treated as a specific variant. For detailed information of the packages,
please refer to Chapters 7, 8, and 9.
6.1 DB3370 and DB3430 revisions and variants
Table 3 DB3370 R1A/x and DB3430 R1A/x, list of variants
Package type Package marking
DB3370
Package marking
DB3430
SCP DB3370 R1A/2 DB3430 R1A/2
PoP 12x12 DB3370 R1A/3 DB3430 R1A/3
PoP 14x14 DB3370 R1A/4 Not available

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7 Packaging the SCP
This chapter describes the SCP assembly. The digital baseband controller is supplied in a
Very thin profile Fine pitch Ball Grid Array (VFBGA) package. 10 10 mm. 392 balls with
0.4 mm pitch.
7.1 Package outline assembly
Title: VFBGA 10 10 1.0 392 5R24 24 PITCH 0.4 BALL 0.25
Table 4 VFBGA SCP mechanical data
Package mechanical data [mm] [mm]
Ref. Min. Typ. Max.
A
1
- - 1.0
A1 0.125 0.165 0.205
A2 0.15 0.19 0.23
A4 0.57 0.585 0.60
b
2
0.22 0.26 0.30
D 9.95 10.00 10.05
D1 - 9.20 -
E 9.95 10.00 10.05
E1 - 9.20 -
e
3
- 0.40 -
Z - 0.40 -
ddd - - 0.08
eee
4
- - 0.09
fff
5
- - 0.04

1
Very thin profile: 0.80 mm < A 1.00 mm/Fine pitch: e < 1.00 mm pitch.
The total profile height (Dim A) is measured from seating plane to the top of the component.
The maximum total package height is calculated by the following methodology:
A1 Typ + A2 Typ. + A4 Typ. + (A1 + A2 + A4 tolerance values).
2
The typical ball diameter before mounting is 0.25 mm.
3
VFBGA with 0.40 mm ball pitch is not yet registered in JEDEC publications.
4
The tolerance of position that controls the location of the pattern of balls with respect to datums A and B.
For each ball, there is a cylindrical tolerance zone eee perpendicular to datum C and located on true position with respect to
datums A and B as defined by e. The axis perpendicular to datum C of each ball must lie within this tolerance zone.
5
The tolerance of position that controls the location of the balls within the matrix with respect to each other.
For each ball, there is a cylindrical tolerance zone fff perpendicular to datum C and located on true position as defined by e.
The axis perpendicular to datum C of each ball must lie within this tolerance zone. Each tolerance zone fff in the array is
contained entirely in the respective zone eee above. The axis of each ball must lie simultaneously in both tolerance zones.

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7.2 Package mechanical drawing: SCP
Figure 3 illustrates the SCP mechanical package
6
.

Figure 3 SCP mechanical package

6
The terminal A1 corner must be identified on the top surface by using a corner chamfer, ink or metalized markings, or other
feature of package body or integral heat slug. A distinguishing feature is allowable on the bottom surface of the package to
identify the terminal A1 corner. The exact shape of each corner is optional.

Digital baseband controller Data sheet Packaging the 12 12
PoP
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8 Packaging the 12 12 PoP
This chapter describes the 12 12 PoP assembly. The digital baseband controller is
supplied in a VFBGA PoP: 12 12 mm. 396 balls with 0.5 mm pitch. 128 top lands with
0.65 mm pitch.
The package conforms to lead-free (ROHS Directive 2002/95/EC) and halogen-free
(ECOPACK2

) requirements.
8.1 Package outline assembly
Title: VFBGA 12 12 1.0 344 + 52 5R23 23 PITCH 0.5 BALL 0.30
JEDEC/EIAJ reference number: JEDEC standard no.95, section 4.22.
Table 5 VFBGA (PoP) package mechanical data
Package mechanical data [mm]
Ref. Min. Typ. Max.
A
7
- - 0.85
A1 0.16 0.21 0.26
A2 - 0.57 -
A3 0.26 0.30 0.34
A5 0.24 0.27 0.30
b
8
0.25 0.30 0.35
C - 1.00 -
c - 0.30 -
D 11.90 12.00 12.10
D1 - 11.00 -
D2 - 11.05 -
E 11.90 12.00 12.10
E1 - 11.00 -

7
Very thin profile: 0.80 mm < A 1.00 mm/Fine pitch: e < 1.00 mm pitch.
- The total profile height (Dim A) is measured from seating plane to the top of the component.
- The maximum total package height is calculated by the following methodology:
A1 Typ + A3 Typ. + A5 Typ. + (A1 + A3 + A5 tolerance values)
8
The typical ball diameter before mounting is 0.30 mm.

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Package mechanical data [mm]
E2 - 11.05 -
e - 0.50 -
F 8.819 8.869 8.919
f - 0.65 -
G 8.819 8.869 8.919
h - 1.50 -
K - 30 -
Z - 0.50 -
Z1 - 0.475 -
ddd - - 0.10
eee
9
- - 0.15
fff
10
- - 0.05
kkk
11
- - 0.15
mmm
12
- - 0.08

9
This is the tolerance of position that controls the location of the pattern of balls with respect to datums A and B.
For each ball, there is a cylindrical tolerance zone eee perpendicular to datum C and located on true position with respect to
datums A and B as defined by e. The axis perpendicular to datum C of each ball must lie within this tolerance zone.
10
This is the tolerance of position that controls the location of the balls within the matrix with respect to each other.
For each ball, there is a cylindrical tolerance zone fff perpendicular to datum C and located on true position as defined by e.
The axis perpendicular to datum C of each ball must lie within this tolerance zone. Each tolerance zone fff in the array is
contained entirely in the respective zone eee above. The axis of each ball must lie simultaneously in both tolerance zones.
11
This is the tolerance of position that controls the location of the pattern of lands with respect to datums A and B.
For each land there is a cylindrical tolerance zone kkk perpendicular to datum C and located on true position with respect to
datums A and B as defined by f. The axis perpendicular to datum C of each land must lie within this tolerance zone.
12
This is the tolerance of position that controls the location of the lands within the matrix with respect to each other.
For each land, there is a cylindrical tolerance zone mmm perpendicular to datum C and located on true position as defined by
kkk. The axis perpendicular to datum C of each ball must lie within this tolerance zone. Each tolerance zone mmm in the array
is contained entirely in the respective zone kkk above. The axis of each ball must lie simultaneously in both tolerance zones.

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PoP
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8.2 Package mechanical drawing: PoP 12 12
8.2.1 Top view
Figure 4 illustrates the top view of the 12 12 PoP mechanical package.

Figure 4 12 12 PoP mechanical package top view

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8.2.2 Bottom view
Figure 5 illustrates the bottom view of the 12 12 PoP mechanical package
13
.

Figure 5 12 12 PoP mechanical package bottom viewf

13
The terminal A1 corner must be identified on the top surface by using a corner chamfer, ink or metalized markings, or other
feature of package body or integral heat slug. A distinguishing feature is allowable on the bottom surface of the package to
identify the terminal A1 corner. The exact shape of each corner is optional.

Digital baseband controller Data sheet Packaging the 14 14
PoP
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9 Packaging the 14 14 PoP
This chapter describes the 14 14 PoP assembly. The digital baseband controller is
supplied in a VFBGA PoP: 14 14 1.0 mm and in a Very Very Thin profile Fine pitch Ball
Grid Array (WFBGA) PoP: 14 14 0.8. The packages have 412 balls with 0.5 mm pitch
and 152 top lands with 0.65 mm pitch.
The package conforms to lead-free (ROHS Directive 2002/95/EC) and halogen-free
(ECOPACK2) requirements.
9.1 Package outline assembly 2L substrate
Title: WFBGA 14 14 0.8 412 6R25 25 PITCH 0.5 BALL 0.30
JEDEC/EIAJ reference number: JEDEC standard no. 95, section 4.22
Package code: 9L
Table 6 WFBGA (PoP) package mechanical data
Package mechanical data [mm]
Ref. Min. Typ. Max.
A5F
14
- - 0.77
A1 0.16 - 0.28
A3 - - 0.24
A5 - - 0.30
b6F
15
0.25 0.30 0.35
C - - 1.10
c - 0.30 -
D 13.90 14.00 14.10
D1 - 12.00 -
D2 - 13.00 -
E 13.90 14.00 14.10
E1 - 12.00 -

14
Very Very Thin profile: 0.65 mm < A 0.80 mm / Fine pitch: e < 1.00 mm
The total profile height (Dim A) is measured from seating plane to the top of the component.
The maximum total package height is calculated by the following methodology:
A max = A1 Typ + A3 Typ. + A5 Typ. + (A1 + A3 + A5 tolerance values)
15
The typical ball diameter before mounting is 0.30 mm.

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Package mechanical data [mm]
Ref. Min. Typ. Max.
E2 - 13.00 -
e - 0.50 -
F - - 10.90
f - 0.65 -
G - - 10.90
K - 30 -
Z - 1.00 -
Z1 - 0.50 -
ddd - - 0.10

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9.2 Package mechanical drawing: PoP 14 14
9.2.1 Top view
Figure 6 illustrates the top view of the 14 14 PoP mechanical package.

Figure 6 14 14 PoP mechanical package top view

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PoP
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9.2.2 Bottom view
Figure 7 illustrates the bottom view of the 14 14 PoP mechanical package16.

Figure 7 14 14 PoP mechanical package bottom view

16
The terminal A1 corner must be identified on the top surface by using a corner chamfer, ink or metalized markings, or other
feature of package body or integral heat slug. A distinguishing feature is allowable on the bottom surface of the package to
identify the terminal A1 corner. The exact shape of each corner is optional.

Digital baseband controller Data sheet Component identification
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10 Component identification
This chapter describes the different examples of the component identification marking.
The examples in Section 10.1 and Section 10.2 illustrate the markings for DB3370, and
DB3430.
10.1 Component markings: SCP
Figure 8 illustrates the typical package markings for the digital baseband controller in
SCP.

e2
/// DB3370, or DB3430
R1A/XX
F
G
H
I
J
K
L
M
Green package
ST-Ericsson device number
ST-Ericsson revision number
Assembly plant
BE sequence
Diffusion traceability plant
Country of origin
Test and finishing plant
Assembly year
Assembly week
Pin1-ref
Figure 8 Component markings: SCP
ST-Ericsson device number DB3370, or DB3430
Each digital baseband controller unit is marked as follows:
The ST-Ericsson external family product number
The number/batch ID and assembly sequence [manufacturers information]
The date of manufacture, that is, year and week in a digit code according to ISO 8601
(yyyyww) or batch code [manufacturers information]
The ST-Ericsson revision code and internal ID suffix.
A terminal identification index on the case (pin 1, where applicable).
Note: The markings are resistant to mechanical wear and common
fluids that the digital baseband controller may be exposed to
during normal handling, storage, and operation.
///DB3370
R1A/XX
F G H
I J K L
M
e2

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10.2 Component markings: PoP
Figure 9 illustrates the typical package markings for the digital baseband controller in PoP
version.

e2
/// DB3370 or DB3430
R1A/XX
D
E
F
G
H
I
J
b
Green package
ST-Ericsson device number
ST-Ericsson revision number
Assembly plant
BE sequence
Diffusion traceability plant
Country of origin
Test and finishing plant
Assembly year
Assembly week
Pin1-ref
Figure 9 Component markings: PoP
ST-Ericsson device number DB3370, or DB3430
Each digital baseband controller unit is marked as follows:
The ST-Ericsson external family product number
The number/batch ID and assembly sequence [manufacturers information]
The date of manufacture, that is, year and week in a digit code according to ISO 8601
(yyyyww) or batch code [manufacturers information]
The ST-Ericsson revision code and internal ID suffix.
A terminal identification index on the case (pin 1, where applicable).
Note: The markings are resistant to mechanical wear and common
fluids that the digital baseband controller may be exposed to
during normal handling, storage, and operation.
DB3370
R1A/XX

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11 Electrical characteristics
11.1 Absolute maximum ratings
The device reliability can be adversely affected by exposure to the absolute maximum
ratings for extended periods.
Table 7 Absolute maximum ratings
Symbol Parameter Condition Min. Max. Unit
V
DD
Supply voltage core - -0.30 1.32 V
V
DDA
Supply voltage analog cells - -0.30 2.75 V
V
DDE
Supply voltage IOs without level shifter - -0.30 2.75 V
V
DDE
Supply voltage IOs with level shifter - -0.30 2.75 V
V
DDE
Supply voltage IOs with level shifter and fail
safe
- -0.30 2.75 V
V
PP
Fuse programming voltage - -0.30 7.10 V
V
I
Input voltage IOs without level shifter - -0.30 2.75 V
V
I
Input voltage IOs with level shifter - -0.30 2.75 V
V
I
Input voltage IOs with level shifter and fail safe - -0.30 2.75 V
V
O
Output voltage IOs with level shifter - -0.30 2.75 V
V
O
Output voltage IOs with level shifter and fail safe - -0.30 2.75 V
I
IC
Input clamp current V
I
< V
SS
or V
I
> V
DD
- - 100 mA
I
OC
Output clamp current V
O
< V
SS
or V
O
> V
DD
- - 100 mA
ESD Human body model - 2,000 - V
T
amb
Operating ambient temperature Still air -40 85 C
T
stg
Storage temperature Still air -65 150 C

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11.2 Normal operating conditions
The device can operate in a mixed-voltage environment. To obtain the correct function on
IOs, analog blocks, and subcores, the controlling block (main core) must be supplied first
during power up.
To guarantee system functionality, PWRRSTn must be active until all supplies are valid
during power up and go active before any supply drops during power down.
The device must be used in normal operating conditions, see Subsection 11.2.1, unless
otherwise specified.
11.2.1 Characteristics
Table 8 Characteristics
Symbol Parameter

Condition Min. Typ. Max. Unit
t
amb
Operating ambient temperature Still air -30 25 85 C
Clk
in
Main clock square wave input - - 26.0 - MHz
Clk
in
RTC clock square wave input - - 32.768 - kHz
Noise
A
Supply noise 5 MHz, % RMS of V
DD
All supplies - - 1 %
Noise
B
Supply noise 104 MHz, % RMS of V
DD
All supplies - - 1 %
V
DD
Supply voltage core Active mode 1.12 1.20 1.30 V
V
DD
Supply voltage core Idle mode 0.96 1.05 1.10 V
V
DDA
Supply voltage analog cells PLL - 2.35 2.5 2.65 V
V
DDA
Supply voltage analog cells DAC/ADC - 2.35 2.50 2.65 V
V
DDE
Supply voltage IO Normal
operation
1.70 1.80 1.90 V
V
PP
Fuse programming voltage During fuse
programming
6.95 7.00 7.05 V
V
DD
Supply voltage core During fuse
programming
1.12 1.20 1.30 V
V
DDA_AF
Supply voltage fuse During fuse
programming
2.35 2.5 2.75 V
V
DDE
Supply voltage IO During fuse
programming
1.7 1.8 1.9 V
t
amb
Temperature range
(Environment = DARK)
During fuse
programming
+10 - +45 C
I
DD
Supply current core Online
17
- 300 500 mA


17
Digital Signal Processor (DSP) and CPUs running at full speed. All parts powered up.

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Symbol Parameter

Condition Min. Typ. Max. Unit
I
DDA
Supply current analog - - - 20 mA
I
DDE
Supply current IO
18
- - 55 mA
I
DDQ
Leakage current V
DD
19
@1.0 V - 1.14 mA
I
DDQ
Leakage current V
DD

19
@1.2 V - 0.28 (1.50) mA
I
DDQA
Leakage current V
DDA
19
- 150 450 A
I
DDQE
Leakage current V
DDE

19
-

20 100 A
C
IN
Input capacitance IO
20
-

- 3.5 pF
Note: Leakage at 1.2 V is only an estimated value, not measured.
11.3 IO characteristics
11.3.1 Input clock MCLK
The conditions are as defined in Section 11.2, unless otherwise specified.
Table 9 Input clock MCLK characteristics
Symbol Parameter Condition Min. Typ. Max. Unit
f
in
Input frequency - - 26 - MHz
t
DCin
Input duty cycle (including jitter) - 45 50 55 %
t
r
/t
f
Clock input rise and fall time 20-80% 1 - 5 ns
t
jitterin
Input jitter -0.5 - 0.5 %
11.3.2 Input clock RTCCLKIN
The conditions are as defined in Section 11.2, unless otherwise specified.
Table 10 Input clock RTCCLKIN characteristics
Symbol Parameter Condition Min. Typ. Max. Unit
f
in
Input frequency - - 32,768 - Hz
t
DCin
Input duty cycle (including jitter) - 35 50 65 %

18
Max. allowed total IO current
19
Value specified at Tamb = 25 C VDD = Typ.
20
Sum of the package maximum capacitance and the maximum buffer input capacitance.

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Symbol Parameter Condition Min. Typ. Max. Unit
t
r
/t
f
Clock input rise and fall time 20-80% 1 - 20 ns
t
jitterin
Input jitter -0.30 - 0.30 %
11.3.3 Output clock SYSCLK [2:0]
The conditions are as defined in Section 11.2, unless otherwise specified.
Table 11 Output clock SYSCLK characteristics
Symbol Parameter Condition Min. Typ. Max. Unit
f
out
Output frequency - 0 - 52 MHz
t
DCin
Output duty cycle (including jitter) - 45 50 55 %
t
r
Rise time C
L
= 10 pF 0.86 - 0.93 ns
t
r
Rise time C
L
= 50 pF 3.08 - 3.41 ns
t
f
Fall time C
L
= 10 pF 0.84 - 0.93 ns
t
f
Fall time C
L
= 50 pF 3.17 - 3.53 ns
t
jitterout
Output jitter -2 - 2 %
11.3.4 Bidirectional buffer 2 mA 1.8 V
Vendor reference: BD2SCARyQP_1 V8_LIN (IO65LPVT_SF_1 V8)
The Y in the vendor reference indicates whether the cell has pull-up (U), pull-down (D) or
both (UD).
The buffer is level-shifting.
The buffer has internal, controllable pull-up and pull-down. The use of the pull-up and
pull-down is described in Reference [6].
The conditions are as defined in Section 11.2, unless otherwise specified.
Table 12 Bidirectional buffer 2 mA 1.8 V characteristics
Symbol Parameter Condition Min. Typ. Max. Unit
V
DD
Supply voltage core interface - 1.12 1.20 1.30 V
V
DDE
Supply voltage IO cell - 1.70 1.80 1.90 V
V
IL
Low-level input voltage - 0 - 0.35 V
DDE
V
V
IH
High-level input voltage - 0.65 V
DDE
- V
DDE
V
V
hys
Hysteresis (V
IT+
- V
IT-
) - 150 - - mV

Digital baseband controller Data sheet Electrical characteristics
DB3370 and DB3430



1424-LZN 901 2501/1 Uen Rev G 2010-11-02

LZN 901 2501/1 R2B
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Copyright ST-Ericsson 2009, 2010. All rights reserved. COMPANY CONFIDENTIAL

Symbol Parameter Condition Min. Typ. Max. Unit
I
IL
Low-level input current V
IL
-2 - 2 A
I
IH
High-level input current V
IH
-2 - 2 A
f
max
Input cell frequency V
IL
, V
IH
- - 104 MHz
t
DCout
Input cell duty cycle out t
DCin
50%, V
IL
, V
IH
45 - 55 %
I
OL
Low-level output current - - - 2.00 mA
I
OH
High-level output current - -2.00 - - mA
I
OZ
Output leakage current V
O
= V
DD
or V
SS
-1 - 1 A
V
OL
Low-level output voltage I
OL
0 - 0.20 V
V
OL
Low-level output voltage I
OL
= 100 A 0 - 0.10 V
V
OH
High-level output voltage I
OH
V
DDE
- 0.20 - V
DDE
V
V
OH
High-level output voltage I
OH
= -100 A V
DDE
- 0.10 - V
DDE
V
V
IO
IO cell operating voltage
21
0 - V
DDE
V
V
IO
IO cell operating voltage - -0.3 - V
DDE
+

0.3 V
f
max
Output cell frequency C
L
= 10 pF - - 52 MHz
f
max
Output cell frequency C
L
= 20 pF - - 26 MHz
t
DCout
Output cell duty cycle out t
DCin
50%, V
OL,
V
OH

45 - 55 %
z
out
Output impedance - - 80 -
t
r
Rise time C
L
= 10 pF 1.42 - 1.53 ns
t
r
Rise time C
L
= 50 pF 5.84 - 6.45 ns
t
f
Fall time C
L
= 10 pF 1.49 - 1.60 ns
t
f
Fall time C
L
= 50 pF 6.41 - 7.14 ns
I
EN
Pull-up current enabled - -85 -36 -18 A
I
EN
Pull-down current enabled - 15 36 88 A
I
DIS
Pull-up/pull-down current disabled - -1 - 1 A
I
Z
Total IO cell leakage current - -1 - 1 A

21
Limited to less than of the period time

Digital baseband controller Data sheet Electrical characteristics
DB3370 and DB3430



1424-LZN 901 2501/1 Uen Rev G 2010-11-02

LZN 901 2501/1 R2B
55 (86)
Copyright ST-Ericsson 2009, 2010. All rights reserved. COMPANY CONFIDENTIAL

11.3.5 Bidirectional buffer 4 mA 1.8 V
Vendor reference: BD4SCARyQP_1 V8_LIN (IO65LPVT_SF_1 V8)
The Y in the vendor reference indicates whether the cell has pull-up (U), pull-down (D) or
both (UD).
The buffer is level-shifting.
The buffer has internal, controllable pull-up and pull-down. The use of the pull-up and
pull-down is described in Reference [6].
The conditions are as defined in Section 11.2, unless otherwise specified.
Table 13 Bidirectional buffer 4 mA 1.8 V characteristics
Symbol Parameter Condition Min. Typ. Max. Unit
V
DD
Supply voltage core interface - 1.12 1.20 1.30 V
V
DDE
Supply voltage IO cell - 1.70 1.80 1.90 V
V
IL
Low-level input voltage - 0 - 0.35 V
DDE
V
V
IH
High-level input voltage - 0.65 V
DDE
- V
DDE
V
V
hys
Hysteresis (V
IT+
- V
IT-
) - 150 - - mV
I
IL
Low-level input current V
IL
-2 - 2 A
I
IH
High-level input current V
IH
-2 - 2 A
f
max
Input cell frequency V
IL
, V
IH
- - 104 MHz
t
DCout
Input cell duty cycle out t
DCin
50%, V
IL
, V
IH
45 - 55 %
I
OL
Low-level output current - - - 4.00 mA
I
OH
High-level output current - -4.00 - - mA
I
OZ
Output leakage current V
O
= V
DD
or V
SS
-1 - 1 A
V
OL
Low-level output voltage I
OL
0 - 0.20 V
V
OL
Low-level output voltage I
OL
= 100 A 0 - 0.10 V
V
OH
High-level output voltage I
OH
V
DDE
-

0.20 - V
DDE
V
V
OH
High-level output voltage I
OH
= -100 A V
DDE
-

0.10 - V
DDE
V
V
IO
IO cell operating voltage
22
0 - V
DDE
V
V
IO
IO cell operating voltage - -0.3 - V
DDE
+

0.3 V
f
max
Output cell frequency C
L
= 10 pF - - 104 MHz
f
max
Output cell frequency C
L
= 30 pF - - 60 MHz

22
Limited to less than of the period time

Digital baseband controller Data sheet Electrical characteristics
DB3370 and DB3430



1424-LZN 901 2501/1 Uen Rev G 2010-11-02

LZN 901 2501/1 R2B
56 (86)
Copyright ST-Ericsson 2009, 2010. All rights reserved. COMPANY CONFIDENTIAL

Symbol Parameter Condition Min. Typ. Max. Unit
t
DCout
Output cell duty cycle out t
DCin
50%, V
OL,
V
OH

45 - 55 %
z
out
Output impedance - - 50 -
t
r
Rise time C
L
= 10 pF 0.86 - 0.93 ns
t
r
Rise time C
L
= 50 pF 3.08 - 3.41 ns
t
f
Fall time C
L
= 10 pF 0.84 - 0.93 ns
t
f
Fall time C
L
= 50 pF 3.17 - 3.53 ns
I
EN
Pull-up current enabled - -85 -36 -18 A
I
EN
Pull-down current enabled - 15 36 88 A
I
DIS
Pull-up/pull-down current disabled - -1 - 1 A
I
Z
Total IO cell leakage current - -1 - 1 A
11.3.6 Bidirectional buffer 8 mA 1.8 V
Vendor reference: BD8SCARyQP_1 V8_LIN (IO65LPVT_SF_1 V8)
The Y in the vendor reference indicates whether the cell has pull-up (U), pull-down (D) or
both (UD).
The buffer is level-shifting.
The buffer has internal, controllable pull-up and pull-down. The use of the pull-up and
pull-down is described in Reference [6].
The conditions are as defined in Section 11.2, unless otherwise specified.
Table 14 Bidirectional buffer 8 mA 1.8 V characteristics
Symbol Parameter Condition Min. Typ. Max. Unit
V
DD
Supply voltage core interface - 1.12 1.20 1.30 V
V
DDE
Supply voltage IO cell - 1.70 1.80 1.90 V
V
IL
Low-level input voltage - 0 - 0.35 V
DDE
V
V
IH
High-level input voltage - 0.65 V
DDE
- V
DDE
V
V
hys
Hysteresis (V
IT+
to V
IT-
) - 160 - - mV
I
IL
Low-level input current V
IL
-1 - 1 A
I
IH
High-level input current V
IH
-1 - 1 A
f
max
Input cell frequency V
IL
, V
IH
- - 104 MHz

Digital baseband controller Data sheet Electrical characteristics
DB3370 and DB3430



1424-LZN 901 2501/1 Uen Rev G 2010-11-02

LZN 901 2501/1 R2B
57 (86)
Copyright ST-Ericsson 2009, 2010. All rights reserved. COMPANY CONFIDENTIAL

Symbol Parameter Condition Min. Typ. Max. Unit
t
DCout
Input cell duty cycle out t
DCin
50%, V
IL
,
V
IH

45 - 55 %
I
OL
Low-level output current - - - 8.00 mA
I
OH
High-level output current - -8.00 - - mA
I
OZ
Output leakage current V
O
= V
DD
or
V
SS

-1 - 1 A
V
OL
Low-level output voltage I
OL
0 - 0.20 V
V
OL
Low-level output voltage I
OL
= 100 A 0 - 0.10 V
V
OH
High-level output voltage I
OH
V
DDE
-

0.20 - V
DDE
V
V
OH
High-level output voltage I
OH
= -100 A V
DDE
-

0.10 - V
DDE
V
V
IO
IO cell operating voltage
23
0 - V
DDE
V
V
IO
IO cell operating voltage -0.3 - V
DDE
+ 0.3 V
f
max
Output cell frequency C
L
= 10 pF - - 104 MHz
f
max
Output cell frequency C
L
= 50 pF - - 52 MHz
t
DCout
Output cell duty cycle out t
DCin
50%,
V
OL,
V
OH

45 - 55 %
Cz
out
Output impedance - - 20 -
t
r
Rise time C
L
= 10 pF 0.58 - 0.64 ns
t
r
Rise time C
L
= 50 pF 1.70 - 1.87 ns
t
f
Fall time C
L
= 10 pF 0.56 - 0.62 ns
t
f
Fall time C
L
= 50 pF 1.84 - 1.98 ns
I
EN
Pull-up current enabled - -85 -36 -18 A
I
EN
Pull-down current enabled - 15 36 88 A
I
DIS
Pull-up/pull-down current disabled - -1 - 1 A
I
Z
Total IO cell leakage current - -1 - 1 A

23
Limited to less than of the period time

Digital baseband controller Data sheet Electrical characteristics
DB3370 and DB3430



1424-LZN 901 2501/1 Uen Rev G 2010-11-02

LZN 901 2501/1 R2B
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Copyright ST-Ericsson 2009, 2010. All rights reserved. COMPANY CONFIDENTIAL

11.3.7 Bidirectional buffer 1.8 V
Vendor reference: BDPROGMOBDDRSCARUDQP_1 V8_2 V5_TF_LIN
(IO65LPSVTHVT_SF_TF_DDR_1 V8_2 V5_7M4X0Y2Z)
BDCLKMOBDDRSCARUDQP_1 V8_2 V5_TF_LIN
(IO65LPSVTHVT_SF_TF_DDR_1 V8_2 V5_7M4X0Y2Z)
The Y in the vendor reference indicates whether the cell has pull-up (U), pull-down (D) or
both (UD). The use of the pull-up and pull-down is described in Reference [6].
The buffer has three input signals (ZOUT-PROGA, PROGA, and PROGB). Table 15
contains the four different configurations that can be selected.
Table 15 Modes of operation
ZOUT-PROGA PROGA PROGB Mode Impedance [] Description
0 0 0 000 50 -
0 0 1 001 50 -
0 1 0 010 50 -
0 1 1 011 50 -
The buffer is level-shifting.
The buffer has internal, controllable pull-up and pull-down.
The conditions are as defined in Section 11.2, unless otherwise specified.
Table 16 Bidirectional buffer with programmable slope 1.8 V characteristics
Symbol Parameter Condition Min. Typ. Max. Unit
V
DD
Supply voltage core interface - 1.12 1.20 1.30 V
V
DDE
Supply voltage IO cell - 1.70 1.80 1.90 V
V
IL
Low-level input voltage - 0 - 0.3 V
V
IH
High-level input voltage - 0.8 V
DDE
- V
DDE
V
V
hys
Hysteresis (V
IT+
-V
IT-
) - 200 - - mV
I
IL
Low-level input current V
IL
-1 - 1 A
I
IH
High-level input current V
IH
-1 - 1 A
f
max
Input cell frequency V
IL
,V
IH
- - 104 MHz
t
DCout
Input cell duty cycle out t
DCin
50%, V
IL
,V
IH
45 - 55 %
I
OL
Low-level output current All modes - - 2.00 mA
I
OH
High-level output current All modes -2.00 - - mA
I
OZ
Output leakage current V
O
= V
DD
or V
SS
-1 - 1 A

Digital baseband controller Data sheet Electrical characteristics
DB3370 and DB3430



1424-LZN 901 2501/1 Uen Rev G 2010-11-02

LZN 901 2501/1 R2B
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Copyright ST-Ericsson 2009, 2010. All rights reserved. COMPANY CONFIDENTIAL

Symbol Parameter Condition Min. Typ. Max. Unit
V
OL
Low-level output voltage I
OL
0 - 0.20 V
V
OH
High-level output voltage I
OH
0.9 V
DDE
- V
DDE
V
V
IO
IO cell operating voltage - 0 - V
DDE
V
V
IO
IO cell operating voltage
24
-0.3 - V
DDE
+

0.3 V
f
max
Output cell frequency Mode = 000
C
L
= 5 pF
- - 260 MHz
f
max
Output cell frequency Mode = 001
C
L
= 5 pF
- - 260 MHz
f
max
Output cell frequency Mode = 010
C
L
= 5 pF
- - 260 MHz
f
max
Output cell frequency Mode = 011
C
L
= 5 pF
- - 260 MHz
t
DCout
Output cell duty cycle out t
DCin
50%, V
OL,
V
OH
45 - 55 %
z
out
Output impedance 50 mode - 50 -
t
r
Rise time Mode = 000
C
L
= 8 pF
0.58247 - 0.79954 ns
t
r
Rise time Mode = 001
C
L
= 8 pF
0.57903 - 0.7755 ns
t
r
Rise time Mode = 010
C
L
= 8 pF
0.56486 - 0.81862 ns
t
r
Rise time Mode = 011
C
L
= 8 pF
0.55789 - 0.7514 ns
t
r
Rise time Mode = 000
C
L
= 15 pF
0.96636 - 1.2772 ns
t
r
Rise time Mode = 001
C
L
= 15 pF
0.96461 - 1.2635 ns
t
r
Rise time Mode = 010
C
L
= 15 pF
0.95179 - 1.2752 ns
t
r
Rise time Mode = 011
C
L
= 15 pF
0.94717 - 1.24 ns
t
r
Rise time Mode = 000
C
L
= 22 pF
1.359 - 1.766 ns

24
Limited to less than of the period time

Digital baseband controller Data sheet Electrical characteristics
DB3370 and DB3430



1424-LZN 901 2501/1 Uen Rev G 2010-11-02

LZN 901 2501/1 R2B
60 (86)
Copyright ST-Ericsson 2009, 2010. All rights reserved. COMPANY CONFIDENTIAL

Symbol Parameter Condition Min. Typ. Max. Unit
t
r
Rise time Mode = 001
C
L
= 22 pF
1.359 - 1.756 ns
t
r
Rise time Mode = 010
C
L
= 22 pF
1.349 - 1.755 ns
t
r
Rise time Mode = 011
C
L
= 22 pF
1.346 - 1.732 ns
t
r
Rise time Mode = 000
C
L
= 30 pF
1.817 - 2.330 ns
t
r
Rise time Mode = 001
C
L
= 30 pF
1.816 - 2.322 ns
t
r
Rise time Mode = 010
C
L
= 30 pF
1.806 - 2.315 ns
t
r
Rise time Mode = 011
C
L
= 30 pF
1.802 - 2.302 ns
t
f
Fall time Mode = 000
C
L
= 8 pF
0.564 - 0.862 ns
t
f
Fall time Mode = 001
C
L
= 8 pF
0.572 - 0.835 ns
t
f
Fall time Mode = 010
C
L
= 8 pF
0.546 - 0.837 ns
t
f
Fall time Mode = 011
C
L
= 8 pF
0.529 - 0.751 ns
t
f
Fall time Mode = 000
C
L
= 15 pF
0.911 - 1.288 ns
t
f
Fall time Mode = 001
C
L
= 15 pF
0.914 - 1.272 ns
t
f
Fall time Mode = 010
C
L
= 15 pF
0.900 - 1.268 ns
t
f
Fall time Mode = 011
C
L
= 15 pF
0.891 - 1.215 ns
t
f
Fall time Mode = 000
C
L
= 22 pF
1.272 - 1.742 ns
t
f
Fall time Mode = 001
C
L
= 22 pF
1.270 - 1.732 ns

Digital baseband controller Data sheet Electrical characteristics
DB3370 and DB3430



1424-LZN 901 2501/1 Uen Rev G 2010-11-02

LZN 901 2501/1 R2B
61 (86)
Copyright ST-Ericsson 2009, 2010. All rights reserved. COMPANY CONFIDENTIAL

Symbol Parameter Condition Min. Typ. Max. Unit
t
f
Fall time Mode = 010
C
L
= 22 pF
1.264 - 1.727 ns
t
f
Fall time Mode = 011
C
L
= 22 pF
1.261 - 1.695 ns
t
f
Fall time Mode = 000
C
L
= 30 pF
1.686 - 2.280 ns
t
f
Fall time Mode = 001
C
L
= 30 pF
1.686 - 2.271 ns
t
f
Fall time Mode = 010
C
L
= 30 pF
1.678 - 2.263 ns
t
f
Fall time Mode = 011
C
L
= 30 pF
1.680 - 2.244 ns
I
EN
Pull-up current enabled - -85 -36 -18 A
I
EN
Pull-down current enabled - 15 36 88 A
I
DIS
Pull-up/pull-down current disabled - -1 - 1 A
I
Z
Total IO cell leakage current - -1 1 A
11.3.8 subLVDS buffer 1.8 V
Vendor reference: SUBLVDS_IN_1 V8_SF_LIN
(IO65LPSVTHVT_SF_SUBLVDS_1 V8_50_7M4X0Y2Z)
The buffer is a standard Low Voltage Differential Signal (LVDS) buffer used as a Standard
Mobile Imaging Architecture (SMIA) buffer.
The buffer can operate in the following two modes:
As a standard single-ended 1.8 V input buffer, also referred to as Single-ended (SE)
Mode.
As a low voltage differential input buffer, also referred to as LVDS mode. In this
mode, an LVDS input buffer has two input pads.
The termination resistor is separately controlled and must be disabled in mode 1.
The buffer is level-shifting.
The conditions are as defined in Section 11.2, unless otherwise specified.

Digital baseband controller Data sheet Electrical characteristics
DB3370 and DB3430



1424-LZN 901 2501/1 Uen Rev G 2010-11-02

LZN 901 2501/1 R2B
62 (86)
Copyright ST-Ericsson 2009, 2010. All rights reserved. COMPANY CONFIDENTIAL

Table 17 SE mode characteristics
Symbol Parameter Condition Min. Typ. Max. Unit
V
DD
Supply voltage core
interface
- 1.12 1.20 1.30 V
V
DDE
Supply voltage IO cell - 1.70 1.80 1.90 V
V
IL
Low-level input voltage - 0 - 0.35 V
DDE
V
V
IH
High-level input voltage - 0.65 V
DDE
- V
DDE
V
V
hys
Hysteresis (V
IT+
- V
IT-
) - 160 - - mV
I
IL
Low-level input current V
IL
-2 - 2 A
I
IH
High-level input current V
IH
-2 - 2 A
V
IO
IO-cell operating voltage - -0.3 - V
DDE
+ 0.3 V
f
max
Input cell frequency V
IL
, V
IH
- - 104 MHz
t
DCout
Input cell duty cycle out t
DCin
50%, V
IL
, V
IH
45 - 55 %
I
Z
Total IO cell leakage current - -1 - 1 A
Table 18 Differential mode characteristics
Symbol Parameter Condition Min. Typ. Max. Unit
V
DD
Supply voltage core interface - 1.12 1.20 1.30 V
V
DDE
Supply voltage IO cell - 1.70 1.80 1.90 V
I
DDE
Current consumption R
term
= 100 ,
330 MHz
- - 2.0 mA
I
DDE
Current consumption AC, A/MHz - - 6.1 A
V
CM
Differential input range
25
(V
DDE
/2) -
0.30
V
DDE
/2 (V
DDE
/2)
+ 0.30
V
V
THL
Differential input threshold
low
- -25 - - mV
V
THH
Differential input threshold
high
- - - 25 mV
R
term
Internal termination resistor
25
75 100 125
f
max
Input cell frequency C
L
= 5 pF - - 330 MHz
t
DCout
Input cell duty cycle out t
DCin
50% 45 - 55 %
I
Z
Total IO cell leakage current - -1 - 1 A
t
PDup
Power up time - - - 20 s
t
PDdwn
Power down time - - - 20 s

25
Outside the SMIA standard

Digital baseband controller Data sheet Electrical characteristics
DB3370 and DB3430



1424-LZN 901 2501/1 Uen Rev G 2010-11-02

LZN 901 2501/1 R2B
63 (86)
Copyright ST-Ericsson 2009, 2010. All rights reserved. COMPANY CONFIDENTIAL

11.4 I
2
C Input/Output cell
11.4.1 I
2
C bidirectional buffer 1.8/2.75 V
Vendor reference: I2C_MASTER_1 V8_2 V85T_LIN
(IO65LPVT_SF_I2C_MASTER_1 V8_2 V85T_7M4X0Y2Z)
The cell can operate at both 1.8 V and 2.75 V bus voltage.
The buffer is level-shifting.
The IO cell is fail safe that is, the IO voltage may exceed the supply voltage.
The IO cell is designed for Fast mode with a maximum of 400 kbit/s.
The conditions are as defined in Section 11.2, unless otherwise specified.
Table 19 I
2
C bidirectional buffer 1.8/2.75 V characteristics
Symbol Parameter Condition Min. Typ. Max. Unit
V
DD
Supply voltage core interface - 1.12 1.20 1.30 V
V
DDE
Supply voltage IO cell (low voltage
mode)
f
max
= 1 MHz 1.12 1.20 1.30 V
V
DDE
Supply voltage IO cell - 1.70 1.80 1.90 V
V
IL
Low-level input voltage - 0 - 0.3 V
DDE
V
V
IH
High-level input voltage - 0.7 V
DDE
- 2.85 V
V
IH
High-level input voltage (low
voltage mode)
V
DDE
= 1.2 V V
DDE
- 2.85 V
V
BUS
Bus voltage - -0.5 - 2.85 V
V
hys
Hysteresis (V
IT+
- V
IT-
) - 0.1 V
DDE
- - mV
I
I
Total IO cell leakage and input
current at
V
I
= 0.1 V
BUS
and V
I
= 0.9 V
BUS

V
BUS
= 1.80 V -10 - 10 A
I
I
Total IO cell leakage and input
current at
V
I
= 0.1 V
BUS
and V
I
= 0.9 V
BUS

V
BUS
= 2.75 V

-10 - 10 A
I
IH
High-level input current Fail safe mode -1 - 1 A
f
max
Input cell frequency V
IL
, V
IH
- - 400 kHz
f
max
Input cell frequency V
IL
, V
IH
26
- - 24 MHz
t
DCout
Input cell duty cycle out t
DCin
50%, V
IL
, V
IH
45 - 55 %

26
Without glitch suppression

Digital baseband controller Data sheet Electrical characteristics
DB3370 and DB3430



1424-LZN 901 2501/1 Uen Rev G 2010-11-02

LZN 901 2501/1 R2B
64 (86)
Copyright ST-Ericsson 2009, 2010. All rights reserved. COMPANY CONFIDENTIAL

Symbol Parameter Condition Min. Typ. Max. Unit
I
OL
Low-level output current - - - 3.00 mA
V
OL
Low-level output voltage I
OL
V
BUS
= 1.80 V
0 - 0.20 V
DD
V
V
OL
Low-level output voltage I
OL
V
BUS
= 2.75 V
0 - 0.4 V
f
max
Output cell frequency C
L
= 10 - 400 pF
27
- - 400 kHz
f
max
Output cell frequency C
L
= 10-60 pF
28
- - 400 kHz
t
of
Fall time from V
IH
min to V
IL
max C
L
= 10-400 pF
29
20

+

0.1C
b
- 250 ns
t
SP
Pulse width of spikes that have to
be suppressed by the input filter.
- 0 - 50 ns
11.5 PLL
11.5.1 PLL_26x
Vendor reference: PLL_26x_CMOS065LP
The PLL output frequency (f
out
) is 397 times the input frequency (f
in
).
The conditions are as defined in Section 11.2, unless otherwise specified.
Table 20 PLL_26x characteristics
Symbol Parameter Condition Min. Typ. Max. Unit
V
DD
Supply voltage core interface - 0.95 1.20 1.35 V
V
DDA
Supply voltage to analog - 1.70 1.80 2.75 V
I
DD
Current consumption active mode V
DD
- 30 50 A
I
DD
Current consumption active mode V
DDA
- 120 150 A
I
DDQ
Current consumption power down V
DD
- 0.1 1 A
I
DDQ
Current consumption power down V
DDA
- 0.1 1 A
f
in
Input frequency - 32,440 32,768 33,096 Hz
t
DCin
Input duty cycle (including jitter) - 30 50 70 %
t
r
/t
f
Clock input rise and fall time - - - 2 ns

27
With an external 1.0 k pull-up resistor
28
With an external 3.3 k pull-up resistor
29
Cb = Capacitance of one bus line in pF

Digital baseband controller Data sheet Electrical characteristics
DB3370 and DB3430



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Symbol Parameter Condition Min. Typ. Max. Unit
t
jitterin
Input jitter -0.5 0.5 %
f
loop
Loop filter cut off frequency - - 1800 - Hz
Load Cell drive capability - - - 0.35 pF
f
out
Output frequency - - 397 f
in
- MHz
t
DCout
Output duty cycle (including jitter) - 45 50 55 %
t
jitterout
Output jitter -2 - 2 %
Ph
err
Static phase error - -250 - 250 ps
t
lock
Locking time - - - 30 ms
t
PD
Minimum width of Power
Down (PDN) pulse required
- 2 - - ms
11.5.2 PLL_416x_A
Vendor reference: PLL_416x_A_CMOS065LP
The PLL can operate in the following modes, controlled by the SEL input signal:
The PLL output frequency (f
out
) is 8 times the input frequency (f
in
) when SEL = 1.
The PLL output frequency (f
out
) is 16 times the input frequency (f
in
) when SEL = 0. In
this mode the input clock to the PLL could come from the PLL_26x (that is, PLL_26x
and PLL_416x_A in series).
The conditions are as defined in Section 11.2, unless otherwise specified.
Table 21 PLL_416x_A characteristics
Symbol Parameter Condition Min. Typ. Max. Unit
V
DD
Supply voltage core interface - 0.95 1.20 1.35 V
V
DDA
Supply voltage to analog - 1.70 1.80 2.75 V
I
DD
Current consumption active mode V
DD
- 510 580 A
I
DD
Current consumption active mode V
DDA
- 320 420 A
I
DDQ
Current consumption power down V
DD
- 0.1 6 A
I
DDQ
Current consumption power down V
DDA
- 0.1 1 A
f
in
Input frequency SEL = 0 12.85 13 13.15 MHz
f
in
Input frequency SEL = 1 25.70 26 26.30 MHz
t
DCin
Input duty cycle (including jitter) - 30 50 70 %
t
r
/t
f
Clock input rise and fall time - - - 0.2 ns

Digital baseband controller Data sheet Electrical characteristics
DB3370 and DB3430



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Symbol Parameter Condition Min. Typ. Max. Unit
t
jitterin
Input jitter -2 - 2 %
f
loop
Loop filter cut off frequency - - 750 kHz
Load Cell drive capability - - - 0.35 pF
f
out
Output frequency SEL = 0 - 16 f
in
- MHz
f
out
Output frequency SEL = 1 - 8 f
in
- MHz
t
DCout
Output duty cycle (including jitter) - 45 50 55 %
t
jitterout
Output jitter -2 - 2 %
Ph
err
Static phase error - -200 - 200 ps
t
lock
Locking time - - - 100 s
t
PD
Minimum width of PDN pulse
required
- 10 - - s
11.5.3 PLL_240x
Vendor reference: PLL_240x_CMOS065LP
The PLL generates the following output frequencies:
F60. The PLL output frequency f
out60
= f
in
/13 30.
F48. The PLL output frequency f
out48
= f
in
/13 24.
The conditions are as defined in Section 11.2, unless otherwise specified.
Table 22 PLL_240x characteristics
Symbol Parameter Condition Min. Typ. Max. Unit
V
DD
Supply voltage core interface - 0.95 1.20 1.35 V
V
DDA
Supply voltage to analog - 1.70 1.80 2.75 V
I
DD
Current consumption active mode V
DD
- 425 480 A
I
DD
Current consumption active mode V
DDA
- 130 160 A
I
DDQ
Current consumption power down V
DD
- 0.1 1 A
I
DDQ
Current consumption power down V
DDA
- 0.1 1 A
f
in
Input frequency - 25.7 26 26.3 MHz
t
r
/t
f
Clock input rise and fall time - - - 0.2 Ns
t
jitterin
Input jitter -1 - 1 %
t
DCin
Input duty cycle (including jitter) - 30 50 70 %
f
loop
Loop filter cut off frequency - - 120 - kHz

Digital baseband controller Data sheet Electrical characteristics
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Symbol Parameter Condition Min. Typ. Max. Unit
Load Cell drive capability - - - 0.35 pF
f
out48
Output frequency - - f
in
/13 24 - MHz
f
out60
Output frequency - - f
in
/13 30 - MHz
t
DCout
Output duty cycle (including jitter) f
out48
40 50 60 %
t
DCout
Output duty cycle (including jitter) f
out60
45 50 55 %
t
jitterout
Output jitter f
out48
-400 - 400 ps
t
jitterout
Output jitter f
out60
-400 - 400 ps
Ph
err
Static phase error - -250 - 250 ps
t
lock
Locking time - - - 100 s
t
PD
Minimum width of PDN pulse
required
- 20 - - s

Digital baseband controller Data sheet Electrical characteristics
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11.6 Analog pads
The ANA_2 V5_LIN is a bidirectional pad for analog signals. It contains primarily
Electrostatic Discharge (ESD) diode protections in parallel with the pad and a secondary
diode protection after a serial resistor.
11.7 Converters
11.7.1 WCDMA I and Q Sigma-Delta ADC
Vendor reference: TL01_Converters
Unless otherwise specified, the minimum and maximum values are given for the process
worst cases, that is the full junction temperature range (-30C to 125C) and the full
supply voltage range (V
DDA
from 2.35 V to 2.65 V), and the typical values are specified at
typical V
DDA
and temperature.
General conditions
The proposed converter is a second-order sigma delta modulator using a 3-bit
quantizer (seven levels). Therefore, it must at least be followed by a second-order multi-
rate decimation filter and a digital filter. A third-order decimator is suggested to have less
in-band folding of the out-of-band noise coming both from the input and from the
modulator itself.
The conditions are as defined in Section 11.2, unless otherwise specified.
Table 23 ADC specification
Parameter Condition Min. Typ. Max. Unit
V
DDA
- 2.35 2.5 2.65 V
V
DDA
current In active mode
30
- 7.5 11 mA
V
DDA
leakage current In power down, CK
steady, max. at
105C
31

- 0.3 14 A
Power Supply Rejection (PSR)
V
DDAAD
= 2.5 V
DC
+ 20 mV
RMS
,
f < 100 kHz
Input voltage = 0
40

-

-

dB
Junction temperature t
junc
-30 125 C

30
The complete cell: I and Q ADC + common parts + reference buffers (one for each ADC), but without the band gap reference
generator (common to all ADCs and DACs). The maximum value is at 125C and in worst process conditions.
31
Half cell:1(I+Q) ADC + their service circuits.

Digital baseband controller Data sheet Electrical characteristics
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Parameter Condition Min. Typ. Max. Unit
Maximum input voltage Differential peak-to-
peak
32

- 2 - V
Input signal bandwidth - 2.2 2.2 2.2 MHz
Input Common Mode Voltage (ICMV) - 0.75 - V
DDA
-

0.75 V
Output offset for both inputs connected
to a fixed common mode voltage
33
-30 - +30 mV
Signal to Noise and Distortion ratio
(SINAD) input level -2 dB
[2.2 MHz bandwidth]
CK = 46.08 MHz
V
in
= 1.59 V
ppd

f
in
2.2 MHz
34

40 - - dB
SINAD input level -6 dB
[2.2 MHz bandwidth]
CK = 46.08 MHz
V
in
= 1 V
ppd

f
in
2.2 MHz
40 - - dB
SINAD input level -32 dB
[2.2 MHz bandwidth]
CK = 46.08 MHz
V
in
= 50 mV
ppd

f
in
2.2 MHz
14 - - dB
SINAD input level 0 dB
[2.2 MHz bandwidth]
CK = 46.08 MHz
V
in
= 2 V
ppd

f
in
2.2 MHz
35

- 10 - dB
I/Q amplitude mismatch - -0.2 - +0.2 dB
I/Q phase mismatch - -1 - +1 Degrees
Equivalent input impedance Each input
36
20 - - k
In-band ripple (up to 1.7 MHz) Referred to DC value -0.1 - +0.1 dB
In-band ripple (from 1.7 MHz to
2.2 MHz)
Referred to DC
value
37

-0.3 - +0.3 dB
Output gain error DC value
38
-0.3 - +0.3 dB
Output gain variation with temperature Referred to 27C
value
39

-0.4 - +0.4 dB

32
The signal level normally does not exceed this value, so there is no need to design any headroom in the modulator. The reference
voltage can also be set to this value. If an over-voltage exceeds this value, the modulator immediately and automatically recovers
when the input returns to the normal values. The input of the converter is assumed to be DC coupled to the source voltage generator.
33
The value is constant in time and almost independent of supply voltage variations. It changes slightly with temperature (typ. 10%
over all the temperature range).
34
For out-of-band signals (2.2 MHz < fin < 23.04 MHz, Vin 1.59 Vppd), there is no degradation of the in-band noise.
35
For 1.59 V < V
in
< 2 V, there is a increasing clipping of the output wave form.
36
Equivalent Rin = 1/(2 fs Cs), where fs = sampling frequency and Cs = input switched capacitor
37
There is no out-of-band peaking in the gain. The gain starts decreasing after 2.2 MHz.
38
The reference voltage error is excluded in the calculation.
39
This is the variation of the gain, in the full temperature range, for one sample of the ADC, including the reference voltage.

Digital baseband controller Data sheet Electrical characteristics
DB3370 and DB3430



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Parameter Condition Min. Typ. Max. Unit
Startup time (ADC Power Down (PDAD)
from 1 to 0)
40
- - 250 s
Activation time
41
- 50 - s
Sampling clock Jittered clock - 46.08 - MHz
CK period - 19.23 - 24.04 ns
Output data width
42
- 3 - bits
Output data rate (sampling clock) - 46.08 - MHz
11.7.2 WCDMA I/Q 10 bit D/A converters and smoothing filters
Vendor reference: TL01_Converters
Unless otherwise specified, the minimum and maximum values are given for the process
worst cases, that is the full junction temperature range (-30C to 125C) and the full
supply voltage range (V
DDA
from 2.35 V to 2.65 V), and the typical values are specified at
typical V
DDA
and temperature.
The conditions are as defined in Section 11.2, unless otherwise specified.
Table 24 DACs and smoothing filters specification
Parameter Condition Min. Typ. Max. Unit
V
DDA
- 2.35 2.5 2.65 V
V
DDA
current In active mode
43
- 6.5 8 mA
V
DDA
leakage current In power down, CKDA
and input data steady
max. at 105C
- 0.2 15 A
PSR
V
DDADA
= 2.5 V
DC
+ 20 mV
RMS
,
f < 100 kHz
Input code = 000H
40
- -
dB
Junction temperature t
junc
-30 - 125 C
Analog output (differential)

40
Measured from the time that the power down is released to the time when the converter is within the specification (the startup of the
reference is assumed to be already finished).
41
Measured from the time that the power down is released to the time when the converter is functional (startup of reference finished)
42
The three output bits format is twos complement. The equivalent decimal content is between +3 and -4. To have symmetrical +7/-7
values and avoid systematic offset, it is necessary to add an LSB fixed to 1 (the final word length 4 bits).
43
The complete cell: I and Q DACs and filters + common parts + the reference buffer, but without the band gap reference generator
(common to all ADCs and DACs). The maximum value is at 125C and in worst process conditions.

Digital baseband controller Data sheet Electrical characteristics
DB3370 and DB3430



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Parameter Condition Min. Typ. Max. Unit
SINAD with full-scale output
voltage = 2 V
ppd

[2 MHz bandwidth]
CKDA = 52 MHz
f
in
2 MHz
1 < V
out
< 2 V
ppd
44

56 - - dB
Peak Harmonic or Spurious Noise
(SFDR)
[0-26 MHz] with full-scale output
voltage = 2 V
ppd

CKDA = 52 MHz
f
in
2 MHz
1 < V
out
< 2 V
ppd
44
- - -57 dB
SINAD with full-scale output
voltage = 1.8 V
ppd

[2 MHz bandwidth]
CKDA = 52 MHz
f
in
2 MHz
1.2 < V
out
< 1.8 V
ppd
44

56 - - dB
SFDR [0-26 MHz] with full-scale output
voltage = 1.8 V
ppd

CKDA = 52 MHz
f
in
< 2 MHz
1.2 < V
out
< 1.8 V
ppd
44

- - -57 dB
SINAD with full-scale output
voltage = 1.6 V
ppd

[2 MHz bandwidth]
CKDA = 52 MHz
f
in
2 MHz
1.3 < V
out
< 1.6 V
ppd
44

57 - - dB
SFDR [0-26 MHz] with full-scale output
voltage = 1.6 V
ppd

CKDA = 52 MHz
f
in
2 MHz
1.3 < V
out
<1.6 V
ppd
44

- - -58 dB
SINAD with full-scale output
voltage = 1.4 V
ppd

[2 MHz bandwidth]
CKDA = 52 MHz
f
in
<2 MHz
1.3 < V
out
< 1.4 V
ppd
44

58 - - dB
SFDR [0-26 MHz] with full-scale output
voltage = 1.4 V
ppd

CKDA = 52 MHz
f
in
2 MHz
1.3 < V
out
< 1.4 V
ppd
44

- - -59 dB

44
Sine wave input signal.

Digital baseband controller Data sheet Electrical characteristics
DB3370 and DB3430



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Parameter Condition Min. Typ. Max. Unit
Differential out-of-band noise spectral
density (with any fixed input code)
f > 2 MHz
f = 2 MHz
f = 5 MHz
f = 10 MHz
f = 50 MHz
F = 200 MHz
-

-
-
-
-
-
-


45
32
25
18
3


60
-
-
-
-
-


nV
RMS
/ Hz
nV
RMS
/ Hz
nV
RMS
/ Hz
nV
RMS
/ Hz
nV
RMS
/ Hz
nV
RMS
/ Hz
Cutoff filter frequency (-3 dB) CKDA = 52 MHz 3.72 4.0 4.28 MHz
Filter+sinc attenuation at 50 MHz CKDA = 52 MHz 64 - - dB
In-band ripple (up to 2 MHz) CKDA = 52 MHz
45
-0.5 - +0.2 dB
Full-scale output voltage Differential peak-to-peak.
200 mV step regulation.
46

1.4 - 2.0 V
Common mode output voltage 25 mV step regulation
47
1.15 - 1.45 V
Differential output offset error
(Input code: 000H)
No offset cancel
With offset cancel
48

-50
-2
-
-
+50
+2
mV
mV
Offset drift with temperature - -3 - +3 mV
Output gain error
49
-0.3 - +0.3 dB
Output gain variation with temperature Referred to 27C value
50
-0.25 - +0.25 dB
Common mode offset error
51
-20 - +20 mV
Resistive output load - R
diff

52
10 - - k
Capacitive output load - C
diff

52
- - 12 pF
Capacitive output load - C
sp
, C
sm

52
- - 5 pF
Output impedance - - - 130
Output impedance in power down
53
6.5 - k

45
Refers to the DC value. The minimum value of -0.5 dB is because of the attenuation at 2 MHz of the smoothing filter having a typical -
3 dB cut-off frequency at 4 MHz.
46
2 bits are necessary for this regulation: SELFS(1:0). 00 1.4 V, 01 1.6 V, 10 1.8 V, 11 2.0 V.
47
4 bits are necessary for this regulation: VCMREG(3:0). Table 25 describes the correspondence between the VCMREG(3:0) bits and
the common mode output voltage.
48
1 bit is necessary for this cancellation (OFFCAN). The cancellation request is managed externally to the cell. The request can be done
only when the reference voltage and the converter itself are already active (after startup). The cancellation is activated on the rising
edge of OFFCAN and the cancellation time is 50 s max. No specific timing is necessary for the relation between the clock edges and
OFFCAN edges. The value with offset cancellation is guaranteed for a fixed output range and a fixed common mode voltage. If the
output range or the common mode is changed, a new offset cancellation must be done to obtain this value.
49
The Vref voltage error is excluded in the calculation.
50
This is the variation of the gain, in the full temperature range, for one sample of the DAC, including the band gap reference voltage.
51
The Vref voltage error is excluded in the calculation. A variation of the reference results in a common mode voltage variation
according to this rule: Vcm/Vcm = Vref/Vref
52
See Figure 10.

Digital baseband controller Data sheet Electrical characteristics
DB3370 and DB3430



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Parameter Condition Min. Typ. Max. Unit
I/Q amplitude mismatch - -0.3 - +0.3 dB
I/Q phase mismatch - -1.5 - +1.5 Degrees
Startup time (PDDA from 1 to 0)
54
- - 250 s
Activation time
55
- 50 s
Sampling clock
56
51 52 53 MHz
Input data width Twos complement
56
10 10 10 bits
Input data rate (Sampling clock)
56
51 52 53 MHz

Table 25 VCMREG (3:0) and VCM OUT correspondence
VCMREG(3:0) 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 11XX
VCM OUT 1.15 1.175 1.2 1.225 1.25 1.275 1.3 1.325 1.35 1.375 1.4 1.425 1.45
Figure 10 illustrates the output load configuration.

Figure 10 Output load configuration
11.7.3 General purpose ADC
Vendor reference: TL01_Converters

53
The impedance is between the two outputs of each converter. The circuit outputs are in high impedance versus the power supplies.
54
Measured from the time that the power down is released to the time when the converter is within the specification (the startup of the
reference is assumed to be already finished)
55
Measured from the time that the power down is released to the time when the converter is functional (startup of the reference
finished).
56
The clock must be present before the power down is released.
Rdiff
Csp
Csm
OP(I, Q)Q
OM(I, Q)Q
Cdiff

Digital baseband controller Data sheet Electrical characteristics
DB3370 and DB3430



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Unless otherwise specified, the minimum and maximum values are given for the process
worst cases, that is the full junction temperature range (-30C to 125C) and the full
supply voltage range (V
DDA
from 2.35 V to 2.65 V), and the typical values are specified at
typical V
DDA
and temperature.
The conditions are as defined in Section 11.2, unless otherwise specified.
Table 26 General purpose ADC specification
Parameter Condition Min. Typ. Max. Unit
V
DDA
- 2.35 2.5 2.65 V
V
DDA
current In active mode
57
- - 0.7 mA
V
DDA
leakage current In power down, max.
at 105C
- 0.2 5 A
Junction temperature t
junc
-30 125 C
Resolution - 10 10 10 bits
Minimum full-scale input range All errors included
(also reference
variations)
- - 1.2 V
Maximum full-scale input range All errors included,
(also reference
variations)
58

2.35 - - -
Programmable full-scale range step 10-step regulation
59
- 200 - mV
Integral Non-linearity (INL) - -1 - +1 LSB
Differential Non-linearity (DNL) - -0.8 - +0.8 LSB
Offset error - -10 - +10 LSB
Conversion gain variation All errors included
60
-10 - +10 %
Conversion gain temperature sensitivity - -0.0025 - 0.0025 dB/C
Conversion gain temperature sensitivity
variation between devices. Reference
included.
Calibration
temperature = 30C
(junction temp.)
61

-0.7 - 0.7 %

57
Mean consumption during conversion time (15 s)
58
The specification is fulfilled for input voltages below 2.35 V. No voltages above 2.35 V are present at the ADC input.
59
The step resolution for the converter, excluding the reference variations, is 1 LSB according to the desired input
ranges.
60
The gain variations are because of the reference variations (both with process and temperature) plus non-idealities inside the
converter itself. The selectable input ranges can be calculated for these gain errors as illustrated in Table 27 A 4-bit selection code is
needed to choose the range in order to fulfill the worst case requirement in Table 26 for the full-scale input range (max. FSRMin and
min. FSRMax) with 0.2 V nominal step resolution. Margins A = 0.2 V and B = 0.45 V are needed on Nom FSRMin and Nom FSRMax, as
illustrated in Figure 11.
61
Conversion gain temperature sensitivity requirements limit the slope near 30C. The nominal characteristic of gain temperature
sensitivity is a second order polynomial of the type Y = mX2 + nX + p with a minimum at 30C and with m = 3.5897 10
-7
,
n = -1.985 10
-5
, p = 0.99629. Figure 12 defines the possible area of variation with temperature of the gain characteristics with
different devices, assuming that these characteristics are normalized to the typical reference value at 30C.

Digital baseband controller Data sheet Electrical characteristics
DB3370 and DB3430



1424-LZN 901 2501/1 Uen Rev G 2010-11-02

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Parameter Condition Min. Typ. Max. Unit
Input capacitance, switched capacitor
during sampling
62
- - 5 pF
Input capacitance, total excluding
switched capacitor
62
- - 5 pF
Input leakage current
62
-20 - +20 nA
Equivalent input resistance
62
5 - - M
Output data width Binary
63
- 10 - bits
Table 27 shows the input ranges selection, starting at 1 V with nominal 0.2 V step
resolution and with regards to the worst gain errors.
Table 27 Input ranges selection
Nominal input range Selection code Worst gain error
+10%
Worst gain error
-10%
Equivalent input range
0 to 1.0 V 0000 0 to 0.90 V 0 to 1.10 V
0 to 1.2 V 0001 0 to 1.08 V 0 to 1.32 V
0 to 1.4 V 0010 0 to 1.26 V 0 to 1.54 V
0 to 1.6 V 0011 0 to 1.44 V 0 to 1.76 V
0 to 1.8 V 0100 0 to 1.62 V 0 to 1.98 V
0 to 2.0 V 0101 0 to 1.80 V 0 to 2.20 V
0 to 2.2 V 0110 0 to 1.98 V 0 to 2.42 V
0 to 2.4 V 0111 0 to 2.16 V 0 to 2.64 V
0 to 2.6 V 1000 0 to 2.34 V 0 to 2.86 V
0 to 2.8 V 1001 0 to 2.52 V 0 to 3.08 V
0 to 2.8 V 1010 1111 0 to 2.52 V 0 to 3.08 V

62
See Figure 14 for the input equivalent circuit. When the sampling switch is open, the input resistance is RTOT, which is much higher
than the minimum 5 M value of the specification. During sampling, the 5 pF switched capacitor can be seen as an equivalent
resistance RSW in parallel with RTOT (RSW // RTOT > 5 M). The equivalent input resistance affects the input signal value of a quantity
depending on the source equivalent resistance. CTOT is the total parasitic capacitance at the input pad. ILEAK is the leakage current of
the junctions and of the protections connected to the pad plus the subthreshold current of the sampling switch when opened.
63
The value of the output data GPADD (9:0) is undetermined from the time that the supply voltage is applied to the first conversion
result.

Digital baseband controller Data sheet Electrical characteristics
DB3370 and DB3430



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Figure 11 illustrates the specification of the programmable full-scale range of the GP
ADC.
FSR
Max
FSR
Min
Max FSR
Min
Min FSR
Max
Guaranteed FSR
Nom FSR
Max
Nom FSR
Min
A B
FSR (V)

Figure 11 Specification of the programmable full-scale range of the GP ADC
Figure 12 illustrates the nominal conversion gain variation with temperature characteristic
(bold black line) and the permitted area of variation with different devices (red dashed
region).

Figure 12 Nominal conversion gain variation and permitted area of variation with different devices

C
o
n
v
e
r
s
i
o
n

g
a
i
n

+125C
Slope = +0.0025 dB/C Slope = -0.0025 dB/C
-30C +30C
(0.99602)
(Y1)
(Y2)
(Y1 + 0.7%)
(Y1 - 0.7%)
(Y2 + 0.7%)
(Y2 - 0.7%)
Nominal curve: Y = 3.5897 10
-7
X
2
- 1.985 10
-5
X + 0.99629
Temperature
Different devices within specification Nominal characteristic

Digital baseband controller Data sheet Electrical characteristics
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Figure 13 illustrates the equivalent input circuit for the GP ADC.

Figure 13 Equivalent input circuit for the GP ADC
11.7.4 Band gap reference voltage generator and central bias current generator
Vendor reference: TL01_Converters
Unless otherwise specified, the minimum and maximum values are given for the process
worst cases, that is the full junction temperature range (-30C to 125C) and the full
supply voltage range (V
DDA
from 2.35 V to 2.65 V), and the typical values are specified at
typical V
DDA
and temperature.
The conditions are as defined in Section 11.2, unless otherwise specified.
Table 28 Reference voltage and bias current generators specification
Parameter Condition Min. Typ. Max. Unit
V
DDA
- 2.35 2.5 2.65 V
V
DDA
current In active mode - 0.9 1.3 mA
V
DDA
leakage current In power down, CK
steady max. at 105C
- 0.1 3 A
Junction temperature t
junc
-30 - 125 C
Reference voltage value At 27C
64
0.94 1 1.06 V
Reference variation with temperature - - - 1.35%
Temperature coefficient, see Figure 14
65
-160 - +160 Ppm/C
Startup time (PDCOMMON from 1 to 0) - - - 500 s
Activation time
66
- 50 - s

64
This precision can be obtained with a sampled differential band gap without trimming and external components. The reference value
is almost independent of the power supply level.
65
Figure 14 illustrates the reference voltage temperature coefficient. The reference voltage variation with temperature has a parabola-
like behavior. The inclination of the parabola can change. The Vmax and Vmin are the maximum and minimum value voltage points of the
parabola. These points define the temperature value points TVmax and TVmin. Vref is the nominal reference voltage.
ILEAK
CTOT CSW RSW
Input pad
Sampling switch
RTOT

Digital baseband controller Data sheet Electrical characteristics
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Figure 14 illustrates the temperature coefficient definition for the reference voltage.

Figure 14 Temperature coefficient definition for the reference voltage
11.8 Random noise generator
Vendor reference: t1xp_rng_65lp_top_ana_SNPS-AVT-CDS
The conditions are as defined in Section 11.2, unless otherwise specified.
Table 29 Random noise generator characteristics
Symbol Parameter Condition Min. Typ. Max. Unit
V
DD
Supply voltage core interface - 1.12 1.20 1.30 V
I
DD
Current consumption norm operation V
DD
- - 20 A
I
DDQ
Current consumption power down V
DD
- - 1 A
SR Sampling rate - 27 - 48 MHz
N Sequence length for equiprobability test - - - 1000 bits
t
ST
Startup time - - - 1 s
F
T1
Voltage-controlled Oscillator (VCO)
frequency in test mode 1
- - 20 - MHz
F
T2
VCO frequency in test mode 2 - - 30 - MHz
F
T3
VCO frequency in test mode 3 - - 40 - MHz

66
Measured from the time that the power down is released to the time when the band gap is functional.
Vmax

Vmin

V
T/

C
Vrefmax

Vrefmin

TVmin

TVmax

min max
min max
1
. .
V V ref
T T
V V
V
coeff Temp

Digital baseband controller Data sheet Electrical characteristics
DB3370 and DB3430



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11.9 IO cell requirements
The load and maximum operating frequency of the IOs are defined in Reference [6].
11.10 Operation modes
To reduce the power consumption, the device can operate in two main modes: Active and
Idle. In each of these modes, various sub modes are defined depending on the clock
gating. In Table 30, the maximum clock frequency is defined for the subsystems and the
main modes of operation.
Table 30 Operation modes
Mode name Core
voltage [V]
Access mode
name
Application
mode name
Fast 1.2 Active Active
- 1.2 Active Low Power
- 1.2 Sleep Active
Low Power 1.2 Sleep Low Power
Idle 1.05 Sleep Low Power
11.10.1 Clock frequencies
In the tables in Subsections 11.10.1.1 and 11.10.1.2, Active mode means 1.2 V core
supply and Idle mode means 1.05 V core supply.
11.10.1.1 Application subsystem
Table 31 specifies the Application subsystem clock frequencies.
Table 31 Application subsystem clock frequencies
Block/System name Active Idle/Low Power Unit
ARM926 208 13 MHz
AHB matrix 52 6.5 MHz
Application EMIF
(SDRAM)
104 13 MHz
Application NFIF (Static) 104 6.5 MHz
MSL 52 6.5 MHz
DMA 52 6.5 MHz

Digital baseband controller Data sheet Electrical characteristics
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Block/System name Active Idle/Low Power Unit
XGAM 52 6.5 MHz
Peripherals 52/26/13 13 MHz
Video encoder 208 6.5 MHz
APEX 52 6.5 MHz
11.10.1.2 Access subsystem
Table 32 specifies the Access subsystem clock frequencies.
Table 32 Access subsystem clock frequencies
Block/System name Active Idle/Sleep Unit
ARM926 208 0 MHz
AHB matrix 52 0 MHz
EMIF 104 0 MHz
MSL 52 0
67
MHz
DMA 52 0 MHz
DSP 208 0 MHz
EGG 104/52/26 0 MHz
WCDMA 104/52/26 0 MHz
WDOG 26 and 32 32 kHz
Peripherals 26 and 48 0
67
MHz
11.11 Power-on sequence
The core V
DD
supply must be stable above 0.9 V, and the PWR_RST held low, for at least
1 s before VDD_AF ramps above 1.0 V. During power down, the reverse sequence must
be ensured. Violating these requirements may cause uncontrolled fusing in the on-chip
One Time Programmable Memory (OTP).

67
Some blocks must be able to wake up by asynchronous detection.

Digital baseband controller Data sheet Test modes
DB3370 and DB3430



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12 Test modes
12.1 Chip modes
The chip modes are defined by the EMU_MODE_1 and EMU_MODE_0 signals when the
TRST_N signal is deactivated. The default mode is Single Full Test Access Port (TAP)
Emulation mode.
Table 33 Chip mode selection
EMU_MODE_1 EMU_MODE_0 TRST_N Description
1 1 0 Mission mode
1 1 1 Single Full TAP Emulation mode
1 0 1 Single Application TAP Emulation mode
0 1 1 Dual TAP Emulation mode (DSP on a separate
multiplexed JTAG interface. The Multiplexer (MUX) is
controlled by the System Controller (SYSCON))
0 0 1 Production TEST mode
- Boundary Scan (BS)
- MBIST
- SCAN
- IDDQ
- Analog cell test
- Fuse mode
- HIGHZ
Table 34 TAP configuration
EMU_MODE_1 EMU_MODE_0 Comment
1 1 JTAG IO CHIP TAP DSP TAP Access ARM TAP
Application ARM TAP JTAG IO
1 0 JTAG IO Application ARM TAP JTAG IO
0 1 JTAG IO Access ARM TAP Application ARM TAP JTAG IO
+
Multiplexed JTAG IO DSP TAP Multiplexed JTAG IO
0 0 JTAG IO CHIP TAP JTAG IO

Digital baseband controller Data sheet Test modes
DB3370 and DB3430



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12.2 Production test mode
The Test mode can be used during PCB test BS to get the highest possible speed.
Table 35 defines the primary Join Test Action Group (JTAG) chain in Test mode.
Table 35 Primary JTAG chain in Production Test mode
TAP Comment IR size BS size
Chip Digital baseband controller TAP 5 801
12.3 JTAG emulation mode
Table 36 defines the JTAG chains in Emulation mode.
Table 36 JTAG Emulation mode
TAP Comment IR size BS size Order
Chip Digital baseband controller TAP 5 801 1
DSP DSP CEVA-X 1620 TAP 32 - 2
CPU CPU ARM926 Access TAP 4 - 3
CPU CPU ARM926 Application TAP 4 - 4
Table 37 TAP ID register
Bit Comment
31-28 Version
27-12 Part number
11-1 Manufacturer ID
0 Always high

Digital baseband controller Data sheet Definitions
DB3370 and DB3430



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13 Definitions
13.1 Jitter
13.1.1 Sigma
The sigma value is based on the requested up-time and the Bit Error Rate (BER).
13.2 Duty cycle
If nothing else is specified, the duty cycle is defined as positive.
The duty cycle is defined at 50% of the supply.
13.3 Timing
13.3.1 Rise and fall time
If nothing else is specified, the rise and fall time is defined as 20-80% of the supply.
13.3.2 Other timing
If nothing else is defined, timing is defined at 50% of the supply.


Digital baseband controller Data sheet Glossary
DB3370 and DB3430



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Glossary
AAIF Application to Access
Interface
AC Alternating Current
ADC Analog to Digital Converter
AHB ARM High-Speed Bus
AMBA Advanced Microprocessor
Bus Architecture
APEX Audio Processing
Execution
APLL Analog Phase Locked Loop
ARM Advanced RISC Machine
BER Bit Error Rate
BIST Built-in Self Test
BS Boundary Scan
CAMISP Camera Integrated Signal
Processing
CDS Camera Data Synchronizer
CHIPCON Chip Controller
CK Clock
CKDA Clock D/A Converter
CMOS Complementary Metal
Oxide Semiconductor
CPU Central Processing Unit
CRC Cyclic Redundancy Check
CRU Code Replacement Unit
D/A Digital/Analog
DAC Digital to Analog Converter
DB Digital Baseband
DC Direct Current
DFT Design for Test
DMA Direct Memory Access
DMAC Direct Memory Access
Controller
DMUC Dynamic Memory Use
Counters
DNL Differential Non-linearity
DSP Digital Signal Processor
DSPSUB Digital Signal Processor
Subsystem
ECC Error Code Correction
EDC ST-Ericsson Discretix
Crypto Cell
EDGE Enhanced Data Rate for
GSM Evolution
EGG EDGE/GSM/GPRS
EMIF External Memory Interface
ESD Electrostatic Discharge
ETM Embedded Trace Macrocell
ETX Enable Transmission
FBGA Fine Pitch, Square Ball Grid
Array Package
FIFO First In First Out
FIQ Fast Interrupt Request
FIR Fast Infrared
FSM Finite State Machine
FSR Full-scale Range
GP General Purpose
GPADD General Purpose ADC Data

Digital baseband controller Data sheet Glossary
DB3370 and DB3430



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GPIO General Purpose
Input/Output
GPRS General Packet Radio
Services
GSM Global System for Mobile
communication
HSDPA High-speed Downlink
Packet Access
HSUPA High-speed Uplink Packet
Access
I&D Instruction and Data
I/Q In-phase Signal/Quadrature
Phase Signal
I
2
C Inter-integrated Circuit
I
2
CIF I
2
C Interface
I
2
S Integrated Interchip Sound
IC Integrated Circuit
ICMV Input Common Mode
Voltage
ICU Interrupt Controller Unit
ID Identity
INL Integral Non-linearity
INTCON Interrupt Controller
IO Input, Output
IP Intellectual Property
IR Instruction Register
IRAM Internal Random Access
Memory
IrDA Infrared Data Association
IRQ Interrupt Request
JPEG JPEG file interchange
format
JTAG Join Test Action Group
KiB Kilo binary byte - A unit of
information or computer
storage, 1 KiB = 2
10
bytes =
1,024 bytes
LSB Least Significant Bit
LVDS Low Voltage Differential
Signal
MCLK Master Clock
ME Mobile Equipment
MemBIST Memory BIST
MiB Mega binary byte - A unit of
information or computer
storage, 1 MiB = 2
20
bytes
= 1,048,576 bytes
MIDI Music Industry Digital
Interface
MIR Medium Infrared
MLCK Master Clock
MMC Multimedia Memory Card
MMU Memory Management Unit
MSB Most Significant Bit
MSL Mobile Scalable Link
MUX Multiplexer
NAND flash Non-volatile flash memory
offering multimedia and
Internet capability
NFIF Flexible Static Memory
Controller Interface
NOR flash Non-volatile flash memory
for mobile and digital
applications
OS Operating System
OTG On-The-Go USB 2.0
OTP One Time Programmable
Memory
PCB Printed Circuit Board
PCM Pulse Code Modulation

Digital baseband controller Data sheet Glossary
DB3370 and DB3430



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PDAD ADC Power Down
PDN Power Down
PDROM Program Data Read Only
Memory
PHY Physical level software for
WCDMA
pin A pin is a part of a male
connector. The description
of the signal associated
with each pin in a
connector is called a
pinout.
PLL Phase-Locked Loop
PMT Parallel Multiplexed Test
PMU Power Management Unit
PoP Package on Package
PSR Power Supply Rejection
PVT Process, Voltage, and
Temperature
RAM Random Access Memory
RISC Reduced Instruction Set
Computer
RMS Root Mean Square
RNG Random Noise Generator
ROM Read-only Memory
RS232 Recommended standard
232. Serial interface
standard approved by EIA.
RTC Real-time Clock
SCP Single Chip Package
SD Secure Digital
SDIO Secure Digital Input/Output
SDR Single Data Rate
SDRAM Synchronous Dynamic
Random Access Memory
SE Single-ended
SEMIF Shared External Memory
Interface
SFDR Peak Harmonic or Spurious
Noise
SIG Special Interest Group
SIM Subscriber Identity Module
SIMIF Subscriber Identity Module
Interface
SINAD Signal-to-Noise and
Distortion ratio
SIR Slow Infrared
SMIA Standard Mobile Imaging
Architecture
SPI Serial Peripheral Interface
SRAM Static Random Access
Memory
SYSCLK System Clock
SYSCON System Controller
TAP Test Access Port
TCM Tightly Coupled Memory
TX Transceiver
UART Universal Asynchronous
Receiver/Transmitter
ULPI USB Low Pin Interface
USB Universal Serial Bus
VCO Voltage Controlled
Oscillator
VFBGA
Very Thin profile Fine pitch
Ball Grid Array
WCDMA Wideband Code-division
Multiple Access
WDOG Watchdog
XGAM Graphics Hardware
Subsystem
XTAL Crystal

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