CHAPTER 1 INTRODUCTION

An arithmetic logic unit (ALU) is a digital circuit that performs arithmetic and logical operations. The ALU is a fundamental building block of the central processing unit (CPU) of a computer, and even the simplest microprocessors contain one for purposes such as maintaining timers. The processors found inside modern CPUs and graphics processing units (GPUs) accommodate very powerful and very complex ALUs; a single component may contain a number of ALUs. Mathematician John von Neumann proposed the ALU concept in 1945, when he wrote a report on the foundations for a new computer called the EDVAC. Research into ALUs remains an important part of computer science, falling under Arithmetic and logic structures in the ACM Computing Classification System. An ALU must process numbers using the same format as the rest of the digital circuit. The format of modern processors is almost always the two's complement binary number representation. Early computers used a wide variety of number systems, including one's complement, sign-magnitude format, and even true decimal systems, with ten tubes per digit. ALUs for each one of these numeric systems had different designs, and that influenced the current preference for two's complement, as this is the representation that makes it easier for the ALUs to calculate additions and subtractions. The two's-complement number system allows for subtraction to be accomplished by adding the negative of a number in a very simple way which negates the need for specialized circuits to do subtraction.

1.1 Simple operations

Most ALUs can perform the following operations

Integer arithmetic operations (addition, subtraction, and sometimes multiplication and division, though this is more expensive)

Bitwise logic operations (AND, NOT, OR, XOR)

Bit-shifting operations (shifting or rotating a word by a specified number of bits to the left or right, with or without sign extension). Shifts can be interpreted as multiplications by 2 and divisions by 2.

1.2 Complex operations

An engineer can design an ALU to calculate any operation, however complicated it is; the problem is that the more complex the operation, the more expensive the ALU is, the more space it uses in the processor, and the more power it dissipates, etc. Therefore, engineers always calculate a compromise, to provide for the processor (or other circuits) an ALU powerful enough to make the processor fast, but yet not so complex as to become prohibitive. Imagine that you need to calculate the square root of a number; the digital engineer will examine the following options to implement this operation: 1. Design an extraordinarily complex ALU that calculates the square root of any number in a single step. This is called calculation in a single clock. 2. Design a very complex ALU that calculates the square root of any number in several steps. But the intermediate results go through a series of circuits that are arranged in a line, like a factory production line. That makes the ALU capable of accepting new numbers to calculate even before finished calculating the previous ones. That makes the ALU able to produce numbers as fast as a single-clock ALU, although the results start to flow out of the ALU only after an initial delay. This is called calculation pipeline. 3. Design a complex ALU that calculates the square root through several steps. This is called interactive calculation, and usually relies on control from a complex control unit with built-in microcode. 4. Design a simple ALU in the processor, and sell a separate specialized and costly processor that the customer can install just beside this one, and implements one of the options above. This is called the co-processor. 5. Tell the programmers that there is no co-processor and there is no emulation, so they will have to write their own algorithms to calculate square roots by software. This is performed by software libraries.

6.

Emulate the existence of the co-processor, that is, whenever a program attempts to perform the square root calculation, make the processor check if there is a coprocessor present and use it if there is one; if there isn't one, interrupt the processing of the program and invoke the operating system to perform the square root calculation through some software algorithm. This is called software emulation. The options above go from the fastest and most expensive one to the slowest and

least expensive one. Therefore, while even the simplest computer can calculate the most complicated formula, the simplest computers will usually take a long time doing that because of the several steps for calculating the formula. Powerful processors like the Intel Core and AMD64 implement option #1 for several simple operations, #2 for the most common complex operations and #3 for the extremely complex operations. That is possible by the ability of building very complex ALUs in these processors.

1.3 Inputs and outputs

The inputs to the ALU are the data to be operated on (called operands) and a code from the control unit indicating which operation to perform. Its output is the result of the computation. In many designs the ALU also takes or generates as inputs or outputs a set of condition codes from or to a status register. These codes are used to indicate cases such as carry-in or carry-out, overflow, divide-by-zero, etc.

CHAPTER 2 LITERATURE SERVEY

2.1 Introduction
Logic gates process signals which represent true or false. Normally the positive supply voltage +Vs represent true and 0V represents false. Other terms which are used for the true and false states are shown in the table on the right. It is best to be familiar with them all.

Logic states True

1 High +Vs On

False
0 Low 0V Off

Table 2.1 Logic States Gates are identified by their function: NOT, AND, NAND, OR, NOR, EX-OR and EX-NOR. Capital letters are normally used to make it clear that the term refers to a logic gate. Note that logic gates are not always required because simple logic functions can be performed with switches or diodes:

Switches in series (AND function) Switches in parallel (OR function) Combining IC outputs with diodes (OR function)

Logic gate symbols There are two series of symbols for logic gates:

The traditional symbols have distinctive shapes making them easy to recognize so they are widely used in industry and education.

The IEC (International Electro technical Commission) symbols are rectangles with a symbol inside to show the gate function. They are rarely used despite their official status, but you may need to know them for an examination.

Inputs and outputs Gates have two or more inputs, except a NOT gate which has only one input. All gates have only one output. Usually the letters A, B, C and so on are used to label inputs, and Q is used to label the output. On this page the inputs are shown on the left and the output on the right. The inverting circle (o) Some gate symbols have a circle on their output which means that their function includes inverting of the output. It is equivalent to feeding the output through a NOT

gate. For example the NAND (Not AND) gate symbol shown on the right is the same as an AND gate symbol but with the addition of an inverting circle on the output. Truth tables A truth table is a good way to show the function of a logic gate. It shows the output states for every possible combination of input states. The symbols 0 (false) and 1 (true) are usually used in truth tables. For example below truth table shows the inputs and output of an AND gate. Input A 0 0 1 1 Input B 0 1 0 1 Output Q 0 0 0 1

Logic ICs Logic gates are available on special ICs (chips) which usually contain several gates of the same type, for example the 4001 IC contains four 2-input NOR gates. There are several families of logic ICs and they can be split into two groups

4000 Series 74 Series

NOT gate (inverter) The output Q is true when the input A is NOT true; the output is the inverse of the input Q = NOT A A NOT gate can only have one input. A NOT gate is also called an inverter.

Input A 0 1

Output Q 1 0

Traditional symbol

IEC symbol

Truth Table

AND gate The output Q is true if input A AND input B are both true: Q = A AND B An AND gate can have two or more inputs, its output is true if all inputs are true.

Inpu tA 0 0 1 1

Inpu tB 0 1 0 1

Outpu tQ 0 0 0 1

Traditional symbol

IEC symbol

Truth Table

NAND gate (NAND = Not AND) This is an AND gate with the output inverted, as shown by the 'o' on the output. The output is true if input A AND input B are NOT both true: Q = NOT (A AND B) A NAND gate can have two or more inputs, its output is true if NOT all inputs are true.

Inpu tA 0 0 1 1

Inpu tB 0 1 0 1

Outpu tQ 1 1 1 0

Traditional symbol

IEC symbol

Truth Table

OR gate The output Q is true if input A OR input B is true (or both of them are true) Q = A OR B An OR gate can have two or more inputs, its output is true if at least one input is true.

Inpu tA 0 0 1 1

Inpu tB 0 1 0 1

Outpu tQ 0 1 1 1

Traditional symbol
.

IEC symbol

Truth Table

NOR gate (NOR = Not OR) This is an OR gate with the output inverted, as shown by the 'o' on the output. The output Q is true if NOT inputs A OR B is true Q = NOT (A OR B) A NOR gate can have two or more inputs; its output is true if no inputs are true.

Input A 0 0 1 1

Input B 0 1 0 1

Outp ut Q 1 0 0 0

Traditional symbol

IEC symbol

Truth Table

EX-OR (EXCLUSIVE-OR) Gate The output Q is true if either input A is true OR input B is true, but not when both of them are true: Q = (A AND NOT B) OR (B AND NOT A) this is like an OR gate but excluding both inputs being true. The output is true if inputs A and B are DIFFERENT. EX-OR gates can only have 2 inputs.

Input A 0 0 1 1

Input B 0 1 0 1

Output Q 0 1 1 0

Traditional symbol

IEC symbol

Truth Table

EX-NOR (EXCLUSIVE-NOR) Gate This is an EX-OR gate with the output inverted, as shown by the 'o' on the output. The output Q is true if inputs A and B are the SAME (both true and both false) Q = (A AND B) OR (NOT A AND NOT B) EX-NOR gates can only have 2 inputs.

Input A 0 0 1 1

Input B 0 1 0 1

Output Q 1 0 0 1

Traditional symbol

IEC symbol

Truth Table

SUMMARY TRUTH TABLES The summary truth tables below show the output states for all types of 2-input and 3-input gates.
Summary for all 2-input gates Input Output of each gate E X N O R 1 0 0 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 A B C Summary for all 3-input gates Inputs Output of each gate N A N D O R

A A B N D

N A N D O R

E N O R X O R

A N D

N O R

0 0 1 1

0 1 0 1

0 0 0 1

1 1 1 0

0 1 1 1

1 0 0 0

0 1 1 0

CHAPTER 3 FUNCTION OF ALU

3.1 ARITHEMATIC LOGIC UNIT
The first entity described is the ALU. This entity performs a number of arithmetic or logical operations on one or more input busses. A symbol for the ALU is shown in Fig.1

Acc

data

Opcode

out put

ALU
out Fig3.1 ALU out

The arithmetic-logic unit (ALU) performs all arithmetic operations (addition, subtraction, multiplication, division) and logic operations. Logic operations test various conditions encountered during processing and allow for different actions to be taken based on the results. The data required to perform the arithmetic and logical functions are input from the designated CPU registers and operands. The ALU relies on basic items to perform its operations. These include number systems, data routing circuits (adders/subtracters) timing, instructions, operands, and registers.

S 0 0

S 1 0

S 2 0

S 3 0 R S T

Operation

RESET Accumulator to 0

L D A

Load Accumulator from Data Memory

S T O

Store from Accumulator to Data Memory

A D D

Add Input Data to Accumulator

S U B

Subtract Input Data from Accumulator

A N D

Logical AND Input Data with Accumulator

O R

Logical OR Input Data with Accumulator

N O T

Logical NOT Accumulator

S H L

Shift Accumulator Left (up)

S H R

Shift Accumulator Right (down)

1 1 1 1

0 0 1 1

1 1 0 0

0 1 0 1 I N C

NOP NOP NOP Increment Accumulator

D E C

Decrement Accumulator

S E T

SET Accumulator to 1

Table 3.1 Operations of ALU The Logic Unit is a sequential unit with a single Accumulator, in which to store intermediate data. The Logic Unit has an single 8-bit data input port, and a single 8-bit data output port.

CHAPTER-4 RESULTS AND DISCUSSIONS

When the table is complete, your project properties will look like the following:

Fig 4.1: Select the device familys according to the device Click Next to proceed to the Create New Source window in the New Project Wizard. At the end of the next section, your new project will be complete. Create an HDL Source In this section, you will create the top-level HDL file for your design. Determine the language that you wish to use for the tutorial. Then, continue either to the Creating a VHDL Source section below, or skip to the Creating a Verilog Source section. Creating a VHDL Source Create a VHDL source file for the project as follows: 1. Click the New Source button in the New Project Wizard. 2. Select VHDL Module as the source type.

3. Type in the file name counter. 4. Verify that the Add to project checkbox is selected. 5. Click Next. 6. Declare the ports for the counter design by filling in the port below: information as shown

Fig 4.2 Define The Model Click Next, and then Finish in the New Source Wizard - Summary dialog box to complete the new source file template. Click Next, then Next, then Finish. The source file containing the entity/architecture pair displays in the Workspace, and the counter displays in the Source tab, as shown below:

Fig 4.3 New project in ISE Using Language Templates (VHDL) The next step in creating the new source is to add the behavioral description for the counter. To do this you will use a simple counter code example from the ISE Language Templates and customize it for the counter design. 1. 2. Place the cursor just below the begin statement within the counter architecture. Open the Language Templates by selecting Edit Language Templates

Note: You can tile the Language Templates and the counter file by selecting window Tile

Vertically to make them both visible. 3. Using the + symbol, browse to the following code example: VHDL Synthesis Constructs Coding Examples Counters Binary

Up/Down Counters Simple Counter 1. With Simple Counter selected, select Edit Use in File, or select the Use Template in the File toolbar button. This step copies the template into the counter source file.

5. Close the Language Templates. Final Editing of the VHDL Source 1. Add the following signal declaration to handle the feedback of the counter output below the architecture declaration and above the first begin statement: signal count_int : std_logic_vector(3 downto 0) :"0000"; 2. Customize the source file for the counter design by replacing the port and signal name placeholders with the actual ones as follows: replace all occurrences of <clock> with CLOCK replace all occurrences of <count_direction> with DIRECTION replace all occurrences of <count> with count_int

3. Add the following line below the end process; statement: COUNT_OUT <= count_int; 4. Save the file by selecting File Save. When you are finished, the counter source file will look like the following: Library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; -- Uncomment the following library declaration if instantiating -- any Xilinx primitive in this code. --library UNISIM; --use UNISIM.VComponents.all; entity counter is

Port (CLOCK : in STD_LOGIC; DIRECTION : in STD_LOGIC; COUNT_OUT : out STD_LOGIC_VECTOR (3 downto 0); end counter; architecture Behavioral of counter is signal count_int : std_logic_vector(3 downto 0) := "0000"; begin process (CLOCK) begin if CLOCK='1' and CLOCK'event then if DIRECTION='1' then count_int <= count_int + 1; else count_int <= count_int - 1; end if; end process; COUNT_OUT <= count_int; end Behavioral;

You have now created the VHDL source for the tutorial project. Skip past the Verilog sections below, and proceed to the Checking the Syntax of the New Counter Modulesection.

4.1 Checking the Syntax of the New Counter Module

When the source files are complete, check the syntax of the design to find errors and types. 1. Verify that Synthesis/Implementation is selected from the dropdown list in the Sources window. 2. Select the counter design source in the Sources window to display the related processes in the Processes window. 3. Click the + next to the Synthesize-XST process to expand the process group. 4. Double-click the Check Syntax process.

Note: You must correct any errors found in your source files. You can check for errors in the Console tab of the Transcript window. If you continue without valid syntax, you will not be able to simulate or synthesize your design. 5. Close the HDL file.

4.2 Design Simulation

4.2.1 Verifying Functionality using Behavioral Simulation Create a test bench waveform containing input stimulus you can use to verify the functionality of the counter module. The test bench waveform is a graphical view of a test bench. Create the test bench waveform as follows: 1. 2. 3. Select the counter HDL file in the Sources window. Create a new test bench source by selecting Project New Source.

In the New Source Wizard, select Test Bench Waveform as the source type, and type counter_tbw in the File Name field.

4.

Click Next.

5.

The Associated Source page shows that you are associating the test bench waveform with the source file counter. Click Next.

6.

The Summary page shows that the source will be added to the project, and it displays the source directory, type and name. Click Finish.

7.

You need to set the clock frequency, setup time and output delay times in the Initialize

Timing dialog box before the test bench waveform editing window opens. The requirements for this design are the following: The counter must operate correctly with an input clock frequency = 25 MHz The DIRECTION input will be valid 10 ns before the rising edge of CLOCK. The output (COUNT_OUT) must be valid 10 ns after the rising edge of

CLOCK. The design requirements correspond with the values below. Fill in the fields in the Initialize Timing dialog box with the following information: Clock High Time: 20 ns. Clock Low Time: 20 ns. Input Setup Time: 10 ns. Output Valid Delay: 10 ns. Offset: 0 ns. Global Signals: GSR (FPGA)

Note: When GSR(FPGA) is enabled, 100 ns. is added to the Offset value automatically. Initial Length of Test Bench: 1500 ns.

Leave the default values in the remaining fields.

Fig 4.4 Initializing Timing

8. Click Finish to complete the timing initialization. 9. The blue shaded areas that precede the rising edge of the CLOCK correspond to the Input Setup Time in the Initialize Timing dialog box. Toggle the DIRECTION port to define the input stimulus for the counter design as follows: Click on the blue cell at approximately the 300 ns to assert DIRECTION high so that the counter will count up. Click on the blue cell at approximately the 900 ns to assert DIRECTION low so that the counter will count down.

Fig 4.5 Test Bench Waveforms 10. Save the waveform. 11. In the Sources window, select the Behavioral Simulation view to see that the test bench waveform file is automatically added to your project.

Fig 4.6 Behavior Simulation 12. Close the test bench waveform. Simulating Design Functionality Verify that the counter design functions as you expect by performing behavior simulation as follows: 1. Verify that Behavioral Simulation and counter_tbw are selected in the source window. In the Process 2. In the Processes tab, click the + to expand the Xilinx ISE Simulator process and double-click the Simulate Behavioral Model process. The ISE Simulator opens and runs the simulation to the end of the test bench.

3.

To view your simulation results, select the Simulation tab and zoom in on the transitions.

The simulation waveform results will look like the following:

Fig 4.7 Simulation Results

Note: You can ignore any rows that start with TX. 4. Verify that the counter is counting up and down as expected. 5. Close the simulation view. If you are prompted with the following message,You have an active simulation open. Are you sure you want to close it?, click Yes to continue. You have now completed simulation of your design using the ISE Simulator.

4.3 Implement Design and Verify Constraints

Implement the design and verify that it meets the timing constraints specified in the previous section. 4.3.1 Implementing the Design 1. Select the counter source file in the Sources window. 2. Open the Design Summary by double-clicking the View Design Summary process In the Processes tab. 3. Double-click the Implement Design process in the Processes tab.

4. Notice that after Implementation is complete, the Implementation processes have a green check mark next to them indicating that they completed successfully without Errors or Warnings.

Fig4.8 Post implementation Design summary 5. Locate the Performance Summary table near the bottom of the design Summary. 6. Click the All Constraints Met link in the Timing Constraints field to view the Timing
Constraints report. Verify that the design meets the specified timing requirements.

4.4 Assigning Pin Location Constraints

Specify the pin locations for the ports of the design so that they are connected correctly on the Spartan-3 Startup Kit demo board. To constrain the design ports to package pins, do the following:
1. Verify that counter is selected in the Sources window. 2. Double-click the Assign Package Pins process found in the User constraints process group. The Xilinx Pinout and Area Constraints Editor (PACE) opens. 3. Select the Package View tab.

4. In the Design Object List window, enter a pin location for each pin in the Loc column using the following information:

CLOCK input port connects to FPGA pin T9 (GCK0 signal on board) COUNT_OUT<0> output port connects to FPGA pin K12 (LD0 signal on board) COUNT_OUT<1> output port connects to FPGA pin P14 (LD1 signal on board) COUNT_OUT<2> output port connects to FPGA pin L12 (LD2 signal on board) COUNT_OUT<3> output port connects to FPGA pin N14 (LD3 signal on board) DIRECTION input port connects to FPGA pin K13 (SW7 signal on board)

Notice that the assigned pin locations are shown in blue:

Fig4.9 Package pin location 5. Select File Save. You are prompted to select the bus delimiter type based on the synthesis tool you are using. Select XST Default <> and click OK.

6. Close PACE. Notice that the Implement Design processes have an orange question mark next to them, indicating they are out-of-date with one or more of the design files. This is because the UCF file has been modified.

4.5 Download Design to the Spartan-3 Demo Board

This is the last step in the design verification process. This section provides simple instructions for downloading the counter design to the Spartan-3 Starter Kit demo board. 1. Connect the 5V DC power cable to the power input on the demo board(J4). 2. Connect the download cable between the PC and demo board(J7). 3. Select Synthesis/Implementation from the drop-down list in the Sources window. 4. Select counter in the Sources window. 5. In the Processes window, click the + sign to expand the Generate Programming File processes. 6. Double-click the Configure Device (iMPACT) process. 7. The Xilinx WebTalk Dialog box may open during this process. Click Decline. 8. Select Disable the collection of device usage statistics for this project only and click OK. iMPACT opens and the Configure Devices dialog box is displ

Fig 4.10 Impact Welcome Dialog Box

9.

In the Welcome dialog box, select Configure devices using Boundary-Scan (JTAG).

10. Verify that Automatically connect to a cable and identify Boundary-Scan chain is selected. 11. Click Finish. 12. If you get a message saying that there are two devices found, click OK to continue. The devices connected to the JTAG chain on the board will be detected and displayed in the iMPACT window. 13. The Assign New Configuration File dialog box appears. To assign a configuration file to the xc3s200 device in the JTAG chain, select the counter. bit file and click Open.

Fig 4.11 Bit file add to the FPGA 14. If you get a Warning message, click OK. 15. Select Bypass to skip any remaining devices. 16. Right-click on the xc3s200 device image, and select Program. The Programming Properties dialog box opens.

17. Click OK to program the device

Fig 4.12 program is successfully dumped on FPGA

When programming is complete, the Program Succeeded message is displayed. On the board, LEDs 0, 1, 2, and 3 are lit, indicating that the counter is running.

CONCLUSION

The ALU design has been implemented on Xilinx Spartan 3E FPGA. The IP Core is developed using the Xilinx 9.1i. The simulation is done using ISE Simulator.

FUTURE SCOPE
The design which was designed is for 8-bits. This can be extended to 16 bit and 32 bit further.

APPENDIX
INTRODUCTION TO VHDL:
VHDL is a language that is used to describe the behavior of digital circuit designs Very High Speed Integrated Circuit Hardware Description Language

VHDL designs can be simulated and translated into a form suitable for hardware implementation Hierarchical use of VHDL designs permits the rapid creation of complex digital circuit designs

Entities , Architecture And Configurations

VHDL Program Structure Primary Design Unit Model Structure Entity Declaration Architecture

Each VHDL design unit comprises an entity declaration and one or more architectures. Each architecture defines a different implementation or model of a given design unit. The entity definition defines the inputs to , and out puts from the module. Entity Declaration Format: Entity entity_ name is Port(port definition list); End entity _name; Port declaration format: Port name : mode signal_type; The mode of a port defines the directions of the signals, and is one of in,out,inout.

Port Modes : An in port can be read but not updated within the modes carrying information out of the module . An out port can be updated but not read within the carring information out of the module. An inout port is bidirectional and can be both read and updated. Entity_Name: It is identifier selected by the user to name the entity. Port_Name: It is a list of user selected identifier to name external interface signals. Example : entity and _gate is port ( a , b: in bit; c : out bit ) ; end and_gate ; Architecture : An architecture defines one particular implementation of a design unit , at some desired level of abstraction. It specifies behavior , functionality , inter connections or relationship between inputs and outputs . An architecture body using format: architecture arch _name of entity_ name is .Declarations begin concurrent statements end arch _name ;

Declarations include data types, constants, files, components, attributes, subprograms and other information to be used in the implementation describes . concurrent statements describe a desired unit at one or more levels of modeling.An architecture body using any of following modeling styles specifies the internal details of an entity. As a set of concurrent assignments statements o represent Dataflow As a set of interconnected components to represent Structure As a set of sequential assignments statements to represent Behavioral

MODELLING STYLES : Three different modeling styles of architecture bodies. Behavioural Structural Data flow

Structural Design: In this we use components . It has two steps, one is component declaration and the other is component instantiation Architecture STRUCT of <identifier_name> is Component component_name Port( port_name : mode signal_type; ..; ..); End component_name; Begin Component_label : component_name port map (list); End STRUCT;

Example: Architecture gate of or_gate is Component or_gate Port(x,y : in bit; Z:out bit); End component; Begin U1: or gate port map(a, b, c); End gate; The declared components are instantiated in architecture body using component instantiation stage. U1 is a component label for this component instantiation. x is connected to signal a y is connected to signal b z is connected to signal c in or gate port map. The signals in the port map of a component instantiation and the port signals in the component declaration are associated by position. DATA FLOW MODEL: Syntax : Architecture DATAFLOW of <identifier_name> is Begin Concurrent statements; .; .; End DATAFLOW;

A simple concurrent statement is written as Target signal <= expression; Example: Architecture gate of or gate is Begin C<= a or b; End gate;

BEHAVIOUR MODEL: The behavioral style of modeling specifies behavior of an entity as a set of statements that are executed sequentially in a specified order. The key mechanism used to model the behavior of the entity is, a process statement. Syntax: Architecture BEHV of <identifier_name> is Begin Process (sensitivity list) Begin Sequential statements ; ; ; End process; End BEHV;

Example:

Architecture gate of or_gate is Begin Process(a,b) Begin C<=a or b; End process; End gate;

Sequential Statements: Sequential statements are used to define algorithms to express the behavior of a design. The sequential statements execute one after another as per writing order. They must be placed inside a process statement.

Conditional Statements: IF statement : Syntax: If condition1 then sequential statements.. Elsif condition2 then sequential statements.. Else sequential statements.. End if;

Introduction to XILINX 9.1i:

The ISE 9.1i provides Xilinx PLD designers with the basic design process using ISE 9.1i. In this chapter you will understande of how to create, verify, and implement a design. This chapter contains the following sections: Getting Started Create a New Project Create an HDL Source Design Simulation Create Timing Constraints Implement Design and Verify Constraints Reimplement Design and Verify Pin Locations Download Design to the Spartan-3 Demo Board

Getting Started: Software Requirements:- ISE 9.1i Hardware Requirements:- Spartan-3 Startup Kit, containing the Spartan-3 Startup Kit Demo Board. Starting the ISE Software To start ISE, double-click the desktop icon,

(OR) Start ISE From The Start Menu By Selecting: Start All Programs Xilinx ISE 9.1i Project Navigator

Note: Your start-up path is set during the installation process and may differ from the one above.Accessing Help At any time during the tutorial, you can access online help for additional information about the ISE software and related tools. To open Help, do either of the following: Press F1 to view Help for the specific tool or function that you have selected orhighlighted. Launch the ISE Help Contents from the Help menu. It contains information about creating and maintaining your complete design flow in ISE.

Fig 3.1 : ISE Help Topic

1. Select File Create a New Project Create a new ISE project which will target the FPGA device on the Spartan-3 Startup Kit demo board. To create a new project: New Project... The New Project Wizard appears. 2. Type tutorial in the Project Name field. 3. Enter or browse to a location (directory path) for the new project. A tutorial subdirectory is created automatically. 4. Verify that HDL is selected from the Top-Level Source Type list. 5. Click Next to move to the device properties page

6. Fill in the properties in the table as shown below: Product Category: All Family: Spartan3 Device: XC3S200 Package: FT256 Speed Grade: -4 Top-Level Source Type: HDL Synthesis Tool: XST (VHDL/Verilog) Simulator: ISE Simulator (VHDL/Verilog) Preferred Language: VHDL (or Verilog) Verify that Enable Enhanced Design Summary is selected.

INTRODUCTION TO FPGA
The basics of digital circuit design:

Fig:FPGA kit FPGA Design Services: 1-CORE Technologies provides FPGA design services of high quality since 2004. Outsourcing FPGA design to Russia will significantly reduce your design costs. This FPGA design tutorial article is intended to provide an introduction to the area of digital circuit design. The information presented here can be applied not only to FPGA design, but to all types of digital circuit design. Logic gates symbols:

As you can see, small circles denote inversion. Combinational and Sequential Circuits Combinational circuit is a circuit containing no memory units (such as latches and flip-flops). Sequential circuit is a therefore a circuit containing memory units.

A register (block of flip-flops or latches) is an essential part of a typical sequential circuit. In a sequential circuit registers are controlled by a clock signal. The set of

registers controlled by one clock signal is called a clock domain. Complex circuits can have multiple clock domains. Complex logic designs can be split into combinational logic sub-circuits communicating via registers.

Fig: combinational and sequential circuits Timing requirements in synchronous circuits: The following rules apply to synchronous circuits: 1. Setup time (ts). All register inputs must be constant during this time before a corresponding clock edge. 2. Hold time (th). All register inputs must be constant during this time after a corresponding clock edge.

Fig: Timing Diagram There are two other effects that must be taken into account when elaborating sequential circuits:

Clock skew is an effect of non-simultaneous clock switching at the inputs of different registers (controlled by one clock signal).

Clock jitter is an effect of phase noise in a clock signal.

Thus a maximum propagation delay of a combinational circuit must satisfy the following condition: tpmax tclk - ts - t, where tclk is a clock period, ts is a setup time and t accounts for skew and jitter. Typical Logic Primitives: There are many standard logic primitives used by almost all digital designs. Multiplexer A multiplexer is a device which selects from a number of input channels (selection is made based on special control signal).

Fig: Multiplexer For example, the output of the multiplexer on the picture above is determined by a C signal: if C="00" then Z=D0, if C="01" then Z=D1 and so on. Gate-level schematic of this multiplexer is shown below:

Fig: Gate Level Multiplexer

Shift register A shift register can be implemented as a chain of flip-flops:

Fig: Shift Register On a clock edge each flip-flop is assigned a value of the previous one (and zeros flip-flop is assigned a value of DIN). In order for this circuit to work, obviously, flipflop switching delay plus propagation delay must begreater than flip-flop's hold time. Adder Let's have a look on a 1-bit adder, which generates 1-bit sum and a carry bit.

Fig: 1-Bit Adder Several 1-bit adders in a chain make a n-bit adder (4-bit adder shown as an example):

Fig: 4-Bit Adder COUT signal can be used to cascade multiple adders.

Example: An Accumulator Logic primitives can be used to create more complex circuits. For instance, let's consider an 4-bit accumulator (a synchronous device which adds input value to its internal value). Obviously, it can be made of a 4-bit adder and a 4-bit register. Circuit schematic: Our accumulator should have the following ports:

DIN - Data Input; DOUT - Data Output; CLK - Clock; CLR - Asynchronous clear (set register to 0);

Fig:Accumulator

REFERENCES:
1. Digital Design Principles and Practices by John F. Wakerly, Prentice Hall 2. A VHDL primer by J Bhaskar III rd edition 3. Digital Systems Design with FPGAs by ion grout 4. Advanced FPGA Design: Architecture, Implementation, and Optimization by Steve Kilits 5. Digilent Basys Board reference Manual 6. ISE 9.1i Quick start Tutorial 7. Hugo de garis (usu):the designers guide to vhdl 8. www.xilinx.com 9. www.wikipedia.com 10. www.google.com