Microelectronics Journal 41 (2010) 827833

Contents lists available at ScienceDirect

Microelectronics Journal
journal homepage: www.elsevier.com/locate/mejo

Investigation of pillar thickness variation effect on oblique rotating implantation (ORI)-based vertical double gate MOSFET
Munawar A. Riyadi a,b,n, Ismail Saad c, Razali Ismail a
a

Faculty of Electrical Engineering, Universiti Teknologi Malaysia, 81310 Skudai, Malaysia Department of Electrical Engineering, Diponegoro University, Semarang 50271, Indonesia c School of Engineering & IT, Universiti Malaysia Sabah, 88999 Kota Kinabalu, Malaysia
b

a r t i c l e in fo
Article history: Received 11 November 2009 Received in revised form 9 July 2010 Accepted 12 July 2010 Available online 22 July 2010 Keywords: Vertical MOSFET Oblique rotating ion implantation Double gate Silicon thickness effect Fully depleted

abstract
The rapid scaling of integrated circuit requires further shrinkage of lateral device dimension, which correlates with pillar thickness in vertical structure. This paper investigates the effect of pillar thickness variation on vertical double gate MOSFET (VDGM) fabricated using oblique rotating ion implantation (ORI) method. For this purpose, several scenarios of silicon pillar thickness tsi were evaluated for 20100 nm channel length. The source region was found to merge at pillar thickness below 75 nm, which results in oating body effect and creates isolated region in the middle of pillar. The vertical devices using ORI method show better performance than those with conventional implantation method for all pillar thickness, due to the elimination of corner effect that degrades the gate control. The presence of isolated depletion region in the middle of pillar at oating body increases parasitic effect for higher drain potential. By further reduction of pillar thickness towards fully depleted feature, the increase in gate-to gate charge coupling improves the performance of ORI-based vertical double gate MOSFET, as evident in near-ideal swing value and lower DIBL, compared to the partially depleted and body-tied device. & 2010 Elsevier Ltd. All rights reserved.

1. Introduction Recent development of integrated circuit reveals that several fabrication aspects are already approaching the limit, especially when the dimensions are of nanometer scale [1,2]. Furthermore, the complexity of lithography for nanoscale technology poses major technological challenge and skyrocketing manufacturing investment [3]. In dealing with this issue, some innovative structures for further scaling of nanoscale devices have been elaborated, and the vertical metal oxide semiconductor eld effect transistor (MOSFET) is identied as one of them [4,5]. The benets of applying vertical structure in the nanoscale era have been promoted by a number of researchers, e.g. [613]. For ultra short channel length, the channel region could be produced with relaxed lithography in vertical architecture, instead of using complicated lithography tools for planar structure. It can handle the lithography-bounded problem in further scaling by converting the lithography process into layer denition/deposition process for adjusting the channel length. Moreover, as the active area is located at the silicon pillar sidewall, it is easier to produce double or multiple gate structure on vertical geometry that subsequently

n Corresponding author at: Faculty of Electrical Engineering, Universiti Teknologi Malaysia, 81310 Skudai, Johor, Malaysia. Tel.: + 60 7 5536266; fax: + 60 7 5566272. E-mail addresses: munawar.riyadi@gmail.com, munawar.riyadi@ieee.org (M.A. Riyadi).

increases the drive current, with self-aligned features for both gates, which are difcult to obtain in planar geometry. It also has a possibility to increase the space density [8], depending on the application, especially for layout with different W/L ratios. In planar MOSFET, the design of various W/L will directly result in the different size of each transistor, expanding the occupied area. But in vertical structure, the variation of W/L, and particularly the gate length, can be adjusted in the vertical direction by specic process, while maintaining the width of pillar. Various methods have been proposed for developing nanometersized vertical structure. A number of fabrication techniques have been elaborated, either by layer epitaxy [911] or by silicon pillar etch combined with ion implantation methods [1216]. Epitaxy method seems to be an easier way to dene the channel region vertically, but it faces difculties in manufacturing for different types of grown layer in n- and p-type MOS. Conventional ion implantation method allows the CMOS-compatible processing; however, the formation of direct vertical channel at sidewall was limited by either the silicon pillar height itself or by the nitride spacer thickness that is applied as a mask for sidewall region, which eventually creates L-shaped channel (Fig. 1(a)). This shape of channel leads to corner effect in the bottom of pillar, which eventually degrades the devices performance [17]. Moreover, parasitic overlap capacitance problem in source/drain-to-gate area is commonly found in vertical structure that provides drawback effect on the switching speed. The use of llet local oxidation (FILOX) technique above source/drain region was

0026-2692/$ - see front matter & 2010 Elsevier Ltd. All rights reserved. doi:10.1016/j.mejo.2010.07.004

828

M.A. Riyadi et al. / Microelectronics Journal 41 (2010) 827833

Fig. 1. Possible channel formation in vertical MOSFET: (a) L-shape channel in the corner and (b) direct (pure) vertical current channel.

introduced to reduce the problem [18]. Subsequently this work was enhanced by others such as incorporating dielectric pocket [19] or introducing ORI method [20]. Applying dielectric pocket may reduce short channel effect, but the possibility of further shrinkage in pillar dimension is very limited due to the presence of dielectric in the middle of pillars top area. The later, combined with FILOX technique, was convincingly improving the channel scaling with straight vertical current (as illustrated in Fig. 1(b)) while keeping the parasitic capacitance low and offers good short channel effect control. However, the pillar thickness in previous report is noticeably large, and its pillar shrinkage effect has not been elaborated further. In the trend of increased density for overall chip, the pillar width tends to be made in smaller dimension; thus it is of importance to investigate the effect of pillar thickness variation, especially on the fully depleted case. In this paper, the effect of silicon pillar thickness variation on vertical double gate MOSFET with FILOX and ORI method is investigated numerically. The effect of processing variation is elaborated as well as the possibility of formation of partially and fully depleted device using this method, as an extension of a previous work. The devices electrical characteristic and its respective subthreshold behaviour are also elaborated to understand the device performances, especially in the very short channel.

2. Device simulation The proposed vertical MOSFET structure has the feature of symmetrical self-aligned source/drain region for both gates and exhibits straight vertical channel on the sidewall, as shown in Fig. 1(b). The ORI method is employed to reveal this unique feature of the device structure. A o1 0 04 silicon wafer with uniform boron doping of 1 1019 cm 3 is selected as the base substrate. This relatively high substrate doping gives a benet for the suppression of short channel effect [21]. The silicon pillar is formed by dry etch of substrate, which is selectively covered by nitride as etch mask, with the width of nitride equal to the pillar thickness tsi. In addition, the channel length denition is affected by hpillar, the height of pillar (Fig. 2(a)). Stress relief oxide of 20 nm is thermally grown over all silicon surface, followed by the deposition of nitride layer, which subsequently is dry-etched anisotropically to dene the active area (Fig. 2(b)). Later, a thermal oxidation process is held to produce FILOX in the area which is not protected by the nitride spacers; those are the whole active area and the top of the pillar (Fig. 2(c)). The self-aligned source and drain region are constructed by arsenic implantation (6 1015 cm2, 150 keV) using oblique rotating implantation (ORI) method [20] (Fig. 2(d)). This method has

Fig. 2. Process ow for vertical double gate fabrication: (a) pillar denition, (b) nitride spacer, (c) FILOX formation, (d) source/drain implant using ORI (451 tilt and 1801 rotation), (e) poly-gate formation and (f) metal contact.

shown a better shape of source region in the bottom, with the drain-to-source current owing in pure vertical direction [20], rather than with the non-ORI method. After etching of nitride spacers and stress relief oxide underneath, a 3 nm silicon oxide layer is grown on the sidewall of pillar as a gate dielectric. Later, polysilicon with in-situ As doping is deposited for gate electrode. Polysilicon spacer is patterned using dry etch, forming a double gate structure with self-aligned features (Fig. 2(e)). After deposition of LTO for isolation, rapid thermal annealing (RTA, 1100 1C, 10 s) is carried out for dopant activation. Following the contact opening process, aluminum is deposited as metal contact at gate, source and drain (Fig. 2(f), while contact for the double gate is not shown here). The electrical characteristics of the device were obtained by simulating the nal structure using Silvacos Atlas software package [22]. The driftdiffusion (DD) transport model with the Boltzmann carrier transport framework was used, as it is able to predict IV characteristics of DG-MOSFET [23]. Even for nanoscale

M.A. Riyadi et al. / Microelectronics Journal 41 (2010) 827833

829

size 4 10 nm, Granzner et al. [24] have shown that for DG-MOSFETs current characteristics, the DD and Monte-Carlo simulation results produced excellent agreement, while Ren and Lundstorm [25] and Rhew and Lundstorm [26] have revealed that the DD model can predict IV characteristics of short-channel MOS devices more realistically than the energy-balance (EB) model. It is then combined with Lombardi CVT model [27] where its semi-empirical equation gave the complete correlation between carrier concentration, carrier mobility, electric eld and temperature for non-planar device, which is the vertical device, while ShockleyReadHall (SRH) recombination with xed carrier lifetimes models was selected. Moreover, the combination of Gummel and Newton numerical methods was employed for solving quantities for obtaining a convergence of the device structure. The process simulation was validated by comparing the simulated and experimental results from [14] of the 125 nm

channel length vertical structure fabricated without the ORI method, as shown in Fig. 3. The gure shows good agreement between the simulated and experimental results. The discrepancies of subthreshold current from the comparison show that the simulation gives lower drain current than the experimental data with maximum of an order of magnitude at around Vg 1.5 V, which may result from the additional processes not sufciently explained in [14]. However, the extraction of threshold voltage for both data indicates a similar value, which is an indication that the simulation process and the parameters used in the simulation are justied. For the purpose of investigating the channel and junction depth caused by variation of pillar dimension, the silicon thickness and height were varied. Several devices with channel length from 20 to 100 nm at various silicon thicknesses tsi (2575 nm) were constructed and simulated. The values of pillar thickness are selected as representatives of different body potential scenarios in the pillar. The conventional vertical MOSFET, which employs the conventional implantation method, was used as a comparison for several pillar thicknesses. However, the channel length for conventional vertical MOSFET is limited to 50100 nm due to recessed channel length in lateral direction at the bottom of pillar that is around 2040 nm in length, which were also counted here as a part of L-shaped channel length, which in turn makes it difcult to obtain very short channel structure. In all cases, the drain is always on top of the pillar, and the backside substrate is connected to the ground.

3. Pillar thickness variation and junction prole Fig. 4 shows the cross-section of devices with two different pillar thicknesses with different channels and source proles (tsi 75 and 46 nm, with Lch 40 and 70 nm, respectively, for Vds 0.1 V and Vgs 1 V) after all processing sequences were completely done. In addition, the vertical cross-section of the 75 nm thick pillar (Fig. 5) reveals the ability of ORI-based process to obtain the pure vertical channel, as opposed to the non-ORI for the same pillar thickness. The current direction in channel area is purely vertical from drain to source for both cases, as the result of

Fig. 3. Comparison between simulation model and experimental data (taken from [14]) for Lch 125 nm, double gate structure and pillar width 9 mm.

Fig. 4. Cross-section of vertical DG-MOSFET structure with ORI method, taken at Vgs 1 V and Vds 0.1 V for: (a) tsi 75 nm, Lch 50 nm and (b) tsi 45 nm, Lch 100 nm.

830

M.A. Riyadi et al. / Microelectronics Journal 41 (2010) 827833

Fig. 5. The cross-section in vertical pillar of 75 nm shows the formation of direct channel in vertical direction for ORI method as opposed to the non-ORI method.

Fig. 6. The concentration of electron and hole in cross-sectional area AA0 of Fig. 4(b) for several pillar thicknesses (Lch 100 nm), for Vds 0.1 V and Vgs 1 V.

the source region overlapping the corner side of pillar in the bottom area. This feature is of a great advantage in applying ORI method; with conventional implantation technique it is likely that the channel area becomes L-shape, which is the case of some reported devices (e.g. [7,14,28]) as a consequence that the implanted doping for source region cannot occupy the pillars corner at the bottom. But the junction prole inside the pillar changes its shape when the pillar is made thinner, according to the source region boundary in relation with the pillars corner. For device with tsi 75 nm (Fig. 4(a)), the source regions at the right and left side are separately formed, and the pillar regions channel area is tied to the substrate. The channel region is connected to and has the same potential with substrate, similar to bulk transistor. Meanwhile, while smaller pillar thickness is chosen (tsi 46 nm for Fig. 4(b)), both source parts will eventually join together and form a single region, thus the pillar region becoming disconnected from substrate. Thus, for lower thickness, the pillar region is separated from substrate by the source region and is not tied to any potential, and oating body is created. This oating body in turn could be a disadvantage for the device performance, as it may reduce the output resistance and create parasitic transistor on it, which is the case in the partially depleted SOI MOS [29]. The transition width between body-tied and oating body of channel area in pillar depends on several factors, e.g. implantation doses, dielectric thickness and substrate doping, which require optimization for distinct process recipes. In this research, we found that the oating body occurs for pillar thickness below 75 nm, and partially depleted channel is formed. Moreover, when the thickness of the pillar is made thinner, less than 25 nm, it turns out to be fully depleted. The electronhole concentration and potential distribution along the channel, taken for Vgs 1 V and Vds 0.1 V, are shown in Fig. 6. At tsi 57 nm, majority carriers in the middle of pillar region are holes, with almost as many concentration ( $1018 1019 cm 3) as those at the pillars substrate, which has the same type of impurity (p-type). The collection of carriers in the middle area of pillar creates an island (as big as 50 nm in diameter at Lch 100 nm) surrounded by the region whose majority carrier is already depleted; some literatures call this island as depletion isolation region [30]. In decreased pillar thickness, the depletion isolation size as well as its peak carrier concentration are reduced. Furthermore, at tsi 46 nm, the hole concentration in the pillars middle region is overpowered by electron (1071012 cm 3), while in tsi 36 nm, the electron concentration has almost the similar

concentration with the initial substrate impurities in many parts of the pillar. In addition, the depletion isolation is undetected from the graph for this thickness, while the potential barrier between drain and source exhibits a very low barrier created at the lowest tsi. Moreover, the behaviour at pillar thickness of 25 nm (not shown) represents the condition of fully depleted device, as is noted by the calculation of depletion width wd for the respective pillar thickness [31]. This low potential barrier explains the high current drive capability on lower pillar thickness, in which the carriers ow easily without signicant barrier when the channel starts conducting.

4. Result and discussion The electrical performance for different channel lengths from 100 to 20 nm is analyzed for several pillar thicknesses. The threshold voltage for both vertical conventional and ORI DG-MOSFET becomes smaller in shorter channel length due to charge sharing increase between source and drain terminals and also electric eld build-up at the source, which reduces channel region controllability by the gate. In addition, the vertical ORI MOSFET shows lower threshold voltage than its conventional counterpart at every channel length for particular pillar thicknesses (Fig. 7), which is the direct result of straight channel geometry. The conventional vertical structure (with the L-shape channel) lacked the gate control in the corner region, also known as corner effects, which made the decreased potential in the corner area compared to the straight channel, thus preventing the quick conversion into inversion and requiring higher threshold voltage. The similar phenomenon is also found in grooved channel in planar MOSFET, as has been elaborated in [32,33]. In addition, the lower threshold is advantageous for the concern of power consumption in conduction state. The threshold voltage decrease is observed on shorter channel for both structures but with tendency of more rapid decline for L-shaped channel, which need to be avoided for better short channel effect control. The pillar thickness variation effect on drain induced barrier lowering (DIBL) is shown in Fig. 8. The DIBL is calculated for threshold voltages taken at VD 0.1 V and 1.0 V, by the formula: DIBL VT at VD 0:1 V VT at VD 1:0 V =1:0-0:1 in mV/V. For each pillar thickness, it is found that the shorter the channel length, the higher the DIBL, as expected. The pattern is found for both ORI and conventional vertical DG-MOSFET, but the ORI-based vertical DG MOSFETs tend to get lower DIBL in shorter channel than the

M.A. Riyadi et al. / Microelectronics Journal 41 (2010) 827833

831

Fig. 7. Threshold voltage comparison between conventional and ORI vertical DG MOS for several pillar thicknesses (VD 0.1 V).

Fig. 8. DIBL of depleted devices for several channel length in different pillar thicknesses for both ORI and non-ORI vertical DG-MOS, taken at VD 0.1 and1.0 V.

another approach by redening the channel length including the horizontal, recessed part. The comparison study of DIBL in L-shaped (recessed) and straight channel is also found in the surrounding vertical gate (SVG) MOSFET [36], with A pillar diameter of 20 nm. However, that paper uses a different denition of channel length for L-shaped channel (represented by recessed surrounding vertical gate (RSVG) MOSFET), measured only along the vertical part in both channel shapes, and it is found that the recessed part reaches up to 20 nm, quite close with the vertical part length. By rearranging the channel length to be in our term (by adding both vertical and horizontal paths as new Lch for recalculated RSVG structure, as shown in Fig. 9), it reveals the similar trend of DIBL degradation in short channel with our nding, with the value difference resulting from many factors applied in both sets of data (body doping, structure type, pillar thickness, etc). In the terms of pillar variation, the oating body effect (FBE) is emerged for ORI-based vertical DGMOS as shown by increase in DIBL value on pillar narrowing, especially in partial depletion (PD) at thicknesses of 57 and 46 nm before falling down again to fully depleted (FD) feature. The oating body is formed by a different mechanism: one by total isolation due to source connection from left and right (in pillars of 46 nm and thinner) and the other by depletion isolation [30] in higher drain bias, for thicker pillars, such as 57 nm. This effect appears irrelevant for conventional vertical structure that has the propensity to decreasing DIBL for smaller tsi, due to the fact that its channel body is connected to ground. The appearance of isolated area at PD regime in the middle of the pillar for ORI-based structure is believed to provide injection of majority carrier in the area (i.e. hole) to the body comparable to the drain bias (also found similarly in the partially depleted silicon on insulator [37]), which later shifts down the threshold voltage at larger bias and creates large discrepancy with threshold voltage at low drain voltage. With the reduction of pillar thickness towards FD regime, the isolated island is gradually diminished and its unwanted effect is effectively suppressed. The increase of gategate charge coupling [30] along the channel in thinner pillar means that control by both gates is stronger than the drain, thus results in low DIBL, especially in the FD case. Fig. 10 exhibits subthreshold swing (S) on the variation of channel length at several pillar thicknesses, which shows that the swing is decreased for smaller pillar thickness, both with ORI and non-ORI methods. Furthermore, the swing gets closer to the ideal value (i.e. 60 mV/decade for bulk structure) for ORI method,

conventional one with L-shaped channel, which implies better control of SCE. Initially, it seems contradictory with the case in the planar MOSFET, given that the recessed (or grooved) gate has been used to improve the SCE control and reduce DIBL [3335]. Tanaka et al. [33] explored subthreshold performance in grooved gate and elevated source/drain for sub-0.1 um bulk MOSFET, while Ono et al.[34] hinted at increased cutoff frequency with the recessed source/drain structure. However, the denition of channel length in those planar structures is somewhat different with the vertical structure used here. The channel length is measured only for the planar part (parallel to the wafer surface) as in [35], and the raised part is uncounted as its length is considerably small compared to the planar part. But in vertical structure, the horizontal part of L-shape channel (see Fig. 1a) may have more signicant size, and it is commonly found in either source or drain but not in both. By excluding the recessed part, for the same Lch value, the path taken by current in L-shaped channel would be factually longer than in the direct channel, and the ratio of actual current path between both shapes would be signicantly larger when the horizontal (recessed) part gets lengthy and has a comparable size with the vertical part. Thus we choose to take

Fig. 9. DIBL comparison between straight and L-shaped channel in vertical surrounded gate (VSG) MOS (adapted from [36]). The straight channel is represented by the VSG (diamond symbol), the L-shaped channel by the recessed VSG (RSVG) (circle symbol), while the recalculated RVSG (square symbols) counts the horizontal part of recessed gate in its channel length.

832

M.A. Riyadi et al. / Microelectronics Journal 41 (2010) 827833

Fig. 10. Subthreshold swing (S) characteristic of several channel lengths in different pillar thicknesses (VD 0.1 V).

Fig. 12. Drain-source leakage current for various tsi for ORI (solid symbols) and non-ORI (dotted, non-solid symbols) approaches (taken at Vg 0 V and VD 0.1 V).

counterpart while it still maintains the compatibility with standard processing. Moreover, in the future application, it is more advantageous to switch to fully depleted pillar as it shows better overall performance than in partially depleted structure, although the issue of producing reliable ultra thin pillar is of concern that must be answered.

5. Conclusion The structure of vertical double gate MOSFET fabricated with ORI method has been numerically simulated and studied for silicon pillar thicknesses from 75 to 25 nm, which ranges from body-tied to partially depleted to fully depleted channel. The electrical performance for channel length variation between 100 and 20 nm has also been analyzed. It has been demonstrated that the vertical devices using ORI method show generally better performance in terms of lower subthreshold swing, DIBL and threshold roll-off and higher drive current than the conventional implantation vertical device for all pillar thicknesses. This improvement is best explained due to the elimination of corner effect that degrades the gate control and decreases the effective mobility. Shrinking down the silicon pillar thickness below 75 nm eventually creates oating body when the source area from each gate merges in the bottom of pillar. The reduction of pillar thickness produces the decline in threshold voltage and subthreshold swing for the same channel length, but the presence of isolated depletion region in the middle of pillar at oating body increases the parasitic effect for higher Vds, which is evident in higher DIBL. By further reduction of pillar thickness towards fully depleted feature (i.e. less than 25 nm in this case), the increase in gate-to gate charge coupling improves the performance of ORI-based vertical double gate MOSFET, as evident in near-ideal swing value, lower DIBL and better current drive, compared to the partially depleted and body-tied device.

Fig. 11. The on current of ORI vertical DG-MOSFET in various channel lengths Lch, for several tsi, taken at VD 2 V and VgVT 1 V.

especially for large channels. The increase of substhreshold swing in ultra short channel is evident for all pillar thicknesses for both methods, but with steeper increase in non-ORI method. The swing reduction in ORI-based vertical MOSFET for the same channel length indicates an increase in gategate charge coupling with a decrease in pillar thickness, as was independently found in [30]. On the other hand, conventional vertical device suffers from high swing due to less control of gate near the corner. It is found that drain current of ON-state, ID ON, calculated at VD 2 V and VgVT 1 V, rises for smaller pillar thickness, especially when it is close to fully depletion and also for smaller channel length, as shown in Fig. 11. Furthermore, Fig. 12 reveals that the leakage current, calculated at Vg 0 V, tends to increase with the reduction of pillar thickness and channel length. A caution must be taken for the high leakage current, which could lead to rise in power consumption, as the power needed in off state will be signicantly high. On the other hand, the conventional vertical device has lower ON current than the ORI method, due to the fact that the change of direction of current at the pillar corner alters the effective mobility of the charge, which in turn reduces the total current, the phenomenon which is successfully eliminated by the ORI method. Based from our evaluation above, the vertical ORI method gives a better prospect in further scaling of MOSFET than its conventional

Acknowledgments The authors would like to thank the Malaysia Ministry of Science, Technology and Innovation (MOSTI) for sponsoring this work under E-Science Fund and the Research Management Centre of UTM for providing invaluable assistance in conducting the research.

M.A. Riyadi et al. / Microelectronics Journal 41 (2010) 827833

833

References
[1] W. Haensch, et al., Silicon CMOS devices beyond scaling, IBM J. Res. Dev. 50 (2006) 339361. [2] P.M. Zeitzoff, International technology roadmap: MOSFET scaling challenges, Solid State Technol. 51 (2008) (2007) 3537. [3] B.J. Lin, The ending of optical lithography and the prospects of its successors, Microelectron. Eng. 83 (2006) 604613. [4] T. Skotnicki, et al., The road to the end of CMOS scaling, IEEE Circuit Dev. Mag. 21 (2005) 1626. [5] K.J. Kuhn, CMOS scaling beyond 32 nm: challenges and opportunities, in: Proceedings of the 46th Annual Design Automation Conference, San Francisco, California, 2009, pp. 310313. [6] J. Moers, Turning the world vertical: MOSFETs with current ow perpendicular to the wafer surface, Appl. Phys. A 87 (2007) 531537. [7] T. Schulz, et al., Short-channel vertical sidewall MOSFETs, IEEE Trans. Electron Dev. 48 (2001) 17831788. [8] S. Hall, et al., Recent developments in deca-nanometer vertical MOSFETs, Microelectron. Eng. 72 (2004) 230235. [9] J.M. Hergenrother, et al., The vertical replacement-gate (VRG) MOSFET, Solid State Electron 46 (2002) 939950. [10] L. Haitao, X. Zhibin, J.K.O. Sin, An ultrathin vertical channel MOSFET for sub-100 nm applications, IEEE Trans. Electron Dev. 50 (2003) 13221327. [11] J. Moers, et al., Vertical p-MOSFETs with gate oxide deposition before selective epitaxial growth, Solid-State Electron 43 (1999) 529535. [12] H. Cho, et al., A low-power, highly scalable, vertical double-gate MOSFET using novel processes, IEEE Trans. Electron Dev. 55 (2008) 632639. [13] M. Masahara, et al., Vertical double-gate MOSFET device technology, Electron. Commun. Jpn. 91 (2008) 4651. [14] E. Gili, et al., Single, double and surround gate vertical MOSFETs with reduced parasitic capacitance, Solid State Electron 48 (2004) 511519. [15] M. Masahara, et al., Ultrathin channel vertical DG MOSFET fabricated by using ion-bombardment-retarded etching, IEEE Trans. Electron Dev. 51 (2004) 20782085. [16] K. Mori, A.K. Duong, W.F. Richardson, Sub-100 nm vertical MOSFET with threshold voltage adjustment, IEEE Trans. Electron Dev. 49 (2002) 6166. [17] H. Xiao-Yu, et al., Corner effects in double-gate/gate-all-around MOSFETs, Chin. Phys. 16 (2007) 812816. [18] V.D. Kunz, et al., Reduction of parasitic capacitance in vertical MOSFETs by spacer local oxidation, IEEE Trans. Electron Dev. 50 (2003) 1487. [19] E. Gili, et al., Shallow junctions on pillar sidewalls for sub-100 nm vertical MOSFETs, IEEE Electron Dev. Lett. 27 (2006) 692695.

[20] I. Saad, R. Ismail, Self-aligned vertical double-gate MOSFET (VDGM) with the oblique rotating ion implantation (ORI) method, Microelectron. J. 39 (2008) 15381541. [21] S. Oda, D. Ferry, in: Silicon Nanoelectronics., CRC Press, Boca Raton, FL, 2006. [22] Atlas and Athena user Manual Device and Process Simulation Software, Silvaco International, 2005. [23] N.D. Jankovic, G.A. Armstrong, Comparative analysis of the DC performance of DG MOSFETs on highly-doped and near-intrinsic silicon layers, Microelectron. J. 35 (2004) 647653. [24] R. Granzner, et al., On the suitability of DD and HD models for the simulation of nanometer double-gate MOSFETs, Physica E 19 (2003) 3338. [25] Z. Ren, M. Lundstrom, Simulation of nanoscale MOSFETs: a scattering theory interpretation, Superlattices Microstruct. 27 (2000) 177189. [26] J. Rhew, M. Lundstrom, Driftdiffusion equation for ballistic transport in nanoscale metal-oxide-semiconductor eld effect transistors, J. Appl. Phys. 92 (2002) 5196. [27] C. Lombardi, et al., A physically based mobility model for numerical simulation of nonplanar devices, IEEE Trans. Comput. Aided Des. Integrated Circuits Syst. 7 (1988) 11641171. [28] J. Moers, et al., Vertical double-gate MOSFETs, in: ASDAM 2004Conference Proceedings, 5th International Conference on Semiconductor Devices and Microsystems, 2004, Smolenics Castle, pp. 215218. [29] K.K. Das, C.T. Chuang, R.B. Brown, Reducing parasitic BJT effects in partially depleted SOI digital logic circuits, Microelectron. J. 39 (2008) 275285. [30] M.M.A. Hakim, et al., Depletionisolation effect in vertical MOSFETs during the transition from partial to fully depleted operation, IEEE Trans. Electron Dev. 53 (2006) 929933. [31] M.A. Riyadi, et al., Vertical double gate MOSFET for nanoscale device with fully depleted feature, AIP Conf. Proc 1136 (2009) 248. [32] H. Ren, Y. Hao., The inuence of geometric structure on the hot-carrier-effect immunity for deep-sub-micron grooved gate PMOSFET, Solid-State Electron 46 (2002) 665673. [33] J. Tanaka, et al., A sub-0.1 mm grooved gate MOSFET with high immunity to short-channel effects, in: Technical Digest, International Electron Devices Meeting (IEDM), 1993; pp. 537540. [34] M. Ono, M. Koyama, A. Nishiyama, Recessed channel and/or buried source/ drain structures for improvement in performance of Schottky barrier source/ drain transistors with high-k gate dielectrics, Solid-State Electron 51 (2007) 732738. [35] X. Zhang, et al., An analytical model for threshold voltage of grooved-gate MOSFETs, Chinese Journal of Semiconductors 4 (2004) 441445 (in Chinese). [36] B. Subrahmanyam, M. Jagadesh Kumar, Recessed source concept in nanoscale vertical surrounding gate (VSG) MOSFETs for controlling short-channel effects, Physica E 41 (2009) 671676. [37] D. De Venuto, M.J. Ohletz, Floating body effects model for fault simulation of fully depleted CMOS/SOI circuits, Microelectron. J. 34 (2003) 889895.