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A Novel Design of Reversible Universal Shift Register with Reduced Delay and Quantum Cost
D. Krishnaveni, M. Geetha Priya
Abstract Reversible logic gates provide power optimization which can be used in low power CMOS design, optical computing, quantum computing and nanotechnology. This paper proposes a new 3 * 3 reversible SRK gate that works as a reversible 2:1 Multiplexer and has a reduced quantum cost. A novel design of Reversible Universal Shift Register using SRK gates with reduced delay and quantum cost is proposed. Reduction of delay, which is a major factor contributing to the improvement of efficiency of the circuit is adequately taken care in all the components of the proposed design. Thus, this paper provides a threshold to build more complex sequential systems using reversible logic. Index Terms Low power CMOS; quantum computing; Reversible logic gates; Universal Shift Register; quantum cost, Sequential circuits.

1 INTRODUCTION
The synthesis of reversible logic circuits has been the main area of research in recent years. Reversible circuits are of high interest in the field of low power CMOS design, optical computing, quantum computing and nanotechnology. With increasing complexity of CMOS VLSI circuits, Power dissipation has become the main area of concern in VLSI design. It has been demonstrated by Landauer [1961] that circuits and systems constructed using irreversible logic will result in power consumption and energy dissipation due to information loss [1]. It is proved that the loss of one bit of information dissipates kT*log2 joules of heat energy, where k is Boltzmanns constant and T the absolute temperature at which computation is performed [1]. Bennett [1973] showed that zero power dissipation in logic circuits is possible only if a circuit is composed of reversible logic gates since the amount of energy dissipated in a system bears a direct relationship to the number of bits erased during computation [2]. The state of the output prior to and during present output transition must be known to perform a nondissipative transition of the output. That is the copy of the state of the output must be present at all times which can be obtained by using reversible logic. The circuit constructed using Reversible logic do not erase or lose information. Reversible computation in a system can be performed only when the system comprises of reversible gates. The field of quantum computing also uses reversible logic. All quantum gates are reversible [3]. The number of output bits is relatively small compared to that of input bits in

many computing tasks. All of the information encoded in the input must be preserved at the output in computational tasks such as digital signal processing, communication, computer graphics and cryptography. Hence there are compelling reasons to consider circuits composed of reversible gates and the synthesis of such networks.

1.1 Reversible logic

An n-input, n-output, totally specified Boolean function is reversible if it is a bijection, that is; each input pattern is mapped to a unique output pattern. This helps to determine the outputs from the inputs and also the inputs can be uniquely recovered back from the outputs. A balanced reversible function has half of minterms with value 1 and other half with value 0. In an n-output reversible gate the output vectors are permutation of the numbers 0 to 2n-1. The input that is added to an nxk function to make it reversible is called constant input (CI). Garbage outputs (GO) are the outputs of the reversible circuit that are not used in the circuit except to preserve its reversibility. Number of garbage outputs for a particular reversible gate is not fixed, but any output that is not used in a circuit in which the gate is used is labelled garbage outputs. Quantum cost (QC) refers to the cost of the circuit in terms of the cost of a primitive gate. It is calculated knowing the number of primitive reversible logic gates (1*1 or 2*2) required to realize the circuit. [4]. These parameters have to be reduced while designing a reversible circuit. Some of the major problems with reversible logic synthesis are that fanouts cannot be used, and also feedback from gate outputs to inputs is not permitted. However fanout in reversible circuits is achieved using additional gates. A reversible circuit should be designed using minimum number of reversible logic gates. Computation of delay of any circuit is an important parameter as it affects the speed of the circuit and thus the

First Author D. Krishnaveni is with the A P S College of Engineering, Bangalore, Karnataka, India. Second Author M. Geetha Priya., is with Amrita Viswa Vidhyapeetham, Coimbatore, Tamilnadu, India.

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efficiency. The time taken for an input signal to reach the output, or the time taken for a circuit to respond to the changes in the input is called delay. Delay of different circuits varies depending on their design complexity. According to reference [5], delay of the circuit through which an input signal has to traverse, is computed by finding the number of 1X1 and 2X2 reversible gates which constitute the design. Delay through 1X1 and 2X2 reversible gates is assumed to be equal to unit delay (1). Reversible sequential circuits such as shift registers are very important in reversible memory circuits. In this paper, the focus is on the design of a reversible Universal shift register with reduced delay and quantum cost. A new reversible 3*3 SRK gate is proposed that can work as a 2:1 Multiplexer. A reversible 4:1 Multiplexer, Master Slave DFlip flop with synchronous set/reset input, Master Slave DFlip flop with asynchronous set/reset input and a D-Flip flop with asynchronous set/reset inputs are designed from the proposed SRK gate. The reversible circuits proposed and designed in this work form the basis for a reversible sequential circuit design.

the value on its control line and changes the value on the target line using the transformation given by the matrix. Controlled-V+ gate performs the inverse of V. V and V+ gates are defined by the following unitary matrices:

Hadamard gate is defined by the matrix

2.1 Quantum cost of Fredkin gate (FRG) The Fredkin (FRG) Gate is a controlled swap gate, i.e. if the control bit A is 1, then the two input bits A and B are swapped at the output else their order remains the same. Quantum circuit (Fig 1a) using CNOT and C2NOT gates is obtained and reduced (fig 1b). C2NOT gate is replaced with its primitive gate circuit (fig 1c). Using quantum templates, moving rule and deletion rule, the final quantum circuit (fig 1d) is obtained. Each dotted rectangles in Fig. 1d is equivalent to a 2x2 Feynman gate and so the quantum cost of each dotted rectangle is 1. The total quantum cost of Fredkin gate is thus 5.

2. QUANTUM LOGIC [3], [6]-[9]

Quantum gates are reversible and manipulate qubits rather than pure logic values. A qubit is a two-level quantum system, described by a two-dimensional complex Hilbert space. The two orthogonal quantum states are used to represent the values 0 and 1. The state of a qubit for two pure logic states can be expressed as

0 1

(called superposition), where and are complex numbers so that

Fig 1: Quantum circuit of FRG gate [6], [9]

1.
2 2

3. REVERSIBLE GATES
3.1 Reversible gates
Some major reversible gates required for this study are Feynman gate (FG) [10], Toffoli gate (TG) [11], Fredkin gate (FRG) [12], Peres gate (PG) [13], HNFG [14], and BVF gate [15]. Quantum cost of FG, TG, FRG, PG, HNFG, and BVF gates are 1,5,5,4, 2 and, 2 respectively. The reversible gates and their quantum circuits are shown in fig 2.

An n-qubit quantum gate is a device which performs a specific 2n X 2n unitary operation on selected n qubits in a specific period of time. A matrix U is unitary if UU+ = I where U+ is the conjugate transpose of U and I is the identity matrix. Any reversible gate can be decomposed into a quantum circuit composed of a sequence of elementary quantum gates defined as follows: The NOT gate maps the input x x 1, where the symbol represents the EXOR operation. The NOT gate inverts the input qubit value at the output. The ControlledNOT (CNOT) gate maps two inputs (x, y) (x, y x), where x is the control input and y is the target input. The CNOT gate inverts the target qubit value at the output if and only if the control qubit value is 1. The CNOT gate is also known as Feynman gate. The C2NOT gate maps three inputs (x, y, z) (x, y, z xy), where the product represents the AND operation. Here, x and y are control inputs and z is target input. C2NOT gate is also known as Toffoli gate. The SWAP gate maps two inputs (x, y) (y, x). A SWAP gate exchanges the two qubit values at the output. Controlled-V gate performs the V operation known as the square root of NOT, since two consecutive V operations are equivalent to an inversion. Controlled-V gate depends on

Fig 2a: Feynman (FG) gate [10]

Fig 2b: Toffoli (TG) gate [11]

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3.4 Reversible Universal Shift Register 1) Reversible Universal Shift Register using FRG, FG and HNFG gates [18]

Fig 2c: Fredkin (FRG) gate [12]

Fig 2d: Peres (PG) gate [13]

The existing design of Reversible Universal Shift Register (USR) in reference [18] is basically built from basic cells comprising of DFF, Feynman gate (FG), HNFG gate, and Fredkin (FRG) gates. In the existing design fanout circuits are not used for any of the signals. The selection input S1, which is the input to first FRG, is generated as the output of that FRG gate and is connected to S1 input of second FRG gate to reduce the garbage outputs. Similarly, S0, S1 and clock which are common inputs to all the basic cells, are generated from each basic cell and connected as inputs to the next basic cell, to reduce the garbage outputs.

2)

Reversible Universal Shift Register using FRG and FG gates [5]

Fig 2e: BVF gate [15]

3.2 Reversible Positive level triggered D-Flip Flop [16], [17]

The characteristic equation of D-Flip Flop (DFF) is Q+ =D.CLK + Q.CLK which can be implemented using the Fredkin gate (fig 3). To avoid a fanout problem, a Feynman gate is used to copy the output.

The design discussed in reference [5] makes use of Master Slave D-Flip Flop (MSDFF) with asynchronous set/reset input to design a 4-bit Reversible Universal Shift Register (USR). S1, S0 obtained from 4:1 Multiplexer and clock generated from one D-Flip Flop are given as input to the next component in the design to reduce the garbage outputs. Here, delay of the Flip Flops designed is calculated using the total number of 1X1 and 2X2 gates through which the signal passes. The delay of 1X1 and 2X2 gates is considered to be unit delta (1).

4. PROPOSED 3*3 REVERSIBLE GATE

A 3*3 reversible SRK gate is proposed which is shown in Fig 4. It can be verified that input pattern corresponding to a particular output pattern can be uniquely determined. The quantum cost of SRK gate is calculated to be equal to 4 and that of Fredkin gate used in the existing designs [5] and [18] is 5. The computation of quantum cost of SRK gate is shown in the next section.

Fig 3: D Flip Flop (DFF) using FRG and FG gates

3.3 Reversible Master Slave D-Flip Flop [16], [17]

Master slave D-Flip Flop (MSDFF) is obtained by connecting two D latches in such a way that first DFF acts as a master and second DFF acts as a slave. Master changes its state when clock =1, and slave changes its state when clock =0. This implies that the input given when clock=1, reaches the output of the Flip Flop when clock becomes 0; thus the Flip Flop is level sensitive.

Fig 4: Proposed Reversible SRK Gate

P m(4,5,6,7), Q m(1,2,4,7)

R m(1,3,6,7)

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The proposed SRK gate can work as a reversible 2:1 Multiplexer. When input A is 0, information on input line C is selected and placed on output line R. When input A is 1, information on input line B is selected and placed on output line R. Thus, input line A acts as a select line and input lines C and B act as data input lines; thus forming a 2:1 Multiplexer.

5. QUANTUM COST OF SRK GATE

Quantum circuit of SRK gate using CNOT and C2NOT gates is obtained (fig 5a). C2NOT gate is replaced with its primitive gate circuit (fig 5b). Using quantum templates, moving rule and deletion rule, the final quantum circuit (fig 5c) is obtained. The dotted rectangle in Fig 5c is equivalent to a 2x2 Feynman gate and so its quantum cost is 1. The quantum cost of SRK gate which is equal to the number of 1X1 and 2X2 primitive reversible gates is found to be 4. Thus, if a 2:1 Multiplexer is needed in a design, SRK gate can be used instead of FRG gate.

selectors. In a 2n:1 multiplexer, the data on one of its 2n data input lines is selected using n number of select lines and placed on a single output line. Larger multiplexer trees can be designed, using smaller multiplexers. A 4:1 multiplexer can be constructed using three 2:1 multiplexers. Similarly larger multiplexer trees can designed, using SRK gates as 2:1 multiplexer. The construction of 4:1 multiplexer using SRK gates is shown in Fig 6. In the design of MUX I circuit in fig 6a, a fan out gate (FG gate) is used to provide the select line inputs. This ensures that the delay of the circuit reduces. MUX II design in fig 6b uses the select line signals generated at the output of reversible gates to be given to the next gate. Thus, fan out circuit is not required which leads to reduction in garbage outputs but at the cost of delay. Comparison of the proposed designs with the existing circuit with respect to number of gates, constant inputs (CI), garbage outputs (GO), quantum cost (QC), and delay is given in Table 1.

Fig 5a: Quantum circuit of SRK gate Fig 6a: 4:1 Proposed 4:1 Multiplexer (MUX I)

Fig 5b: C NOT or TG gate replaced with its primitive gate circuit

Fig 6b: Proposed 4:1 Multiplexer (MUX II)

Fig 5c: Reduced quantum circuit of SRK gate

6. REVERSIBLE 4:1 MULTIPLEXER

Multiplexers are very useful MSI devices that act as data

Thus from the comparison shown it is seen that there is a tradeoff between Quantum cost (QC)), garbage outputs (GO) and delay. If quantum cost and garbage outputs need to be reduced, then outputs of a reversible gate need to be used as input to other reversible gate i.e. MUX II design is used. But then, the delay increases. If delay is the main concern of the designer, MUX I design has to be used.

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TABLE 1: A COMPARISON OF 4:1 MULTIPLEXERS No of gates Proposed design (MUX I) Proposed design (MUX II) Existing design using FRG gates [5] 4 3 3 CI 1 0 0 GO 6 5 5 QC 13 12 15 Delay 9 12 15

7.4 Flip flop block using D flip flop with set/reset (FF III)
The D Flip Flop used in the proposed Design of Reversible Universal Shift Register is a clocked DFF with set/reset input. It makes use of SRK gates and BVF gate to act as a DFF. Fig 7d and Fig 7e gives the structure of the D Flip Flop with synchronous set/reset and asynchronous set/reset respectively. All the designs explained above, i.e. Flip flop blocks FF I, FF II and FF III can be used in the proposed Design of Reversible Universal Shift Register. Comparison of the proposed designs of Flip flop blocks with the existing circuits is given in Table 3. TABLE 3: A COMPARISON OF FLIP FLOP BLOCKS WITH THE EX-

7. DESIGN OF FLIP FLOP BLOCKS IN UNIVERSAL

SHIFT REGISTER

7.1 Reversible master slave D flip flop (FF I)

A Flip Flop is a bi-stable element that can be used as a one-bit memory device. The Master Slave D- Flip Flop (MSDFF) designed from SRK gates is shown in Fig 7a.
ISTING DESIGNS

CI Proposed design (FF I)(MSDFF) Proposed design (FF II) (MSDFF with set/reset) Proposed design (FF III) (DFF with set/reset) Existing design if set/reset input is added [18] Existing design [6] 2 2 1 1 2

GO 3 5 4 4 5

QC 10 14 9 11 17

Delay 10 14 9 11 17

7.2 Reversible master slave D flip flop with synchronous set/reset

Synchronous set/reset implies that the Flip Flop is set or reset at the positive edge of the clock. The Master Slave DFlip Flop (MSDFF) with synchronous set/reset input designed from SRK gates is shown in Fig 7b. BVF gate is used at the output of MSDFF as a fanout circuit. In the proposed design, the Flip Flop will set, reset or operate as a normal Flip Flop depending on inputs X and Y as shown in Table 2. TABLE 2: FF OPERATION DEPENDING ON CONTROL INPUTS X AND Y X 0 1 1 Y 0 1 0 Operation Reset Set Normal DFF

8. REVERSIBLE UNIVERSAL SHIFT REGISTER

A register is an interconnection of Flip Flops taken as an entity which store information within a digital system so that they can be used later during the computing process. Shift registers are the registers in which the information can be moved position wise upon the occurrence of a clock signal. The information can be shifted in both the directions in a universal shift register. All modes of operation such as SISO, SIPO, PISO and PIPO can also be performed upon the occurrence of clock. Thus, serial data (SIR during right shift and SIL during left shift) or parallel data (Ia, Ib, Ic, Id) can be loaded into shift register. The values at the select lines determine the operation to be performed as given in Table 4. The Universal shift register performs the shift right operation when the select lines S1S0 of the multiplexers are 01. Thus, input I1 of each multiplexer is selected and connected to the input of respective DFFs. Upon the occurrence of the clock, the register shifts its contents one position to the right. Similarly, when S1S0 take the values 10, 11, and 00, I2, I3 and I0 of each multiplexer is connected to its f output

7.3 Reversible master slave D flip flop with asynchronous set/reset (FF II)
Asynchronous set/reset implies that the Flip Flop is set or reset irrespective of the input data and clock. The Master Slave D- Flip Flop with asynchronous set/reset input designed from SRK gates is shown in Fig 7c. BVF gate is used at the output of MSDFF as a fanout circuit. The Flip Flop will set, reset or operate as a normal DFF depending on inputs X and Y. When the values of X and Y is 00 or 01, the Flip Flop will reset or set respectively and when XY= 10, it works as a normal DFF.

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and thus to the input of FF [19]. TABLE 4: FUNCTION TABLE FOR THE REVERSIBLE UNIVERSAL
SHIFT REGISTER

S1 0 0 1 1

S0 0 1 0 1

Operation No Change (Qi) Right Shift (Qi-1) Left Shift (Qi+1) Parallel load (Ii)

Flip Flop to the output of final Flip Flop, considering the multiplexers is depicted in Table 6. Thus it is seen that in the proposed design of Reversible Universal Shift Register, the delay and quantum cost are drastically reduced as compared to the existing design of [5] and [18]. The proposed designs have been simulated using Xilinx 12.1 version and the simulated waveforms are shown in fig 10 (Reversible universal shift register using D FF) and fig 11 (Reversible universal shift register using MSDFF)

8.1 Proposed Reversible Universal Shift Register

The proposed design of Universal shift register shown in fig 8 consists of Flip flop blocks that can make use of the design of FF I (Master slave D Flip flop), FF II (Master slave D Flip flop with synchronous or asynchronous set/reset) or FF III (D Flip flop with synchronous or asynchronous set/reset), and 4:1 Multiplexer design (MUX I or MUX II).

9. CONCLUSIONS
A new reversible 3*3 SRK gate that acts as a 2:1 multiplexer is proposed in this paper whose quantum cost is less than that of Fredkin gate when used as a multiplexer. Thus the design of reversible Flip flops and Universal shift register using SRK gate has reduced quantum cost and delay. The proposed design can also be extended to an n-bit Reversible Universal shift register. Thus the proposed circuit can be used for designing large reversible sequential systems.

8.2 Analysis and Results

In the proposed design, reduction of delay is adequately taken care for all the components. Circuits are used to duplicate S0, S1 and X, and Y signals for setting or resetting of the flip flop so that these inputs are given simultaneously to all the components, thus effectively minimizing the delay. The existing design [18] of Reversible Universal Shift Register is basically built from basic cells comprising of D Flip Flop, Feynman (FG) gates, HNFG gate, and Fredkin (FRG) gates. In this design number of gates, constant inputs (CI), garbage outputs (GO), and quantum cost (QC), are 26, 14, 19, and 94 respectively. If set/reset input is added to the flip flops in this design, number of gates, constant inputs, garbage outputs, and quantum cost would be 26+7=33, 14+6=20, 19+8=27 and 94+26=120 respectively. The design in [5] consists of FG and FRG gates. In this design the number of gates, constant inputs (CI), garbage outputs (GO), and quantum cost (QC) is 48, 24, 31 and 144 respectively. Comparison of the design in [5], and [18] with the proposed Design wrt number of gates, constant inputs (CI), garbage outputs (GO), and quantum cost (QC) is depicted in Table 5. In the multiplexer circuit in [5] and [18], the selection input S0, which is the input to first FRG, is generated from that FRG gate and is connected to S0 input of second FRG gate to reduce the garbage outputs. If the connections are made in this manner, the number of garbage outputs are reduced, no doubt, but the delay increases as the second FRG gate has to wait for the first FRG gate to produce S0 output which would act as input to the second FRG gate. Thus, the operation of both FRG gates is not simultaneous. This design should be used when delay is not the major aspect. This is the same case with the proposed MUX II design. The delay offered by each Flip Flop is calculated in terms of . Time taken for one SIR or SIL bit to traverse from 1st

REFERENCES
[1] R. Landauer, Irreversibility and Heat Generation in the Computing Process, IBM J. Research and Development, vol. 3, pp. 183191, July 1961. C. H. Bennett, Logical Reversibility of Computation, IBM J. Research and Development, pp.525-532, November 1973. M. Nielsen and I. Chuang. Quantum Computation and Quantum Information. Cambridge University Press, 2000 Maslov, D., Dueck, G. W., Garbage in Reversible Designs of Multiple Output Functions, 6th International Symposium on Representaions and Methodology of Future Computing Technologies,pp: 162-170. Thapliyal, H. and Ranganathan, N., Design of Reversible Sequential Circuits optimizing Quantum Cost, Delay, and Garbage Outputs, 2010 ACM J. Emerg. Technol. Comput. Syst. 6, 4, Article 14, (December 2010), 31 pages. Perkowski, Martin Lukac, Pawel Kerntopf, Mikhail Pivtoraiko,Michele Folgheraiter , Dongsoo Lee, Hyungock Kim,Woong Hwangbo,Jung-wook Kim and Yong Woo Choi.,A Hierarchical Approach to Computer-Aided Design of Quantum Circuits Maslov, D., Dueck, G. W., and Miller, D ,Techniques for the synthesis of reversible Toffoli networks. ACM Trans. Des. Automat. Electron. Syst. 12, 4, Article 42 (September 2007), 28 pages. Pawel Kerntopf, Synthesis of Multipurpose Reversible Logic Gates, Proceedings of the Euromicro Symposium on Digital System Design (DSD02) 2002 IEEE Anindita Banerjee, Anirban Pathak, An algorithm for minimization of quantum cost, arXiv: 0910.2129v2 (2010) Feynman R., 1985. Quantum mechanical computers, Optics News, 11: 11-20. T. Toffoli., Reversible Computing, Tech memoMIT/LCS/TM-151, MIT Lab for Computer Science (1980). Fredkin E. and T. Toffoli, 1982. Conservative logic. Intl J. Theoretical Physics, 21: 219-253. Peres A., 1985. Reversible logic and quantum computers. Physical Review. Haghparast, M. and Keivan Navi, 2008. A novel reversible BCD adder for nanotechnology based systems. Am. J. Applied Sci., 5: 282-288. H.R.Bhagyalakshmi and M.K.Venkatesha, An improved design

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of a multiplier using reversible logic gates, International Journal of Engineering Science and Technology Vol. 2(8), 2010, 3838-3845 [16] Thapliyal, H. and M. Zwolinski, 2006. Reversible logic to cryptographic hardware: a new paradigm. Proceedings of the 49th IEEE International Midwest Symposium on Circuits and Systems (MWSCAS '06), Aug. 6-9, Puerto Rico, 1: 342-346, doi: 10.1109/MWSCAS.2006.382067. [17] Siva Kumar Sastry Hari Shyam Shroff Sk. Noor Mahammad V. Kamakoti, Efficient Building Blocks for Reversible Sequential Circuit Design 2006, IEEE. [18] Noor Muhammed Nayeem, Md. Adnan Hossain, Lafifa Jamal, Hafiz Md. Hasan Babu, Efficient Design of Shift Registers Using Reversible Logic, 2009 International Conference on Signal Processing Systems, IEEE [19] Donald. D. Givone, Digital principles and design, Tata McGrawHill, pp. 332-336.

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Fig 7a: Master slave D Flip Flop (FF I)

Fig 7b: Proposed Reversible MSDFF with Synchronous Set/Reset using SRK gates (FF II)

Fig 7c: Proposed Reversible MSDFF with Asynchronous Set/Reset using SRK gates (FFII)

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Fig 7d: Proposed design of DFF with synchronous set/reset (FF III)

Fig 7e: Proposed design of DFF with asynchronous set/reset (FF III)

Fig 8: Proposed Design of Reversible USR using either FF I, FF II or FF III designs for each Flip flop block and MUX I or MUX II designs for 4:1 Multiplexer with clock input of a gate connected to clock output of previous gate

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Fig 9: Fanout circuit to duplicate (a) the select lines (b) set/reset lines

TABLE 5: COMPARISON OF DESIGN OF REVERSIBLE UNIVERSAL SHIFT REGISTER USING DIFFERENT DESIGNS OF FLIP FLOP BLOCKS WITH THE EXISTING DESIGNS (CLOCK FAN OUT CIRCUIT NOT USED) FF block used FF-I FF-I FF-II FF-II FF-III FF-III Existing design [5] Existing design [18] Existing design (if set/reset is added), [18] 4:1 MUX used MUX-I MUX-II MUX-I MUX-II MUX-I MUX-II MUX using FRG MUX using FRG MUX using FRG No. of gates 41 34 48 41 40 33 48 26 33 CI 28 18 34 24 30 20 24 14 20 GO 33 21 41 29 37 25 31 19 27 QC 108 98 130 120 110 100 144 94 120

TABLE 6: TIME TAKEN FOR SIR OR SIL BIT TO REACH OUTPUT OF LAST FF (CONSIDERING THE DELAY OF MULTIPLEXERS)

FF block used MSDFF-I MSDFF-I MSDFF-II MSDFF-II DFF with S/R DFF with S/R Existing design [5]

4:1 MUX used MUX-I MUX-II MUX-I MUX-II MUX-I MUX-II MUX using FRG

Delay of 1st FF 25 24 29 28 24 23 33

Delay of 2nd FF 46 48 54 56 44 46 67

Delay of 3rd FF 68 73 80 85 65 70 102

Delay of 4rth FF 90 98 106 114 86 94 137

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Fig 10: Simulation result of Reversible Universal Shift Register with Flip flop block using D Flip Flops.

Fig 11: Simulation result of Reversible Universal Shift Register with Flip flop block using Master slave D Flip Flops.

D Krishnaveni obtained her BE. Degree in Electronics and communication from Nagarjuna University, AndhraPradesh, India in 1994. Master of Engineering from B.M.S.C.E., Bangalore, V.T.U. Currently she is working as Assistant Professor in the Department of Telecommunication Engineering, A P S College of Engineering, Bangalore, Karnataka, India. Her areas of research are reversible logic design, quantum computing and Low power VLSI. M.GeethaPriya is an Assistant Professor in Department of Electronics and Communication Engineering, University Amrita school of Engineering, Ettimadai, Coimbatore.She obtained her BE in Electronics and Communication Engineering and ME in VLSI Design from Anna University. Her research interests include VLSI Signal Processing and Reversible logic computation.