Negative feedback control system where fout tracks fin and rising edges of input clock align to rising

edges of output clock Flip-flop Counter PD

Nyquist Rate Phase Detector Uses an analog-to-digital converter.

Zero-Crossing Phase Detector

Digital-Averaging Phase Detector Similar to the Hilbert transform but simpler. cose and sine are implemented by averaging (integrating) the output signals of the multipliers over an appropriate period of time. This phase detector includes a filter function defined by the impulse function of the averaging circuitry.

LOOP FILTERS FOR THE ADPLL Categories 1.) PDs not having a parallel digital output. 2.) PDs having a parallel digital output

K Counter Loop Filter (74xx297) Works with EXOR or JK Flip-flop PDs. (fclock = Mfo)

N before M Loop Filter Block diagram:

Operation: The upper N counter will produce a carry pulse whenever more than N pulses of an ensemble of M pulses have been UP pulses. The lower N counter will produce a borrow pulse whenever more than N pulses of an ensemble of M pulses have been DN pulses. The performance of the filter is very nonlinear. DIGITAL CONTROLLED OSCILLATORS N Counter The N-bit output signal of a digital loop filter is used to control the scaling factor N of the N counter. PLL Failures

 Observation is that VCO frequency is pinned at max value. Cant observe Vctl or feedback clock. VCO fails to oscillate at low frequency because of insufficient gain in 3stage VCO. When VCO finally starts, FBDIV cant keep up, causing runaway Solution: increase gain of delay stage and FBDIV speed. VCO run-away when re-locking to higher frequency due to VCO overshoot and slow FBDIV. VCO loses lock occasionally at low frequencies. Due to insufficient VCO level-shifter gain. Dropped VCO edges. Required real-time scope for debug High jitter at low VCO frequencies due to Vctl approaching Vt of V2I current source. Solution: operate VCO at 2X. Occasional high deterministic jitter caused by coupling into PLLs VDDA bondwire. Extremely high period jitter caused by incorrect wiring of 8-bit charge-pump setting. Bandwidth much too high. Verilog model did not check for legal input settings. PLL wont start-up at low temp due to weak start-up circuit in voltage regulator and lack of simulation at corners with slow VDDA ramp-rate. PLL period modulated strongly by 400MHz signal, resulting from oscillating internal feedback loop in VCO bias ckts. Ultimate cause, fab misprocessing of compensation cap and insufficient margin in ckt. Metastability condition corrupted digital loop filter due to slow devices, low Vdd, and insufficient design margin. Digital VCO out-of-range due to resistor mis-processing. Solution: fusable chicken-bits to adjust frequency range. Race condition in digital loop filter caused by missing synchronizers in clock domain crossing. CDM ESD failures of analog measurement pins no visual inspection and no extraction/simulation of connection to VSS. Duty-cycle corruption (> 57%) caused by unbalanced fanouts in delay stages after VCO exacerbated by singleended clocking. Contention in analog observation signals due to ESD diodes wired backward and control logic bugs. Inconsistent duty cycle. Failure to initialize state in post-VCO divider exposed VCO duty-cycle error. Jitter Definitions Phase Jitter (sec) deviation of VCO output edges from ideal placement in time. specified over a time interval or frequency range. important for I/O apps (e.g. PCI-Express < 1.5ps RMS)

 measure with spectrum analyzer or scope with jitter package Period Jitter (sec) deviation of VCO period from ideal period derivative of Phase Jitter with respect to time peak-to-peak period jitter (Jpp) is max VCO period min VCO period most important for CPU-like apps e.g. 10-20ps for 2GHz CPU clock easily measured on scope self-triggered infinite-persistence or jitter package Cycle-to-Cycle Jitter (sec) change in VCO period from cycle N to cycle N+1 derivative of Period Jitter with respect to time not important for CPU-like apps Jitter Definitions TIE (sec) time difference between total of N-consecutive actual VCO cycles and N ideal cycles easily measured on oscilloscope with jitter package self-triggered measurement TIE time-interval error What is a Digital PLL? Replace charge-pump (time error-to-charge) with TimeError-to-Digital Converter Replace loop filter with discrete-time digital filter (usually 2nd or 3rd order sigma-delta) Replace voltage-controlled VCO with digital-control (vary cap load, interpolation, etc.) Are analog components allowed? Voltage regulator? Analog current-steering DAC for VCO? Sampled-system modeled in the Z-domain Copyright, Dennis Fischette, 2009 93 Why a Digital PLL? Replaces process and noise-sensitive analog circuits with digital equivalents advances on work with digital DLLs Increases PLL design portability and testability Takes advantage of area scaling with nm devices Greater flexibility in loop bandwidth dont need huge capacitors for low BW Increases ability to test and observe. e.g. open-loop, disturb loop Fast behavioral simulation Good-enough for frequency synthesis applications ISSCC presentations: TI(04) and IBM (07) Copyright, Dennis Fischette,

2009 94 Why NOT a Digital PLL? Often not good enough for phase-tracking applications VCO frequency has finite frequency resolution (e.g. 10-14 bits). May use coarse DAC if high-frequency dithering available VCO has limited range requires range control and/or calibration VCO may have poor noise rejection if purely digital frequency control and no voltage regulator (usually analog) Copyright, Dennis Fischette, 2009 95 Why NOT a Digital PLL? Need high-frequency over-sampling clock for sigma-delta loop filter VCO? Refclk? Start-up problem? TimeError-to-Digital Converter is hard poor resolution, high power usually < 5 bits Bang-bang is an alternative (IBM) FbDiv internal state contains phase error information Digital filter generates large noise spurs, possibly inducing jitter, and dissipates more power than passive loop filter Requires delta-sigma modulation to reduce spurs Generating proportional correction can be tricky Voltage-Controlled Oscillator Ring-oscillator (RO) Wide frequency range Easy to design, integrate, and model Easy to generate multi-phase outputs Small area but high power for low jitter Low Q higher jitter LC-tank Narrow frequency range Need field-solver tools to model inductor and accurate varactor model Hard to generate multi-phase outputs Large area but low power High Q lower jitter Loop Filter Basics Simplest and most commonly-used loop filter is continuous-time, passive filter (1 R, 2 Cs) affects stability and bandwidth Integrates low-frequency phase errors onto C1 cap to set avg. freq Resistor provides a means of isolating phase correction from frequency correction Icp*Rlpf for stability but R adds thermal noise that is band-pass filtered by PLL

 C2 cap filters high-freq noise spurs caused by sampling but adds parasitic pole at 1/RC2 Other options include digital(FSM-based) filter, sampled-time filter (see Maneatis, Maxim) , and continuous-time active filter Differential designs can reduce sensitivity to VDD and substrate noise and often area by 2. Requires common-mode feedback loop Copyright, Dennis Fischette, 2009 51 Loop Filter Resistor Resistance may be programmable using switches Parasitic switch resistance varies with control voltage Usually lowest at Vctl extremes if CMOS transmission gate Large Rswitch variation vs. Vctl if NMOS or PMOS only Usually Rswitch < 5-10% of Rlpf Minimize gate leakage and noise coupling from switches Coupling less of a problem if using voltage regulators Typical values: 500 < Rlpf < 50k Poly, Diffusion, Nwell Rs most common MOSFET Rs sometimes used if R placed below C1 cap Constant Vgs needed Copyright, Dennis Fischette, 2009 52 Integrating Cap Configuration Integrating cap (C1) may be placed above or below loop filter resistor Parasitic bottom capacitance for C1 above configuration Variable resistance if switches used in programmable resistor for C1 below configuration Copyright, Dennis Fischette, 2009 53 Loop Filter Capacitors Reference capacitor to same supply as VCO V-to-I reference makes power supply noise common mode Gate Leakage in MOSFET caps can be a HUGE problem Exponential Ileak vs. V: Ileak~Vgate 4 (approximate) Weak temperature dependence Ileak vs. tox ~2-3per Angstrm Use metal caps (2-10X larger) or thick-gate (IO) oxide caps to minimize leakage If MOSFET caps, accumulation mode preferred flatter Cgate vs. V Ileak causes large refclk spurs (jitter) and static phase error

 Typical values: 5pF < C1 < 200 pF 1% (low phase error) < C2/C1 < 10% (low period jitter) Smaller C1 caps are becoming more common w/ higher reference frequencies and metal cap usage PFD Block Diagram Edge-triggered Input duty-cycle doesnt matter Frequency correction takes precedence over phase correction no harmonic locking 3 state operation Output pulse-widths proportional to phase error Reset delay to provide minWidth on output pulses to avoid dead-zone Symmetric NAND used to balance equalize delays from both inputs PFD fails as Treset approaches Tref limit cycles Challenge for Gb/sec IO links Pulsed-flop designs can be faster

Frequency Lock Detector Sample PFD GoFaster signal with rising RefClk Sample PFD GoSlower signal with rising Fbclk If either sampled signal is TRUE, then PFD detected two consecutive RefClks or FbClks cycle slip and loss of frequency lock May apply sticky bit to result to capture temporary loss of lock Sample GoFaster/GoSlower with falling edges of RefClk/Fbclk to detect 180 degrees phase error

Charge-Pump Wish List Equal UP/DOWN currents over entire control voltage range reduce static phase error Minimize mismatch caused by finite current sources gds and Vt mismatches Vt ~ 1 / sqrt(W*L) long L in current sources for higher rout Stacked (a.k.a. common) gates in Isources reduce mismatch use replica-bias CP and feedback amplifier to balance Iup/Idown beware of mismatch between two CP cells increase in CPs phase noise due to finite BW of this feedback? Minimal coupling to control voltage during switching and leakage when off - reduce jitter and phase drift Insensitive to power-supply noise and process variations loop stability Copyright, Dennis Fischette, 2009 41 Charge-Pump Wish List Minimize coupling caused by clock feedthrough (Cgd) and charge-injection big problem sized dummy switches to reduce charge-injection Qinj ~ *Cox*(W*L)*(Vgs-Vt) Small (and/or limited swing) switches to reduce clock feedthrough watch for leakage with limited-swing Balance timing and slew rates of Up/Down inputs Reduce PFD pulse-width to minimize device noise while still avoiding dead-zone (< 100 ps possible in 65nm) noise is band-pass filtered by PLL Typical Icp: 5A (mismatch)< Icp < 300 A (headroom)

Copyright, Dennis Fischette, 2009 42 Charge Pump: const I with amp Amp keeps Vds of current sources constant (Young 92), sinking waste current when UP and/or DOWN off Voffset (off) need high-gain amp Voffset (on)= Icp/gm often Iamp > 3-5X Icp to reduce offset Both PMOS and NMOS input pairs needed for wide input range

Charge Pump: replica-feedback Replica-bias CP and additional amp used to set bias Vbp, forcing Iup=Idn at low freq Start-up may be needed. Stability a concern

Is My PLL Stable? PLL is 2nd-order system similar to mass-springdashpot or RLC circuit. PLL may be stable or unstable depending on phase margin (or damping factor). Phase margin is determined from linear model of PLL in frequency-domain. Find phase margin/damping using MATLAB, loop equations, or simulations. Stability affects phase error, settling, jitter. Copyright, Dennis Fischette, 2004 12 What Does PLL Bandwidth Mean? PLL acts as a low-pass filter with respect to the reference. Low-frequency reference modulation (e.g.spreadspectrum clocking) is passed to the VCO clock. High-frequency reference jitter is rejected. Bandwidth is the frequency at which the PLL begins to lose lock with the reference (-3dB). PLL acts as a high-pass filter wrt VCO noise. Bandwidth affects phase error, settling, jitter What Determines Stability and Bandwidth? Damping Factor (measure of stability) Natural Frequency (measure of bandwidth) Damping and natural frequency can be set independently by LPF resistor

Low-Pass Filter Integrates charge-pump current onto C1 cap to set average VCO frequency (integral path). Resistor provides instantaneous phase correction w/o affecting avg. freq. (proportional path). C2 cap smoothes large IR ripple on Vctl Typical value: 0.5k < Rlpf < 20kOhm

Copyright, Dennis Fischette, 2004 91 Real-world PLL Failures Copyright, Dennis Fischette, 2004 92 PLL Problem Problem: 3-stage PMOS diff-pair VCO wouldnt oscillate at low frequencies. When VCO finally started up at high Vctl, it outran FBDIV. Cause: leaky, mis-manufactured loads in delay cell reduced gain of delay element < 2 Solutions: increase L of load devices for higher gain add more VCO stages to reduce gain requirements Copyright, Dennis Fischette, 2004 93 PLL Problem Problem: VCO stuck at max frequency at poweron. Cause: PLL tried to lock before VDD was stable. Because VCO couldnt run fast enough to lock at low VDD, Vctl saturated. When VDD finally stabilized, Vctl = VDD, causing a maxed-out VCO to outrun FBDIV. Solution: maintain PLL RESET high until VDD is

stable to keep Vctl at 0V. Copyright, Dennis Fischette, 2004 94 PLL Problem Problem: VCO stuck at max frequency after changing power-modes. Cause: Feedback DIV could not run fast enough to handle VCO overshoot when locking to a new frequency or facing a reference phase step. Solutions: limit size of frequency steps increase speed of Feedback DIV Copyright, Dennis Fischette, 2004 95 PLL Problem Problem: PLL would not lock. Cause: Feedback DIV generated glitches causing PFD to get confused. Solution: add re-sampling flop to output of feedback DIV to remove glitches. Copyright, Dennis Fischette, 2004 96 PLL Problem Problem: PLL output clock occasionally skipped edges at low VCO frequencies Cause: VCO level-shifter had insufficient gain when VCO swing was close to Vt. Solutions: increase W of diff-pair inputs use low-Vt devices Copyright, Dennis Fischette, 2004 97 PLL Problem Problem: VCO jitter was huge at some divider settings and fine at others. Cause: Integration team connected programmable current sources backward. Solution: write accurate verilog model that complains when inputs are out-of-range. Copyright, Dennis Fischette, 2004 98

PLL Problem Problem: PLL jitter was poor at low freq and good at high freq. Cause: Vctl was too close to Vt at low frequency. Solution: Run VCO at 2X and divide it down to generate slow clocks. Copyright, Dennis Fischette, 2004 99 PLL Problem Problem: RAMDAC PLL had large accumulated phase error which showed up as jitter on CRT screen. Cause: PLL bandwidth was too low, allowing random VCO jitter to accumulate. Solution: increase bandwidth so that loop corrects before VCO jitter accumulates. Copyright, Dennis Fischette, 2004 100 PLL Problem Problem: PLL had poor peak-peak jitter, but good RMS jitter. Cause: digital VDD pin in package adjacent to PLLs analog VDD coupled digital VDD noise to analog VDD during certain test patterns. Solution: Remove wirebond for adjacent digital VDD pin. Copyright, Dennis Fischette, 2004 101 PLL Problem Problem: large static offset. Cause: designer did not account for gate leakage in LPF caps. Solutions: switch to thick-gate oxide caps switch to metal caps Copyright, Dennis Fischette, 2004 102 PLL Problem Problem: VCO period jitter = +/- 20%, modulated at a fixed frequency. Cause: Unstable V2I internal feedback loop caused by incorrect processing of stabilizing caps.

 Solutions: correct manufacturing of capacitors add more caps Copyright, Dennis Fischette, 2004 103 PLL Problem Problem: bandgap reference was stable in one process but oscillated in a different process with similar feature sizes. Cause: compensation caps for 2-pole feedback system with self-bias were too small. Solution: make compensation caps 3X larger. Copyright, Dennis Fischette, 2004 104 Uncle Ds PLL Top 5 List 5. Maintain damping factor ~ 1 4. VDD-induced VCO noise loop cant do the work for you 3. Leaky gate caps will cost you your job 2. Make FBDIV run faster than VCO 1. Observe VCO,FBCLK,REF,clkTree on differential I/O pins you cant fix what you cant see! Copyright, Dennis Fischette, 2004 105 Appendices Copyright, Dennis Fischette, 2004 106 Appendices Appendix A: Design for Test Appendix B: Writing a PLL spec Appendix C: Additional PLL material Appendix D: Paper References Appendix E: Monograph References Copyright, Dennis Fischette, 2004 107 Design for Test Copyright, Dennis Fischette, 2004 108 Design for Test Overview Measuring Jitter

 Analog Observation Probing Copyright, Dennis Fischette, 2004 109 Measuring Jitter: Power-Supply Noise Sensitivity Induce noise on-chip with VDD-VSS short need off-chip frequency source or on-chip FSM to control noise generator How to measure induced noise magnitude? Induce noise on board capacitively couple to VDDA hard to get it past filtering and attenuation how much makes it to PLL? VDDA inductance? wire-bond, flip-chip Copyright, Dennis Fischette, 2004 110 Routing: From PLL to Board Differential IO outputs highly desirable Types of IO use highest-speed available Divide VCO to reduce board attenuation only if necessary make divider programmable Measuring duty-cycle - Divide-by-odd-integer - Mux to select either true or inverted clock Minimize delay on-chip from PLL to IO Ability to disable neighboring IO when measuring jitter Avoid coupling in package and board Copyright, Dennis Fischette, 2004 111 General Test Hardware High-bandwidth scope: 4-6 GHz real-time $50-60k e.g. Agilent, Tektronix, LeCroy Differential high-speed probes: 3-6 GHz BW $3-6k Active pico-probes and passive (DC) probes for micro-probing PLL Avoid large GND loops on probes Copyright, Dennis Fischette,

2004 112 Jitter Hardware/Software Jitter Analysis tools: e.g. Wavecrest, Tek(Jit2), Amherst Design Jitter measurement types: Period jitter histogram Long-term jitter Cycle-to-adjacent cycle jitter Half-period jitter Jitter FFT - limited by Nyquist aliasing Scope memory depth Copyright, Dennis Fischette, 2004 113 Miscellaneous Jitter Measurements Open-loop vs. Closed-loop Jitter disable loop-filter does PLL jitter change? Mux Ref into PLL observation path for jitter calibration Is Ref jitter worse after coming from PLL compared to before it enters the chip? Observe end-of-clock tree for jitter and dutycycle distortion Observe Fbclk for jitter and missing edges Copyright, Dennis Fischette, 2004 114 Measuring PLL Loop Dynamics Modulate reference frequency, measuring longterm PLL jitter. Sweep modulation frequency to determine bandwidth and damping. e.g. Wavecrest Spectrum analyzer look for noise suppression in frequency range close to signal peak difficult if noisy setup Copyright, Dennis Fischette, 2004 115 Measuring Phase Error Hard to do! Fbclk available for observation? Need to acct. for Fbclk delay from PLL to IO depends on PVT. Solutions:

 route Fbclk off-chip to pkg and match input delay with Ref. Fbclk/Ref skew at pins ~ Terr at PFD. measure Terr on-chip send out narrow pulses narrow pulses disappear. measure Terr on-chip with A/D. Complex. mux Fbclk and ref into same path. Compare both to external reference. Copyright, Dennis Fischette, 2004 116 Analog Observation Analog observation IO pins for debug and characterization may force internal analog nets as well if bidirectional pin low-bandwidth requirements low MHz or kHz isolate analog nets with unity-gain buffer or resistor and pass-gates w/solid pull-down drive analog pins to known value when not in use tri-state analog pin for ESD leakage testing ESD protection (CDM and HBM) may cause IO leakage Copyright, Dennis Fischette, 2004 117 Probing On-chip If not flip-chip, then put probe pads on top-layer metal. Probe pad size >1um x 1um. Prefer > 2um x 2um. Place probe pad on a side-branch of the analog signal to avoid breaking wire with probe. Separate probe pads to allow room for multiple probes. FIB: can add probe pad, add or remove wires. need room and luck FIB: can FIB SOI flip-chip from back of wafer if enough room around lower-level wires. Copyright, Dennis Fischette, 2004 118 Writing a PLL Spec Copyright, Dennis Fischette, 2004 119

Spec Overview Area, physical integration Technology issues Power-supply voltage Performance metrics Logic interface Copyright, Dennis Fischette, 2004 120 Physical Integration Area, aspect ratio? What metal layers are available? Digital signal routing allowed over PLL? Where is PLL located on chip? Wire-bond or flip-chip? Copyright, Dennis Fischette, 2004 121 Semiconductor Process 90nm, 130nm, 180nm? Bulk vs. SOI? SOI body-ties? Nwell vs. twin-well? Epi substrate? Accumulation-mode capacitors? Gate-oxide thickness? Capacitance density and leakage. Dual-gate oxide available? Leakage. Poly density requirements? Low-Vt available? Resistor types? Poly? Diffusion? Copyright, Dennis Fischette, 2004 122 Power-Supply Separate analog VDDA? What voltage? 1.8V? 2.5V? Higher than core voltage? Separate analog VSSA? Wire-bond or flip-chip? Package Type? What type of VDDA filtering on board? Ferrite bead? What cap sizes? Min, max VDDA? DC variation? AC variation? Natural frequency (1/LC) of VDDA? Copyright, Dennis Fischette, 2004 123 Performance

 Reference clock frequency? Range? Min/Max VCO Frequency? Duty cycle? Period Jitter? Fixed jitter spec or pct of period? Cycle-to-adjacent cycle jitter spec? Half-cycle jitter spec? Copyright, Dennis Fischette, 2004 124 Performance Max Frequency overshoot while settling? Static phase error? Dynamic phase error? Loop bandwidth? Time to acquire initial lock? Time to re-acquire lock after frequency change? Power Dissipation? Copyright, Dennis Fischette, 2004 125 Logic Interface Reset available? PowerOK available? VCO/CP/R range settings allowed? Clock glitching allowed when switching VCO frequency ranges? Level-shift and buffer PLL inputs/outputs? Different power domains? Copyright, Dennis Fischette, 2004 126 Example Design Specs f(ref) = 125 MHz 8 < FBDiv < 16 1 GHz < f(vco) < 2 GHz > 0.7 not constant w/FBDiv 1 MHz < n/2< f(ref) /20 Pk-Pk Jitter < +/- 2.5% w/dVdd = 50mV Tlock < 10 uS FreqOvershoot < 15% w/1-ref-cycle phase step Static Phase Error < +/- 200 pS Icp mismatch < 50%?

New mpin---3229 New application password9223 module counter_load(count, load, clk, reset, data_in); output [3:0] count; input load; input clk; input reset; input [3:0]data_in; reg [3:0] count; always @ (negedge reset or negedge clk) begin if ( reset == 0) count <= 3'b0; else if (load == 1'b1) count <= data_in; else count <= count - 1; end endmodule Phase-locked loops are widely used in many communication systems for clock and data recovery or frequency synthesis. However, analog PLLs have to overcome the digital switch noise coupled with power through power supply as well as substrate induced noise. In addition, the analog PLL is very sensitive to process parameters and must be redesigned if the process is changed or migrates to next generation process. One advantage of a digital implementation is the inherent noise immunity of digital circuits. Another advantage of a digital design is its scalability and easy redesign with process changes or shrinks. Since analog blocks are present in a number of digital and mixed-signal ICs, their redesign is an important factor in the release of a new product. However, the performance requirements of analog blocks necessitates a complete redesign in a new process, thereby increasing the design cycle time. Reducing the amount of analog circuitry can improve the redesign time of these mixed-signal ICs. Due to above mentioned reasons, research in the area of digital equivalent implementations of analog and RF circuits is in great demand now. Phase-looked loops (PLLs) are important and often performance limiting building blocks in modern SoCs. They are used for clock generation and distribution, frequency synthesis, clock and data recovery, etc. Instead of "ahead" or "behind" comparison, a time-to-digital converter is used to measure the frequency difference accurately, which could greatly reduce the lock-in time. [2]. DESIGN OF LOW-JITTER 1-GHZ PHASE-LOCKED LOOPS FOR DIGITAL CLOCK GENERATION by Woogeun Rhee 1999 IEEE [3]. IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 38, NO. 2, FEBRUARY 2003 An All-Digital Phase-Locked Loop for High-Speed Clock Generation by Ching-Che Chung and Chen-Yi Lee

[4]. IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 39, NO. 5, MAY 2004 A Digitally Controlled PLL for SoC Applications by Thomas Olsson, Member, IEEE, and Peter Nilsson, Member, IEEE [5]. IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMSII: EXPRESS BRIEFS, VOL. 54, NO. 11, NOVEMBER 2007 An Ultra-Low-Power and Portable Digitally Controlled Oscillator for SoC Applications By Duo Sheng, Student Member, IEEE, Ching-Che Chung, Member, IEEE, and Chen-Yi Lee, Member, IEEE [6]. IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 43, NO. 1, JANUARY 2008 A Wide Power Supply Range, Wide Tuning Range, All Static CMOS All Digital PLL in 65 nm SOI Jos A. Tierno, Alexander V. Rylyakov, Member, IEEE, and Daniel J. Friedman, Member, IEEE THESIS REFERENCES: [T1]. RESEARCH AND DESIGN OF LOW JITTER, WIDE LOCKING-RANGE ALL-DIGITAL PHASE-LOCKED AND DELAY-LOCKED LOOPS, College of Graduate Studies University of Idaho by Feng Lin March 2000 [T2] January 01, 2011, A low power CMOS design of an all digital phase locked loop BY Jun Zhao,Northeastern University