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Background/Literature Study 1.0 Overview

This report highlights the relevant details which relates to the various configurations of CMOS adiabatic logic circuits utilizing 0.13 micron technology transistors. A comparison between conventional CMOS circuit and adiabatic circuit is emphasized below based on the power dissipation parameter. Also, introductory elements of the levels of abstractions necessary, logic gates used to form the circuits and the significance of adiabatic logic circuits in previous research are further illustrated. 1.1 Introduction

Few properties are taken into consideration to achieve the following goals of this thesis: lower dissipated power shorter delay smaller in size; utilizing 0.13 micron technology

Hence post-simulation data will include the following properties: fall time (tf)

It is the accommodated time for the output waveform to drop from 90% to 10% of its steady state value. It measures the responsive time of one transistor to another. The larger carrier mobility in NMOS transistor will record higher fall time. rise time ( t r ) It is the accommodated time for the output waveform to rise from 10% to 90% of its steady state value. Identical to fall time, it measures the responsive time of one transistor switching to another. The faster the whole cell responses, the lesser the time rise accommodated. propagation delay (tpd)

The average time accommodated by the fall time ( t PHL ) delay and rise time ( t PLH ) delay. By definition, the average propagation delay is the reciprocal to half the addition of fall time delay and rise time delay. The parameter extracted for calculation of propagation delay is both the input and output voltages. In short, the lesser the propagation delay, the more efficient the whole cell is. power dissipation (Pd)

Power dissipation represents power lost from a transistor or a whole cell. Two components of power dissipated recorded are Static Power Dissipation and Dynamic Power Dissipation. Known causes for power dissipation are further explained in detailed below in parasitic extractions.

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power delay product (PDP)

In digital logic circuits, the power delay product corresponds with the energy efficiency of a gate logic transistor circuit. It is the product of time delay and the dissipated power measured. The time delay points to the switching period which occurs when the gate logic switches from logic 0-1 or 1-0. The common power dissipation causes established are either current leakage or parasitic capacitance. 1.2 CMOS Circuit

Conventional CMOS circuit dissipates power during device switching. Dynamic power dissipation contributes the principal of power dissipation in a CMOS circuit configuration. The interchange of logic '0' to logic '1' establishes a path between the power source, Vdd, and the output node. The charge provided above is then grounded when the logic switches from '1' - '0' [4] The equation below depicts the total power dissipated to the ground:

where it is the product of the load capacitance at the output and Vdd at the power source voltage. With the equation above, the allowable parameters to vary the power dissipated lies on the Vdd and . Note that the diagram below utilizes Vdd as it power source for conventional CMOS

Figure 1.1: Conventional CMOS Inverter Logic Gate configuration [1]

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1.3 Adiabatic Logic Circuit

The adiabatic interchange is primarily for energy minimization during charging/discharge. The thermodynamic term of 'adiabatic' signifies a change in state occurring at zero loss or gain in heat. In the event of an adiabatic switching, all relevant nodes are charge/discharge at a constant current rate to suppress the dissipated power. [1] Another considerable attribute of adiabatic logic families is the lower generation of switching noise which is becoming one of the major factors in current digital and uniquely in mixed mode integrated circuits. [3] To realize the constant rate of supply current, an AC power supply is put into effect to ensure that the charging of the circuit are at certain adiabatic phases and the ensuing discharge is perform to recover the supplied charge. This method hence shows the relevancy and competency of an adiabatic logic circuit. The correlation between adiabatic and conventional circuit best defines the principals of adiabatic switching with the use of a time varying voltage source rather than a fixed voltage source. ;where is the time for the driving voltage to change from 0V to Vdd

[1]

The equation above equates the adiabatic logic is mathematical term where it is significantly clear that the energy dissipation can be minimized by decreasing the rate of switching transition. Note that the diagram below depicts utilizes two complementary voltage supply clocks or AC voltage source to perform adiabatic circuitry capabilities

Figure 1.2: Adiabatic CMOS Inverter Logic Gate configuration [1]

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As mentioned above in the statement, by contrasting conventional CMOS configuration with other adiabatic circuits, adiabatic capabilities are highlighted based on power dissipation. The table below is extracted based on a research compiled by the Department of Electronics, Carleton University, Ottawa, Canada. Logic Style 2N-2N2D ADL IAPDL DAPDL 2N-2P IPGL PAL PFAL CAL CMOS* Transistors 8 3 8 10 6 10 6 8 10 4 Clock Phase 2 4 2 2 4 4 2 4 1 1 Min Operational Frequency (Hz) 10K 10 10 10 100 100 10K 10 10K 10 Power Dissipation @ 100MHz 0.747 NA 2.98 2.75 0.766 0.311 0.375 0.337 0.657 2.74 [5]

Diode based adiabatic circuit

Transistor based adiabatic circuit

Figure 1.3: Comparison between adiabatic logic circuitry with conventional CMOS [5] 1.4 0.13 Micron Transistor Technology

The term 0.13 micron or 130nm exemplifies the channel length of the transistor devices in the adiabatic logic circuit configurations; the length between source and drain. The micron term is a commonplace when utilizing EDA tools to draw and formulate minimum sizes in circuit layout designs. One primarily advantage of micron rules is its efficiency utilization of every available area when compared to the lambda rule. The drawback to this however requires realignment if the designer choose to elevate the design into a more recent/different technology. Recent technology demonstrates the ability to scale the value down to 22nm, leading to the development System on Chip, integrating all components on a single chip which also consumes lesser power. 1.5 Levels of Abstraction

Figure 1.1 depicts the five levels of abstraction relevant in VLSI design process. All are equivalent of each other but at different complexity. The hierarchical characteristic from top to
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bottom shows increasing developmental period due to increased complexity; dealing with the design at channel length and width (layout level), while from bottom to top is the rise in manufacturing cost due to larger scale of materials used. This project will concentrate on the transistor and layout level.

Figure 1.1: Five levels of Abstractions 1.5.1 Layout Level A layout is used to fabricate a mask that enables the fabrication of a chip. An illustration below depicts its functional purpose:

Figure 1.4: Layout Functional Purpose [6]

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Hence its definition is a process to create an accurate physical representation of an engineering drawing that tally with the constraints imposed by the manufacturing process, design flow and the performance requirements shown feasible by the simulation. At the layout mask constructed above, the detailing level is at its principal with multiple layers like metal layers, metal contacts, wiring paths, diffusion and polysilicon layers are all evidently shown. With the employment of the logic circuits above, a set of design rules are in place to ensure and avoid misalignment which may cause possible electrical hazards. A Layout Versus Schematic applies to determine if the physical schematic represents the electrical schematic. The final step will be parasitic extraction whereby they primarily encompass [6]: a) Capacitance from a conductor to ground b) Capacitance between conductors c) Bulk resistance Therefore the parasitic components are calculated and slight modification is rendered to ensure that the parasitic will not cause failure in the design. Foundries which manufactures the layout masks requires that the layout mask drawn must adhere to the LVS (Layout Versus Schematic) and DRC (Design Rule Checking) constraints specific to a process (vendor native rules)[6]. 1.5.1.1 Design Rule Checker

The DRC performs only the physical layout reconciliation with the recommended pertaining design rules. The underlying parameters for DRC are the width and spacing rule since they exist at each layer. It therefore ensures enough margins for connectivity restriction to justify for variability that the parts used works appropriately [7]. 1.5.1.2 Layout Versus Schematic

The terms contemplates to a series of Electronic Design Automation (EDA) software endorsement to determine whether an integrated circuit layout matches to the original schematic or circuit diagram of the particular design. A LVS check is undergo since a DRC does not guarantee circuitry representation of the fabrication design. The checking is divided into a three point steps whereby the first is extraction, followed by reduction and comparison. Most cases recorded faults in the layout are shorts, open, component mismatch, missing or parameter mismatch [7]. 1.5.1.3 Parasitic Extraction

The calculation of parasitic effects is an indispensable phenomenon where it simply affects the overall performance and capability of a circuitry design. Common parasitic device parameters are parasitic capacitance, resistance and inductances are extracted to create an accurate analog model of the circuit. Further detailed simulations can imitate the actual digital and analog circuit responses and therefore determine whether the extra parasitic parameters allow the designed circuit to function.

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1.5.2 Transistor Level

Transistor level capitalizes on circuitry theory by manipulating various electrical/electronic components with the design to formulate a sheet of data by displaying the required output graph. Some of the existing software used at transistor levels is Simulation Program Integrated Circuit Especially (SPICE) while the different variants are HSpice, LTSpice and Pspice. At this operation level, stipulating the transistor model is important to determine the necessary parameters. The conventional ones are width-length channels, oxide layer thickness, and carrier mobility. Analysis and simulation run on the software compute the waveforms of either DC sweeps or a transient analysis. An illustration of an inverter circuit in Figure 1.5 using LTSPICE depicts a design at transistor level.

Figure 1.5: Example of an Inverter Circuit at Transistor Level drawn using LTSPICE 1.6 Further Research on Applicability of Adiabatic Logic Circuit Configuration

The design and compilation of different families of adiabatic logic circuit is demonstrated by a 8x8 adiabatic quasi-static CMOS Multiplier. The logic circuit in question is the Adiabatic QuasiStatic CMOS circuit under the diode based adiabatic circuit family. A pictorial of AqsCMOS Inverter

[8] Figure 1.6: An AqsCMOS Inverter [8]

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This research was propelled by The Chinese University of Hong Kong Department of Electronics Engineering. As seen below, the result tabulated clearly highlights the robustness of adiabatic logic circuit with power dissipation versus frequency.

[8]

Figure 1.7: Power Vs Freq Comparison of AqsCMOS Multiplier and Static Multiplier Another important factor whilst designing of transistor is the heat dissipation which is another crucial parameter. Since SoC (System on Chip) is becoming more apparent, smaller area with more transistors, the heat dissipated has to be kept at a minimal value to avoid from overheating consequences. This design therefore able to grasp and borne a solution for designers for lower temperature designs since lesser power is required.

[8]

Figure 1.8: Power vs Temp Comparison of AqsCMOS Multiplier and Static Multiplier
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References

[1].

Nazrul Anuar,Yasuhiro Takahashi, Toshikazu Sekine (2009). 4-Bit Ripple Carry Adder of Two-Phase Clocked Adiabatic Static CMOS Logic: A Comparison with Static CMOS. 2nd ed. Faculty of Engineering Gifu University, Japan 501-1193: 2009 IEEE. p65-68. Nazrul Anuar, Yasuhiro Takahashi and Toshikazu Sekine (2009).Fundamental Logics Based On Two Phase Clocked Adiabatic Static CMOS Logic. Department of Electrical and Electronic Engineering Gifu University, 1-1 Yanagido, Gifu-shi 5011193 Japan: 2009 IEEE. p503-506. Hamid Mahmoodi-Meimand' and Ali Afzali-Kusha2 (Oct. 31- Nov. 2, 2000). Low-Power, Low-Noise Adder Design with Pass-transistor Adiabatic Logic. Department of Electrical and Computer Engineering, University of Tehran, Iran: The 12th International Conference on Microelectronics. p61-64. Luis F. Cisneros-Sinencio, Alejandro Diaz-Sanchez, Jaime Ramirez-Angulo, Carlos A. Gracios-Marin (2009). Floating-Gate Energy Recovery Logic. Puebla Institute of Technology Puebla, Puebla, Mexico, Klipsch School of Electrical and Computer Engineering, : 2009 IEEE. p519-522. Muhammad Arsalan, student member IEEE, and Maitham Shams (2004).Comparative Analysis of Adiabatic Logic Styles. Department of Electronics, Cudeton University, Ottawa, ON. KIS 586, Canada.: 2004 IEEE. p663-668. Phillip Allen ( May 13, 2004). THE PRACTICE OF ANALOG IC DESIGN. Schlumberger Professor of ECE Georgia Institute of Technology: IEEE Santa Clara Valley Solid-State Circuits Chapter. p1-46. Dr. Lynn Fuller (12-31-2007). CMOS VLSI DESIGN. Microelectronic Engineering Rochester Institute of Technology 82 Lomb Memorial Drive Rochester, NY 14623-560: ROCHESTER INSTITUTE OF TECHNOLOGY MICROELECTRONIC ENGINEERING. p1-50. W.S. Mak, C.F. Chan, K.W. Cheung and C.S. Choy (May 28-31, 2000,).An 8x8 Adiabatic Quasi-Static CMOS Multiplier. IEEE International Symposium on Circuits and Systems,: IEEE 2000. p553-556.

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