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ADDER IN FPGAAIM: To design, synthesize, simulate pipelined serial and parallel adder to add 8 numbers of 12bit size each in 2s complement and to implement and program the same in FPGA. TOOLS REQUIRED :SOFTWARE:XILINX ISE 9.1iHARDWARE:XILINX - Spartan kit XC3S400TQ144, Power supply Adapter, Parallel portcable, FRC connector, AU card - I THEORY: SERIAL ADDER:Serial Adder uses a simple adder and constructs the sum sequentially. At a timet, the Sun is calculated and the carry is stored in a register. At time t+1, the sum uses carry[t] tocalculate a new sum.Carry [ t + 1] = A [ t +1].B[ t + 1 ] . ( A [ t + 1 ] + B [ t + 1 ] )Sum [ t + 1 ] = Carry [ t + 1 ] . ( A [ t + 1 ] + B [ t + 1 ] + c [ t ] )+ A [ t + 1 ] . B [ t + 1 ] . c [ t ]The two inputs to the adder are stored in a n-bit register. Sum bit is stored in an -bit register. Addition is commenced by clearing the carry register. Then the operands areserially applied to the inputs of the adder. The sum and carry array are advantageous because these delays determine the fastest clock frequency at which the adder can operate.Bit serial architecture has been used widely for a variety of signal processingapplications, especially with technologies in the 2-5 micro range. Reasons for using bit serialarchitecture include reduced signal routing, reduced module sizes and higher speed operation.PARALLEL ADDER:An n-bit parallel adder may be constructed by cascading n 1-bit adders. This iscalled Ripple Carry Adder. The inputs are n bit A and B values. The carry signal of stage i isfed to the C signal of the stage i+1 and the sum signal forms the n bit output. The nth bit of thesum indicates whether overflow has occurred. Because the carry output signal is u sed in theg e n e r a t i o n o f t h e s u m , t h e s u m w i l l b e d e l a y e d w i t h r e s p e c t t o t h e c a r r y . I n c a s e o f n - b i t parallel adder, the carry delay has to be minimized because the delay associated the adder isT n = nT c Where T n is the Total Add Time, n is the number of stages and T c is the delay of one carry stage. To optimize the Carry delay, the inverter at the output of the carry gate can beomitted. In this case, every other stage operates on complement data. PROGRAM:

Verilog code for serial adder module serial_adder(clk,addr,load,clear,data_in,calc,result);input clk,clear,calc,load;input [2:0]addr;input [11:0]data_in;output reg [11:0]result;reg [11:0]ram[7:0];reg [11:0]temp;always@(negedge clk)beginif(clk)temp = ram[0] + ram[1];temp = (temp + ram[2]);temp = (temp + ram[3]);temp = (temp + ram[4]);temp = (temp + ram[5]);temp = (temp + ram[6]);temp = (temp + ram[7]);endalways@(posedge clk)beginif(~clear)beginram[0]=12'b0;ram[1]=12'b0;ram[2]=12'b0;ram[3]=12'b0;ram[4]=12'b0;ram[5]=1

2'b0;ram[6]=12'b0;ram[7]=12'b0;endelse if(~load)beginresult=data_in;ram[addr] = data_in;endelse if(~calc)result = temp;elseresult = ram[addr];endendmodule Verilog code for parallel adder

module parallel_adder(clk,addr,load,clear,data_in,calc,result);input clk,clear,calc,load;input [2:0]addr;input [11:0]data_in;output reg [11:0]result;reg [11:0]ram[7:0];wire [11:0]temp;always@(posedge clk)beginif(~clear)beginram[0]=12'b0;ram[1]=12'b0;ram[2]=12'b0;ram[3]=12'b0;ram[4]=12'b0;ram[5]=1 2'b0;ram[6]=12'b0;ram[7]=12'b0;endelse if(~load)ram[addr]=data_in;endassign temp=ram[0]+ram[1]+ram[2]+ram[3]+ram[4]+ram[5]+ram[6]+ram[7];always@(posedge clk)beginif(~load)result=data_in;else if(~calc)result=temp;elseresult=ram[addr];endendmodule

DESIGN AND IMPLEMENTATION OF MULTIPLIER IN FPGAAIM: To design, synthesize, simulate pipelined multiplier to multiply two 8 bit signednumbers in 2s complement and to implement and program the same in FPGA. TOOLS REQUIRED :SOFTWARE:XILINX ISE 9.1iHARDWARE:XILINX - Spartan kit XC3S400TQ144, Power supply Adapter, Parallel portcable, FRC connector, AU card - I THEORY: MULTIPLIER:In many digital signal processing applications such as correlations,convolutions, filtering and frequency analysis, one needs to perform multiplication.Multiplication algorithms will be used to illustrate methods of designing different cells so theyf i t i n t o a l a r g e r s t r u c t u r e . I n o r d e r t o i n t r o d u c e t h e s e d e s i g n s , s i m p l e s e r i a l a n d p a r a l l e l multipliers will be introduced. The appropriate tests should be consulted for more d efinitesystem architecture. The most basic form of multiplication consists of forming the products of two positive binary numbers. This may be accomplished through the traditional technique of Successive Addition and shifts in which each additive is condit ional on one of the multiplier bits. The multiplication process may be viewed to consist of the following steps:1. Evaluation of Partial Products,2. Accumulation of the shifted partial productsIt should be noted that binary multiplication is equal to partial AND operations.Thus evaluation of partial products consists of the logical AND of the Multiplicand and therelevant Multiplier bit. Each column of partial products must then be added and if necessaryany carry values is passed to the next column. There ar e a number of techniques that may beused to perform multiplication. In general the choice is based on the factors such as speed,throughput, numerical accuracy and area. As a rule, multiplication may be classified by the format, in which the words are accessed namely,1 . S e r i a l F o r m 2. Serial / Parallel Form3 . P a r a l l e l F o r m

PROGRAM:Verilog code for multiplier

module multiplier(clk,addr,load,clear,data_in,calc,result);input clk,clear,calc,load;input addr;input [7:0]data_in;output reg [15:0]result;reg [7:0]ram[1:0];always@(posedge clk)beginif(~clear)beginram[0]=8'b0;ram[1]=8'b0;endelse if(~load)ram[addr]=data_in;endalways@(posedge clk)beginif(~load)result={8'b0,data_in};else if(~calc)result= multiply_8x8_2sC (ram[0],ram[1]);elseresult={8'b0,ram[addr]};endfunction[15:0] multiply_8x8_2sC;input[7:0] a,b;reg[7:0] a_mag,b_mag;reg[14:0] y_mag;reg[14:0] y_neg;begincase (a[7])0: a_mag = a[6:0];1: a_mag = 128 - a[6:0]; // max(a_mag) = 128, thus 8 bitsendcasecase (b[7])0: b_mag = b[6:0];

1: b_mag = 128 - b[6:0];endcasey_mag = a_mag * b_mag; // max(y_mag) = 16384, thus 15 bitsif ((a[7] ^ b[7]) & (y_mag != 0)) // if (a * b) is -ve AND non-zerobegin// y_mag >=1, <= 16256, thus need only 14 bitsy_neg = 32768 - y_mag[13:0]; // max(y_neg) = 32767, thus need 15 bitsmultiply_8x8_2sC = {1'b1,y_neg};endelsemultiply_8x8_2sC = y_mag;endendfunctionendmodule