A Design Methodology for Logic Paths Tolerant to Local Intra-Die Variations

Daniel Iparraguirre-C rdenas, Jos L. Garca-Gervacio and Vctor Champac a e

National Institute for Astrophysics, Optics and Electronics (INAOE) Puebla, M xico e Email: {iparra, jgarcia, champac}@inaoep.mx key of this work is the fact that intra-die variations become averaged in an array of components, in such a way that relative performance deviation becomes reduced in comparison to a single component. This fact suggests the implementation of new digital structures with a library of new gates, in which single transistors are replaced with arrays of transistors in a parallel, serial or mixed fashion. An adequate structure selection and transistor sizing allows achieving a signicant variability reduction, at the expense of more area for the given logic path. This paper is organized as follows: Section II presents the proposals core. Section III describes the library of structures used including electrical characteristics of each one. Section IV shows the application of the proposed methodology for the design of logic paths, as well as the achieved improvements by simulation results. Finally, Section V gives the conclusions of the present work. II. T HE PROPOSAL S
CORE

AbstractProcess variations have become a critical issue inuencing the performance of nanometer digital circuits at gigascale integration; variations are classied in two types: inter-die and intra-die. Whereas inter-die variations affect the deviation of performance distribution in a lot of chips, intradie variations affect the media of performance distribution. The present work proposes a new design methodology for designing logic paths tolerant to local intra-die variations. A library of transistor structures with different degree of delay variability is dened. Transistors from the logic gates are replaced with these structures according to selection criteria to improve the delay tolerance to process variation on logic paths. Delay variability is reduced at the expense of circuit area. Results show a signicant variability reduction for a moderate increment of area and power consumption.

I. I NTRODUCTION Process variability has been a typical issue in analog design, because circuit accuracy becomes highly dependent on the nal electrical and physical characteristics in every transistor of the analog circuit. In contrast, only recently process variability has become a problematic issue in digital design. A synchronous clocked digital system, which is one of the subjects of the present work, contains a number of logic paths whose propagation delays determine the system performance. According to Bowman [1], inter-die variability directly affects the deviation of circuits performance, whereas intra-die variability affects the media. This has signicant consequences for the digital systems, because intra-die variations, which were ignored in the past, have become signicant in nanometer technologies. There are three different general design approaches for dealing with process variations: compensation techniques, statistical design and robust design. Several compensation techniques have been developed until today [2], [3], [4], which adjust propagation delays according to a certain estimation and a control circuitry. They are typically suitable for inter-die and global intra-die variations. On the contrary, little effort has been made for achieving an adequate methodology for robust design, that is, digital structures tolerant to process variations by themselves, without intervention of any compensation scheme. Statistical design for digital circuits and gate-sizing techniques have also been investigated [5][6]. The scope of the present work is to generate a design methodology for robust digital design oriented to reduce the impact of local intra-die process variations. The fundamental

The present design proposal is based on the use of transistor structures, which are intended to replace single transistors in certain gates of the logic path under analysis. The structures average variation effects from single transistors, resulting in improved delay variability. Design methodology involves identifying and replacing the elements inside the path that provide the highest contributions on propagation delay variability; the applied structures are sized in order to make the new path matching the original propagation delay. Figure 1 depicts the design proposals core. The inverter at the shown logic path has been selected for redesign, so the original topology is replaced by two structures, for the NMOS and PMOS section respectively, in which two serial transistors constitute the N structure and two parallel transistors make up the P structure. These structures are selected according to certain design requirements and constraints. The secondary effect of this replacement is a modication of the inverter input capacitance, modifying the load capacitance for the previous stage; that implies a further structure replacement or resizing at the previous stage, in order to maintain the original path propagation delay. Arising from the above example, the main proposal characteristics are the following: The structures are essentially arrays in serial, parallel and mixed fashion, belonging to a structure library.

978-1-4244-1684-4/08/$25.00 2008 IEEE

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... ... ... ...

... ... ...

Array 1 Array 2A

Array 3B

Array 3C Array 2B Array 3D

... ...

Array 3A

Original topology

New topology

Array 4A

Array 4E

Fig. 1. Structure replacement process in a path. The new topologies provide a more consistent performance that improves the paths robustness.

Array 4B

Array 4F

Channel width W is the only parameter to be varied when the structure is sized while channel length L remains having the minimum value. to the minimum value. Area and power consumption are the penalization. It is up to the designer to specify the resource constraints to be afforded, as well as the desired variability reduction. The proposed methodology is applied to digital circuits implemented from the TSMC 0.18m technology. The results presented in this work show the feasibility of the proposed methodology.

Array 4C

Array 4G

Array 4D

Array 4H

Fig. 2.

Nomenclature, schematics and layout of the library structures.

III. T HE STRUCTURE

LIBRARY

The library, which is the core of the current proposal, consists of a set of transistor structures conveniently characterized for the output (drain-source) resistance and input (gate) capacitance. Figure 2 shows the structures, their schematic representations and their layout geometries. The structures are basically built from parallel and serial arrangements. All transistors inside the structure are sharing the same W , which is called structure width. A. Single Transistor The equivalent resistance and the equivalent input capacitance for the single transistor are dened by equation (1). KR R1 = W and Cin = KC W (1)

Variabilities for W and L have different expressions, since they only depend on L and W respectively, rather than device area WL. The expressions are given by (3). l (W ) = aW L and l (L) = aL W (3)

Considering that W is the only design parameter and for xed channel length, from the previous expressions (2-3) can be obtained an expression for the total local intra-die output resistance variability for the single transistor, as shown in (4). l (R1 ) = 1 W2 aR1 W + aR2 (4)

where aR1 merges the effect of L, Vto , tox and 0 variations, and aR2 considers only variations on W. B. Transistor structures A methodology similar to single transistor can be developed for serial, parallel and mixed structures getting its corresponding variability l (R) as shown in table I. Parallel structures share the same bias conditions, since their terminals are connected at the same respective nodes; so, all of them are modeled like identical components, according to the singletransistor case. For serial transistors, they are working at different bias regimes: the top transistor is saturated while remaining transistors are working at the linear region; this

Where KR and KC are the resistance and the input capacitance respectively for the unitary-width transistor. SMOS model [7] [8] states that local intra-die variations are inversely proportional to transistor dimensions. In such a sense, local intra-die deviations (l ) for Vto , tox and 0 represented by P have the form given by (2), where aP is a coefcient dependent on the current technology: l (P ) = aP WL (2)

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TABLE I E QUIVALENT STRUCTURE WIDTH WITH RESPECT TO THE SINGLE

TRANSISTOR FOR STRUCTURES OF THE SAME OUTPUT RESISTANCE . aR1 = 0.8, aR2 = 0.2 AND r = 0.7.

TABLE II BSIM PARAMETER MEDIAS AND INTRA - DIE DEVIATIONS FOR A MINIMUM - SIZED TRANSISTOR .
0.3725327 -0.3948389 4.10E-9 4.60E-7 1.80E-7 259.5304169 109.9762536 l 0.08 0.037 4.10E-10 3.60E-8 1.80E-8 9.7 9.4 8.53E-10 6.28E-10 8.53E-10 6.28E-10 1E-12 1E-12 l 7.6E-11 7.6E-11 7.6E-11 7.6E-11 9.1E-14 9.1E-14

Struc. 4A 3A 2A 4B 1 3B 4C 4F 3C 4D 4E 2B 4G 3D 4H

Equivalent structure width 0.25W 0.333W 0.5W 0.386W W 0.63W 0.706W 1.033W 1.2W 0.85W 0.85W 1.7W 1.9W 2.4W 3.1W

l (R)
1 0.8W + 0.8 W2 1 0.8W + 0.6 W2 1 0.8W + 0.4 W 2 0.917 0.8W + 0.518 W2 1 0.8W + 0.2 W 2 0.861 0.8W + 0.318 W2 0.865 0.8W + 0.283 W2 0.641 0.8W + 0.194 W2 0.597 0.8W + 0.167 W2 0.551 0.8W + 0.235 W2 0.551 0.8W + 0.235 2 W 0.551 0.8W + 0.118 W2 0.401 0.8W + 0.105 2 W 0.378 0.8W + 0.083 W2 0.288 0.8W + 0.065 2 W

W =1 l (R) Cin 1.265 1.183 1.095 1.052 1 0.963 0.900 0.637 0.587 0.570 0.570 0.528 0.381 0.355 0.268 1 1 1 1.54 1 1.89 2.82 4.13 3.6 3.4 3.4 3.4 7.6 7.2 12.4

Vton Vtop tox XW XL Xu0n Xu0p

Xcgd0n Xcgd0p Xcgs0n Xcgs0p Xcgb0n Xcgb0p

0 in 1 CL2 5 inv. CL3 4 inv.

CL1 3 inv.

Fig. 3.

Generic logic path at gate level.

B. Design procedure leads to dene an additional coefcient, r, indicating the ratio between the bottom and top transistor equivalent resistances. Table I shows the output resistance variabilities obtained with the developed expressions for each structure. Wvariations to be 20% of total variations [9] are considered. This gives aR1 = 0.8 and aR2 = 0.2. A value of 0.7 is assumed for r [10]. Equivalent structure width is the W value of the transistor in the structure in order to have the same output resistance of the single transistor structure. In table I all resistance variabilities are normalized to the single transistor of unitary width; variability properties in every structure comes from the combination of variabilities at all transistors inside. The items were arranged by decreasing resistance variability. IV. PATH A. Considerations The library structures are used for replacing single transistors inside the gates. The nomenclature adopted for the new implementation is: The stages are referred by their NMOS and PMOS current branches, considering n NMOS structures for the rst branch and p PMOS structures for the second branch; the numbering at both branches are from GND and VDD to the output node. [N-structure 1]-[N-structure 2]-...-[N-structure n]/[Pstructure 1]-[P-structure 1]-...-[P-structure p] Aspects inuencing cell replacement: 1) The local contributions on variability are quadratical, so the largest improvement on variability is reached when the maximum local variability in the path is reduced. 2) Every stage has a replacement tail. As suggested from gure 1, the replacement at a certain stage entails further replacements at previous stages in order to compensate changes on load capacitances. Because of this the last stages in the path are usually the rst to be considered for improvement.
DESIGN

1) Find propagation delay media () and variability (l ) in the path, as well as for each gate. 2) Determine the stage to be improved. Give preference to: The last stages. Stages having the largest variability imbalance. Stages having the largest local variabilities. 3) Make structure replacements on the selected stage, in order to reach the expected variability improvement, regarding cell height constraints, transistor cost, stages input capacitance and the new stage propagation delay. 4) Make structure replacements at previous stages (replacement tail), regarding the same issues from previous step. 5) Feed the new implementation, as well as the expected structure widths, on the simulation software, in order to: Find the new widths (HSPICE Optimizer). Obtain the new propagation delay variabilities (Monte Carlo Analysis) and power consumption. 6) Evaluate the simulation results and determine whether variability requirements were met. C. Design example: A generic logic path The above procedure has been applied to several topologies with positive results. Figure 3 shows the gate-level schematics of one of those topologies. This one contains an inverter, a NAND and a NOR gate, as well as 3 external capacitances equivalent to 3, 5 and 4 symmetric inverters of double the minimum size (Wn = 0.92m Wp = 2.45m), respectively. Table III shows performance characteristics for the original path, applying local intra-die variabilities shown in Table II. The following conclusions can be extracted from here: Last stage, involving the NOR gate, presents the highest imbalance on low-to-high and high-to-low propagation delay variability. Last stage presents the highest local variability. Therefore, according to the rst criteria design procedure will work primarily on the third stage (NOR gate).

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TABLE III S TRUCTURE SIZES AND PROPAGATION DELAY VARIABILITIES FOR THE ORIGINAL LOGIC PATH .
Stage 3 Stage 2 Stage 1 1 / 1-1 1-1 / 1 1/1 0.53 1.35 0.92 NMOS size (m) 2.84 2.02 2.45 PMOS size (m) TP HL (ps) TP HL 3 (ps) TP LH 2 (ps) TP HL 1 (ps) 420.7 179.9 160.2 80.6 29.6 20.8 12.4 7.15 11.54% 7.72% 8.87% 7.04% 4.94% 2.94% 1.70% TP LH (ps) TP LH 3 (ps) TP HL 2 (ps) TP LH 1 (ps) 401.7 184.6 134.6 82.6 18.2 10.6 9.60 5.40 5.76% 7.13% 6.54% 4.53% 2.65% 2.39% 1.34% 25.36 Area (m2 ) 475 Power (W )

TABLE IV S TRUCTURE SIZES AND PROPAGATION DELAY VARIABILITIES FOR THE IMPROVED LOGIC PATH .
Stage 3 Stage 2 Stage 1 3D / 1-2A 1-2A / 3B 1 / 3B 1.33 1.43 1.62 2.03 1.64 1.75 TP HL (ps) TP HL 3 (ps) TP LH 2 (ps) 417.1 200.9 147.5 16.5 9.92 8.91 4.94% 6.04% 3.97% 2.38% 2.14% TP LH (ps) TP LH 3 (ps) TP HL 2 (ps) 415.2 192.4 126.1 17.8 10.9 7.24 5.67% 5.74% 4.29% 2.63% 1.74% 34.6 Area (m2 ) 613

l l / l /TP HL

l l / l /TP LH

NMOS size (m) PMOS size (m) TP HL 1 (ps) 68.7 4.30 l 6.25% l / 1.03% l /TP HL TP LH 1 (ps) 96.72 6.40 l 6.62% l / 1.54% l /TP LH Power (W )

V. C ONCLUSIONS
0

in

C L1 3 inv. 1

C L2 5 inv.

C L3 4 inv.

Combination 1/3B Wn = 1.62 um Wp = 1.75 um

Combination 1-2A/3B Wn = 1.43 um Wp = 1.64 um

Combination 3D/1-2A Wn = 1.33 um Wp = 2.03 um

The above implementations and performance results have shown the effectiveness of the proposed design methodology on reducing variability effects at logic paths. A careful study of gates and delays characteristics is a key factor to perform an adequate structure selection and sizing. Because of the amount of freedom degrees (stage propagation delays, structure sizes), there are several implementation alternatives for a given path. It is up to the user to establish the most important characteristics and constraints, like area and power consumption, in order to select the adequate combination. R EFERENCES
[1] K. Bowman, S. Duvall and J. Meindl, Impact of Die-to-Die and WithinDie Parameter Fluctuations on the Maximum clock Frequency Distribution for Gigascale Integration, IEEE Journal of Solid-State Circuits, vol. 37, pp. 183-190, Feb. 2002. [2] J. Tschanz et al, Adaptive Body Bias for Reducing Impacts of Die-to-Die and Within-Die Parameter Variations on Microprocessor Frequency and Leakage, IEEE journal of Solid-State Circuits, vol. 37, pp. 1396-1402, Nov. 2002. [3] Maryam Ashouei, Muhammad M. Nisar, Abhijit Chatterjee, Adit D. Singh, Abdulkadir U. Diril , Probabilistic Self-Adaptation of Nanoscale CMOS Circuits: Yield Maximization under Increased Intra-Die Variations, 20th International Conference on VLSI Design (VLSID07), pp.711 - 716, IEEE, 2007. [4] J. Tschanz et al, Effectiveness of Adaptive Supply Voltage and Body Bias for Reducing Impact of Parameter Variations in Low Power and High Performance Microprocessors, IEEE Journal of Solid-State Circuits, vol. 38, pp. 826-829, May 2003. [5] J. Zhang, M. Styblinski, Yield and Variability Optimization of Integrated Circuits, Kluwer Academic Publishers, 1995. [6] M.R. Guthaus et al., Gate Sizing Using Incremental Parameterized Statistical Timing Analysis, International Conference on ComputerAided Design, 2005. [7] C. Michael and M. Ismail, Statistical Modeling for Computer-Aided Design of MOS VLSI Circuits, Kluwer Academic Publishers, 1993. [8] M. Pelgrom, A. Duinmaijer and A. Welbers, Matching Properties of MOS Transistors, IEEE Journal of Solid-State Circuits, vol. 34, pp. 1433-1440, Oct. 1989. [9] K. Bernstein et al., High Speed CMOS Design Styles, Kluwer Academic Publishers, 1999. [10] J. Rabaey, A. Chandrakasan and B. Nikolic Digital Integrated Circuits - A Design Perspective, Pearson Education, Inc., 2003.

Fig. 4.

Schematics for the new implementation.

Furthermore, second criteria involves to improve the TP HL variability of stage 3 at the expense of the TP LH variability of the same stage. This involves replacing the N transistor with serial structures and the P with parallel structures, in order to improve robustness for the high-to-low transition at the expense of the low-to-high transition. Combination 3D/12A (see g. 4) has been selected for such a task. New input capacitance of the NOR gate is expected to be 2.5 times the original; however, the presence of the external capacitance (5 inverters) makes the new total capacitance to be only 1.25 times the former one. This increment can be easily managed by a moderate improvement on the NAND gate, so the alternative 1-2A/3B (see g. 4) became selected. A similar argument leads to a little change on the inverter, by using the 1/3B combination. The complete implementation is displayed at Figure 4. Resulting implementation is fed into Hspice Optimizer. The simulation results are shown in Table 4. A fairly improvement in process tolerance has been reached (61% of the original variability), along with a moderate increment on power dissipation (27%) and area (36%). Further improvement could be made using others replacement structures at the expense of area and power consumption.

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