A Yield-Optimized Latch-Type SRAM Sense Amplier

Bernhard Wicht , Thomas Nirschl , Doris Schmitt-Landsiedel now with Texas Instruments, Freising, Germany Inneon Technologies, Munich, Germany Technical University Munich, Germany b-wicht@ti.com Abstract
A yield analysis of a latch-type voltage sense amplier with a high-impedance differential input stage is presented. It quanties the impact of supply voltage, input dc level, transistor sizing and temperature on the input offset voltage. The input dc level turns out to be most signicant. Also an analytical expression for the sensing delay is derived. Experimental results in 130nm CMOS conrm that the yield can be signicantly improved by lowering the input dc voltage to about 70% of the supply voltage. Thereby, the offset standard deviation decreases from 19mV to 8.5mV without effecting the delay which is measured to be 119ps at 1.5V supply. point ( (SO) = (SON)). In the presence of mismatch and noise a wrong output signal can develop for small input voltage differences. This paper investigates the design issues for this type of sense amplier to ensure a fast and correct decision even for small input signals. The transient behavior, shown in Fig. 2 (at a large value for better visibility), consists of three phases. The of enable signal EN starts the operation by turning on M9. Immediately an operation current begins ow and pulls down node com. Successively the input transistor pair M5, M6 starts to discharge SO, SON. With a voltage difference between the inputs, the drain currents of M5, M6 will be different. This current imbalance causes different discharge speed at SO, SON. So an increasing output difference develops. The output nodes are precharged to before activating the amplier and M2, M4 remain at turned off until the output voltage reaches the transition from phase 1 to phase 2. Now strong positive feedback enhances the output voltage difference starting from an initial value as marked in Fig. 2. The latching completes during a third phase where one n-channel transistor is cut off. Then the current ow stops and the whole sense amplier does not dissipate static power.

1.

Introduction

Even though the conventional latch based on two crosscoupled inverters is widely used as a sense amplier, it always requires some decoupling at its input. This drawback does not occur for the latch circuit shown in Fig. 1 because of a high-impedance input differential stage. It was introduced by Kobayashi et al. in 1993 [1]. As senseamplier-based ip-op the circuit has been reported to be one of the fastest in recent VLSI designs [2]. Due to its high-impedance input it has recently been used as a second stage in a current-sensed SRAM operating down to 0.7V [3]. The most critical point of latch-type sense ampliers is that once the decision process has started, it does not recover unless the circuit is reset to the metastable
VDD
M7 M2 M4 M8

2. Delay Analysis
It is assumed that an input dc voltage is applied to input INP while INN receives a lower input voltage of . This causes output SO to approach

2V

EN

M2 turns on
1.5V

Vo

V thp V out
SO

SO
M1 M5 M3 M6

SON

M1 turns off

1V

0.5 V DD
SON

0.5V

INN com
M9

INP
0

com

to

tlatch tVSA

100ps

150ps

200ps

Io

EN

Phase 1 Phase 2

Phase 3

150

100

130

Delay tVSA / ps

CL = 4fF

Delay / ps

110

VDD = 1.0V, Vin = 10mV VDD = 1.0V, Vin = 70mV VDD = 2.0V, Vin = 10mV VDD = 2.0V, Vin = 70mV

80

tVSA = to + tlatch
60

/ ps

90

40

tlatch

220 170 120 70

-55C
0.5m 0.3m 1m 0.3m

V D D = 1.5V,

V IN = 50mV

140C 27C

70

20

to
0.8 1 1.2 1.4 VINDC / V 1.6 1.8 2

50 0.6

0.8

1.2

1.4

1.6

1.8

VINDC / V

0 0.6

VSA

W / L (M9)

1m 0.12m

3m 0.3m

during the decision and SON to go to zero. For pure voltage sensing the sense amplier is usually connected to the . bitlines with a potential near supply, i.e., However, the power consumption during write recovery can be signicantly reduced for bitline voltages lower than . In an application as a second stage of a current is determined by the rst stage sense amplier and can become nearly any value between 0V and . Fig. 3 shows how the sensing delay depends on . and The speed increases for higher supply voltage larger input voltage difference . Obviously there is does not get below apno speed penalty as long as proximately 60% of . It even slightly decreases and reaches a minimum. on the speed The inuence of , and can be analyzed by estimating the total delay according to Fig. 2 as the sum of the delay in phase 1 and 2, . The delay represents the capacitive discharge of the output load capacitance (at SO, SON) until the rst p-channel transistor turns on. Since the drain current difference between M5 and M6 is small, their current can be approximated by . The second term, , is the latching delay of two cross-coupled inverters [4]

Fig. 2: ). Assuming M9 in linear region and M5, M6 in saturation, can be approximated by

(4)

m,eff

(1)

with the effective transconductance of both inverters, rep resented by m,eff . The latch delay depends on the initial difference between SO and SON at given by (differential stage)

Eqn. (3) explains the impact of various parameters. As can be expected, the total delay is directly proportional to the output load capacitance . Only depends on the input difference resulting in higher total speed for larger (as in Fig. 3). Fig. 4 shows the total delay and its components and as a function of . In rst order is proportional to the square of (Eqn. (4)). For reduced the delay of the rst phase increases because smaller bias current slows down the discharge at both output terminals. On the other hand, Eqn. (2) shows that a delayed discharge with smaller results in an increased initial voltage difference at the end of the rst phase. Hence, decreases due to the inverse dependence on expressed by Eqn. (1). As a consequence, and cancel to some extent. dominates the delay due to For small values of very small . These results match well with the simulated curves of Fig. 3 and prove that the sensing speed is almost at the input of the insensitive to the bias voltage . sense amplier as long as So far, a xed transistor sizing is assumed. Indeed there is low inuence of the ratio on the performance, ex cept for the switch transistor M9 which basically determines the speed (Fig. 5). In 130nm CMOS a sizing of is appropriate regarding area and off-current.

3. Yield Analysis
(2) To ensure a correct decision, it is essential that the circuit is not activated until the input voltage difference is large enough. On the other hand, for a fast read operation the sense amplier should be enabled at the smallest possible input difference. Due to local variations mismatch occurs, causing the circuit to become slightly asymmetrical. This imbalance can be represented by an offset input voltage difference . Only for values of larger than this offset the circuit ips in the right direction. Otherwise the operation fails. Applied to a certain

with the technology constant and the threshold voltage of M2, M4. The nal sensing delay becomes

m,eff

(3)

The output swing can be replaced by ( ) if an absolute threshold is given (see

100

100
VINDC = 0.8VDD

95
Y = 99.8%

90
90

V D D = 1.5V, V IN = 20mV

CL = 4fF

Minimum VIN / mV

80 70 60

85

V INDC = 0.6 V DD
Yield / % 75

Yield / %

80

70

VDD = 1.5V CL = 4fF

Y = 97%
50 40 30

60

VINDC = 0.6V VINDC = 0.9V VINDC = 1.2V VINDC = 1.5V

20 40 V 60 / mV 80 100

65
Y = 90%

V INDC = V DD

50 0

20 0.8

1.2

IN

1.4 V /V
DD

1.6

1.8

55

-55C
0.5m 0.3m 1m 0.3m

27C

140C
1m 0.12m 3m 0.3m

W / L (M9)

number of samples this effect is referred to as functional yield (in %) number of correct decisions number of samples

(5)

Its dependence on several parameters, especially on , and , is analyzed below. This statistical investigation is based on Monte-Carlo simulations which incorporate local and global variations of transistor parameters by , where represents the standard deviation of each parameter. Also random mismatch between the output load capacitances has been considered. Fig. 6 shows the yield versus for values of down to 40% of . Each marker represents a Monte-Carlo simulation of 1000 samples. Obviously, on the yield. In there is a signicant inuence of this case it improves from 72% to almost 100% at = 30mV if the input potential is reduced from 1.5V to 0.6V. From the theoretical point of view the yield is identical to the probability for the actual offset voltage to be below where follows a Gaussian probability distribution

yield can be improved without decreasing the speed just by reducing the input dc level . But also the supply voltage itself has an impact on (Eqn. (2), (4)). For a certain yield specication, the minimum scales with the supply voltage. Fig. 7 shows that there is nearly a linear relation between and . A yield of 99.8% requires to be larger than = 1.5V is 80mV and it 5% of , i.e. at = 1.0V. reduces to = 53mV at The inuence of the transistor sizing and temperature on the yield is rather low. According to Fig. 8 the impact can be neglected compared to the considerable yield improvement due to . The low inuence of the sizing of M9 is due to the fact that the operation current (Eqn. (4)) depends in a quadratic manner on but only linearly on which is proportional to .

4. Experimental Results
A 4kx32-bit SRAM with the considered voltage sense amplier has been published previously [3]. In order to measure speed and yield, a separate sense amplier has been placed beside the memory on the same chip as shown in Fig. 9. Small metal pads for contactless electron beam measurement have been placed at both output pins, at the enable signal and supply. Fig. 10 shows a typical transient response. In this case a delay (from EN to SON, referred to 50% of ) of 119ps can be obtained. The

(6)

Due to the symmetry of the circuit the mean offset will be zero. Hence, is well-dened by just one parameter, the standard deviation of the input offset which is determined by the mismatch between the differential input transistors [5] and between the cross-coupled stage [6]. (Gaussian disBased on tribution) the standard deviation can be extracted from mV and Fig. 6, e.g., mV. To explain the effect on the yield it has to be realized that lower of causes smaller bias current (Eqn. (4)). This, in turn, results in a larger initial voltage difference between the cross-coupled inverter terminals SO and SON (Eqn. (2)). If the initial voltage difference is large, it is more likely that a correct decision occurs. Therefore the yield increases inversely to . For example, for 2V and = 50mV the initial difference increases from 9.93mV to 26.3mV if is lowered to 60% of . Hence, taking Fig. 4 into account, the

ebeam pads (2m x 2m)

sense amplifier

delay for different supply voltages and input differences is plotted in Fig. 11 as a function of . The same characteristic behavior as in Figures 3 and 4 can be observed, even though the measured delay is larger due to a different load at the outputs. Fig. 12 shows the histogram of the input offset voltage and Fig. 13 the corresponding yield is reduced from obtained from 45 samples. If 1.5V to 1.05V (70% of ), the standard deviation of the offset voltage decreases from 19mV to 8.5mV. Consequently, the yield increases, e.g., from 85.2% to 99.2% 20mV. This agrees well with the theory of at Section 3. Fig. 13 indicates a better matching of the transistors and load capacitances than assumed in Fig. 6.

1.5 1.25

SO
1

Volt

0.75

EN
0.5 0.25

SON

VDD= 1.5V, VIN = 100mV, VINDC = 1.05V

0 0 50 100 150 200 250 300 350 400

t / ps

400 350 300 Delay / ps 250 200 150 100 50 0.6 0.7 0.8

VDD = 1V, Vin = 50mV VDD = 1V, Vin = 100mV VDD = 1.5V, Vin = 50mV VDD = 1.5V, Vin = 100mV

5.

Conclusion

An analytical expression for the sense amplier delay has been derived which distinguishes two output transition phases. Based on this investigation and on MonteCarlo simulations the yield concerning the correct sensing decision has been analyzed. This table summarizes the inuence of the most important parameters:

0.9 1 1.1 VINDC / V 1.2 1.3 1.4

has a major impact on yield while the geometry of the turn-on transistor M9 and the temperature are of minor inuence. On the other hand, M9 denitely determines the total delay but there is rather a small inufor . This means for ence of the design of the sense amplier that the delay can be adjusted by sizing M9 while the yield can be optimized by . This is conrmed by experimental results from a sense amplier implemented in 130nm CMOS. The offset standard deviation decreases from 19mV to 8.5mV if the input dc voltage is reduced from 1.5V to 1.05V, while the delay remains almost constant. At 1.5V supply and 50mV input voltage difference a sensing delay of 119ns is measured. Therefore, the sense amplier is well suitable for low-power memory architectures with bitline voltages and as a second stage comparator in current below is typically . sense ampliers where Acknowledgement: Many thanks to Rupert Thanner and Bernd Kr ger for their excellent measurement support. u

20 no. of samples 15 10 5 os = 19mV

VINDC = 1.5V

no. of samples

0 50 40 30 20 10 20 VINDC = 1.05V 15 os = 8.5mV 10 5

10

20

30

40

50

100 80 Yield / % 60 40 20 0 40

0 50 40 30 20 10 0 10 Vos / mV

20

30

40

50

[1] T. Kobayashi, K. Nogami, T. Shirotori, and Y. Fujimoto, IEEE J. Solid-State Circ., vol. 28, Apr. 1993, pp. 523-527. [2] B. Nikoli , V. G. Oklobd ija, V. Stojanovi , W. Jia, J. K. c z c Chiu, and M. M. Leung, IEEE J. Solid-State Circ., vol. 35, June 2000, pp. 876-884. [3] B. Wicht, J.-Y. Larguier and D. Schmitt-Landsiedel, ISSCC Dig. Techn. Papers, Feb. 2003, pp. 462-463. [4] D. Johns, and K. Martin, Analog Integrated Circuit Design, John Wiley & Sons, New York, 2000. [5] M. Pelgrom, A. Duinmaijer and A. Welbers, IEEE J. SolidState Circ., vol. 24, Oct. 1989, pp. 1433-1440. [6] S. J. Lovett, G. A. Gibbs, and A. Pancholy, IEEE J. SolidState Circ., vol. 35, Aug. 2000, pp. 1200-1204.

VINDC = 1.05V = 8.5mV

os

VINDC = 1.5V os = 19mV

VDD = 1.5V, 45 samples

20 V
IN

0 / mV

20

40