CONTROL MEMORY

Control memory is a random access memory(RAM) consisting of addressable storage registers. It is primarily used in mini and mainframe computers. It Is used as a temporary storage for data. Access to control memory data requires less time than to main memory; this speeds up CPU operation by reducing the number of memory references for data storage and retrieval. Access is performed as part of a control section sequence while the master clock oscillator is running. The control memory addresses are divided into two groups: a task mode and an executive (interrupt) mode. Addressing words stored in control memory is via the address select logic for each of the register groups. There can be up to five register groups in control memory. These groups select a register for fetching data for programmed CPU operation or for maintenance console or equivalent display or storage of data via a maintenance console or equivalent. During programmed CPU operations, these registers are accessed directly by the CPU logic. Data routing circuits are used by control memory to interconnect the registers used in control memory. Some of the registers contained in a control memory that operate in the task and the executive modes include the following : Accumulators :Indexes :Monitor clock status indicating registers :Interrupt data register. Microprogramming A control unit is the most complex part in a processor. It sends control signals to activate the data path of a processor. Let's see an example data path and inspects how it fetches an instruction and executes it. A control unit can be implemented in either hardwired or microprogram. A hardwired control unit is a large FSM (finite state machine) sending control signals to data path. A microprogrammed control unit is a complex programmable unit that outputs control signals to data path according to its "microprogram". A microprogrammed control unit can be regarded as a simple computer. In this view, a processor has another simple processor inside it which is its control unit. Controlling a data path is described by its microprogram. Microprogram A general sequential circuit. The Combinational circuit can be directly implemented as a truth table, although it is not efficient in terms of size. A read-only-memory (ROM) stored the truth table. This ROM can be regarded as storing a "program".

The ROM can output a fixed sequence of control signals simply by cycling the address of the ROM. The content of this ROM is a microprogram. It is comparable to a straight line program (no transfer of control). Each entry in the ROM is called a microword. A microprogram counter is used to cycling the sequence of control.

Conditionals are the bits used to determine the flow of microprogram. The next address determines the next microword to be executed. A microprogram is executed as follows. A microword at the location specified by the microprogram counter is read out; control bits are latched at an output buffer which is connected to the data path. If the conditional field is specified and the test for conditional is true, the next address of microprogram will come from the next address field otherwise the microprogram counter will be incremented (execute the next microword). What that has been described is called horizontal microprogram. The microword can have other formats. There are several possibilities: Single format, one address as just described above. Single format, two addresses, contain two next addresses field, one for result of test true, and the other for result of test false. Multiple formats, such as, one format for the control bits without the next address field and another format for jump on condition with the address field. The advantage is that the microword can be shorter than the single format. The disadvantage is that to jump will take one extra cycle. Horizontal microprogram allows each control bit to be independent from other therefore enables maximum simultaneous events and also offers great flexibility. It is also waste a lot bit. For each field of a microword, there may be a group of bits that are not active at the same time therefore they can be encoded to use a fewer bit. A decoder is required to decode these bits and to connect them to the data path. This approach is called vertical microprogram. There are many possibilities to compact the micro memory to be as small as possible, sometimes trading off speed for space, for example, a two-level microprogram. The first level is vertical i.e. maximally encoded; the microword of the level one is pointed to the horizontal word of the second level. This is rather like the first level is composed entirely from subroutine call and the second level is the subroutine. The control unit just described has the output of control unit directly mapped to control signals. It is possible to have more than one output format that map the output of the control unit to the actual control signals, for example using the first bit to choose the format, 1 to mean the control bit, 0 to mean the test and jump to other microprogram address. This is called two-format microprogram. It is the effort to reduce the size of microprogram because control and test can be mutually exclusive. control bits next address a) one-address format control bits true next false next b) two-address format

0 control bits 1 next address c) multiple format data path

specification 32-bit ALU 32-bit bus width 32 registers components register bank: 1 write port, 2 read ports ALU : add T register (temp reg) 32-bit bus PC (program counter) with +1 op. memory interface MAR (mem address reg) MBR (mem buffer reg) IR (instruction reg) memory: CS (code segment) contains program program: machine code format of a 32-bit instruction op:5 r1:5 r2:5 r3:5 x:12 (x -- don't care) op specifies operation of instruction ADD 00001 r1,r2,r3 specifies register number, 32 reg. requires 5 bits example add r1 r2 r3

means R[r2]+R[r3] -> R[r1] 00001 00001 00010 00011 x...x or written in hex as 08443X..X The behaviour of data path can be described in register transfer level (RTL). The level that specifies how data is flowed between components in the data path. Let's call this description, microsteps. notation label: source->destination microsteps fetch: PC -> MAR Mread -> MBR MBR -> IR PC + 1 decode (goto add:) execute add: R[r2] + R[r3] -> T T -> R[r1] goto fetch: each step takes one clock. some step can be overlapped if they are independent, for example, PC + 1 can be activated concurrently of any step in fetch. Now we want to explore in more details how to realist this behaviour (the microstep). Let's image each connection to have an ON/OFF gate (valve) associate with it. The data flow can occur when the gate is ON. To transfer data from a source through bus to a destination, two gates are opened, one is the gate from source to bus, another one is the gate from bus to destination, for example, to do PC -> MAR two gates are: PC>BUS, BUS>MAR Here is the list of all gates in the example: notation gate number, gate name 1 PC>BUS 2 BUS>MAR 3 MBR>BUS

4 BUS>MBR 5 Mread 6 BUS>IR 7 PC+1 8 Rread 9 ALU:add 10 ALU>T 11 T>BUS 12 Rwrite 13 Mwrite 14 BUS>PC 15 ? Each microstep can be written as the state of these gates. We use the convention that when a gate's name is written it is activated (or ON) otherwise it is idles (or OFF). fetch: PC>BUS, BUS>MAR Mread MBR>BUS, BUS>IR PC+1 add: Rread, ALU:add, ALU>T T>BUS, Rwrite these events can be written using gate numbers: fetch: 1,2 5 3,6 7 add: 8,9,10 11,12 A finite state machine is used to realise the control unit. A FSM for this control unit is: notation: state {activation; next state} A {1,2; B} B {5; C} C {3,6; D} D {7; decode}

E {8,9,10; F} F {11,12; A} decode is a state that is multi-way branch to other states according to opcode-field on an instruction in IR (the first 5-bit). This FSM can be implemented using various technology. The design and implementation of a FSM is greatly simplified by the use of CAD tools. How complicate is a control unit? A control unit is implemented as a sequential synchronous machine. It can be described as O = f(I) O output is a function of I input, f is a Boolean function which is purely combinational. To have state feedback, a part of output is stored in a memory to be fed back to input. This memory is synchronised with a clock so that changes at its output (the state) happen at the edge of clock. Between edge of a clock, its output does not change. Oc = f(Ic,Is) Is(t+1) = Os(t) where Oc is the output, Os is the state output, Ic is the input, Is is the state input, t is time. The size of a combination circuit with I input and O output is big-oh(O2^I). This is the size requires to store the output as a function of inputs. The control unit is the example has 15 outputs 5 inputs from opcode-field of IR 6 states (fetch+add) Os must be 3 bits to contain 6 states. Oc is 15 Ic is 5 Is is 3 so its size is (15+3)2^(5+3), approx. 5000 bits (4608) The table contains f and the state feedback can be viewed as a kind of program. O = f(I) address O = f(I) state I 00110101.... 001 ... 10001010.... 010

...

...

the height of this table is 2^I, 256 in our example. the width of each row in this table is 15+3 bits. The content of this table is regarded as a program. We can write it down as the event of activation of gates fetch {1,2; B} B {5; C} C {3,6; D} D {7; decode} add {8,9,10; F} F {11,12; fetch} This is microprogram, voila! Advantage and disadvantage of microprogramming. Advantage Making change to a hardwired control unit implies global change, that is, the circuit will be almost totally changed. Hence, it is constly and time consuming although the present CAD tools do reduce most of the burden in this area. In contrary, for a microprogrammed control unit, making change to it is just changing the microprogram, the bit pattern in the micromemory. There is tools to generate these bit content from a human-readable microprogram, hence making change to microprogram is similar to edit-compile a program. The circuit for control unit does not change. This enables adding new instructions, modifies addressing mode, etc. or updating the version of control behavior easy to do. Disadvantage Microprogram relies on fast micromemory. It requires high speed memory. In fact, the architect of early microprogrammed machine, IBM S360 family, depended on this crucial technology, which was still in the development at that time. The breakthrough in memory technology came, and S360 became the most successful family of computers. Hardwired control unit is much faster. Microprogramming is inherently very low level, making it hard to be absolutely correct. Microprogramming is by nature concurrent, many events occur at the same time, so it is difficult to develop and debug. (for a good reading that shows this process, read Tracy Kidder's "Soul of a new machine").

Design of Control Unit

To execute an instruction , the control unit of the CPU must generate the required control signal in the proper sequence. As for example , during the fetch phase , CPU has to generate PCout signal along with other required signal in the first clock pulse. In the second clock pulse CPU has to generate PCin signal along with other required signals. So, during fetch phase , the proper sequence for generating the signal to retrieve from and store to PC is PCout and PCin. To generate the control signal in proper signal , a wide variety of techniques exists. Most of these techniques , howeve , fall into one of the two categories. 1. 2. Hardwired Control Microprogrammed Control.

Hardwired Control : In this hardwired control techniques , the control signals are generated by means of hardwired circuit. The main objective of control unit is to generate the control signal in proper sequence. Consider the sequence of control signal required to execute the add instruction that is explained in previous lecture. It is obvious that eight non-overlapping time slots are required for proper execution of the instruction represented by this sequence. Each time slot must be at least long enough for the function specified in the corresponding step to be completed. Since , the control unit is implemented by hardwire device and every device is having a propagation delay , due to which it requires some time to get the stable output signal at the output port after giving the input signal. So , to find out the time slot is a complicated design task. For the moment , for simplicity, let us assume that all slots are equal in diameter. Therefore the required controller may be implemented based upon the use of a counter driven by a clock. Each state, or count , of this counter corresponds to one of the steps of the control sequence of the instructions of the CPU. In the previous lecture , we have mentioned control sequence for execution of two instructions only ( one is for add and other one is for branching). Like that we need to design the control sequence of all the instructions.

By looking into the design of the CPU , we may say that there are various instruction for add operation. As for example, Add the [NUM] NUM , R1 Add the contents of memory location specified by NUM to contents of register R1 . R1 R1 +

Add R2 , R1 register R1

Add the contents of register R2 to the contents of R1 R1 + R2

The control sequence for execution of these two add instructions are different. Of course , the fetch phase of all the instruction remain same. It is clear that control signals depend on the instruction, i.e the contents of the instruction register. It is also observed that execution of some of the instructions depend on the contents of condition code or status flag register , where the control sequence depends in conditional branch instruction. Hence , the required control signals are uniquely determined by the following information: * Contents of the control counter. * Contents of the instruction register. * Contents of the condition code and other status flags. The status flags represent the various state of the CPU and various control lines connected to it , such as MFC status signal. The structure of control unit can be represented in a simplified view by putting it in block diagram. The detailed hardware involved may be explored step by step . the simplified view of the control unit is given in the figure (A).

Control Unit Organization The decoder/encoder block is simply a combinational circuit that generates the required control outputs depending on the state of all its input.

The decoder part of decoder/encoder part provide a separate signal line for each control step , or time slot in the control sequence. Similarly , the output of the instructor decoder consists of a separate line for each machine instruction loaded in the IR , one of the output line IN to IN is set to 1 and all other lines are set to 0.

All input signals to the encoder block should be combined to generate the individual control signals. In the previous section, we have mentioned the control sequence of the instruction, Add contents of memory location address in memory direct made to register R1 ( ADD , MD) , Control sequence for an unconditional branch instruction (BR) , also we have mentioned about Branch on negative(BRN). Consder those three CPU instruction ADD , MD , BR , BRN . It is required to generate many control signals by the control unit. These are basically coming out from the encoder circuit of the control signal generator. The control signals are lie PCin , PCout , Zin , Zout , MARin , add , End etc. By looking into the above three instruction , we can write the logic function for Zin as : Zin = + .ADD_MD + .BR + .BRN + For all instructions , in time step1 we need the control signal Zin to enable the input to register Z in time cycle of ADD_MD instruction , in time cycle of BR instruction and so on . Similarly , the Boolean logic function for add signal is add = + .ADD_MD + .BR + .. These logic functions can be implemented by a two level combinational circuit of AND and OR gates. Similarly , the End control signal is generated by the logic function : End = . ADD_MD + .BR + ( .N + . ).BRN + .

This End signal indicates the End of the execution of an instruction , so this End signal can be used to start a new instruction fetch cycle by resettin the control step counter to its starting value. The circuit diagram (Partial) for generating Zin and End signal is shown in the diagram.

Generation of Zin Control Signal Signal

Generation of the End Control

The signal ADD_DM , BR , BRN etc . are coming from instruction decoder circuits which depends on the contents of IR. The signal , , etc are coming out from step decoder depends on control step counter. The signal N (Negative) is coming from condition code register. When wait for MFC (WMFC) signal is generated , then CPU does not do any works and it waits for an MFC signal from memory unit. In this case , the desired effect is to delay the initiation of the next control step until the MFC signal is received from the main memory. This can be incorporated by inhibiting the advancement of the control step counter for the required period. Let us assume that the control step counter is controlled by a signal called RUN. By looking at the control sequence of all the instructions , the WMFC signal is generated as: WMFC = + . ADD_MD + The RUN signal is generated with the help of WMFC signal and MFC signal . The arrangement is shown in the figure.

The MFC signal is generated by the main memory whose operation is independent of CPU clock. Hence MFC is an asynchronous signal that may arrive at any time relative to the CPU clock. It is possible to synchronized with CPU clock with the help of a D flip-flop. When WMFC signal is high , then RUN signal is low. This run signal is used with the master clock pulse through an AND gate. When RUN is low , then the clock signal remains low, and it does not allow to progress the control step counter. When the MFC signal is received , the run signal becomes high and the clk signal becomes same with the MCLK signal and due to which the control step counter progresses. Therefore , in the next control step , the WMFC signal goes low and control unit operates normally till the next memory access signal is generated. The timing diagram for an instruction fetch operation is shown in the figure.

Timing of control signals during instruction fetch.

In this discussion we have presented a simplified view of the way in which the sequence of control signals needed to fetch and execute instructions may be generated . It is observed from the discussion that as the number of instruction increases the number of required control signals will also increase . In VLSI technology , structure that involve regular interconnection patterns are much easier to implement than the random connections. One such regular structure is PLA ( programmable logic array). PLAs are nothing but the arrays of AND gates followed by array of OR gates. If the control signals are expressed as sum of product form then with the help of PLA it can be implemented. The PLA implementation of sequence controller is shown in the figure.

General Register Organization

During execution of a program, data values, results, return addresses, and partial results are stored in the memory location. Accessing the memory is the most time consuming operation in a computer. The CPU can access a register more quickly than a memory location and the register-to-register operation executes faster than compared to the memory-to-memory or register-to-memory operation. Due to the faster execution in register, the intermediate data is stored in the register so that it is more convenient and more efficient for CPU to access these data and perform operation. There are large numbers of registers present in the computer, which are connected with the common bus system. Hence, all the arithmetic, logic, and shift operation in the CPU are performed by the common unit. In the following figure, a seven register bus organization is displayed which has a common ALU to perform all the computation. In the above figure, the ALU gets the data from the register and the result is stored back into these registers. The two multiplexers are connected to the output of the register to form two buses A and B. These buses provides the input to the ALU, where the arithmetic, logic, or shift operations are performed depending up on the opcode specified by the instruction. Once the micro-operations are performed, the result is stored back into the registers. Let us consider the following operation: R1 <- R2 R3 The binary selection variables must be provided by the control unit for the following selector inputs: 1. MUX A Selector (SELA): Places the content of R2 into the bus A. 2. MUX B Selector (SELB): Places the content of R3 into the bus B. 3. ALU Operation Selector (OPR): Provides the arithmetic subtraction A B. 4. Decode destination selector (SELD): Transfers the content of the result to register R1. Control Unit generates all four selection variable mentioned in above example and these variable must be available before the beginning of the instruction cycle. Get all the resource you need for your homework help and assignment help at Transtutors.com. We provide homework help and assignment help for all levels ranging from school level to undergraduate to graduate level. Our team of experts thrive to provide only original and plagiarism free resource for the homework help and assignment help.

STACK ORGANIZATION
Stack is a storage structure that stores information in such a way that the last item stored is the first item retrieved. It is based on the principle of LIFO (Last-in-first-out). The stack in digital computers is a group of memory locations with a register that holds the address of top of element. This register that holds the address of top of element of the stack is called Stack Pointer. Stack Operations The two operations of a stack are: Push: Inserts an item on top of stack. Pop: Deletes an item from top of stack. Implementation of Stack In digital computers, stack can be implemented in two ways: Register Stack

Memory Stack Register Stack A stack can be organized as a collection of finite number of registers that are used to store temporary information during the execution of a program. The stack pointer (SP) is a register that holds the address of top of element of the stack. Memory Stack A stack can be implemented in a random access memory (RAM) attached to a CPU. The implementation of a stack in the CPU is done by assigning a portion of memory to a stack operation and using a processor register as a stack pointer. The starting memory location of the stack is specified by the processor register as stack pointer.