IC Compiler-Clock Tree Synthesis Checklist--Updated for Y-2006.

06-SP2
Prerequisite Check Make sure the design is legally placed; use check_legality -verbose and legalize_placement. Make sure all the clocks and clock constraints are defined; use report_clock or all_clocks to verify. Is source of generated clock really a clock source (make sure that there is a create_clock defined on the source net)? Can create_generated_clock trace back along a real path to the clock source? If not, the sinks of the generated clocks will not be balanced with the sinks of the source. Clock definitions on hierarchical ports are not supported in IC Compiler clock tree synthesis; if any such definitions exists, redefine the clock on the output pin of the driver of the hierarchical port. Clock Options Check The -buffer_relocation, -gate_sizing, -gate_relocation, -delay_insertion and -buffer_sizing options of the set_clock_tree_option command apply to compile_clock_tree only. The optimize_clock_tree command uses its own defaults and options. Not all options of set_clock_tree_options are applicable on a per-clock basis - they are global settings. As of Y-2006.06-SP1, maximum transition can be set on a per-clock basis, but not maximum capacitance. Clock Reference Check Use set_clock_tree_references judiciously, especially with the -sizing_only and -delay_insertion_only options. If you do not provide a list, IC Compiler uses all buffers and inverters in the library (unless they have the dont_use attribute). Avoid using buffers or inverters with large difference in rise and fall characteristics - use set cts_do_characterization true to get details about the delays through various buffers and inverters. As of Y-2006.06-SP2, clock tree synthesis requires at least one usable inverter in its list of buffers and inverters; Make sure at least one inverter is usable (remove_attribute [get_lib_cell invName] dont_touch; remove_attribute [get_lib_cell invName] dont_use ); fix is being worked on. Clock Exceptions Check As of Y-2006.06-SP2, if you use set_clock_tree_exceptions to specify a particular pin as a stop_pin, float_pin or exclude_pin, the last one takes precedence. Clock-related attributes and nondefault rules are propagated in spite of dont_touch_subtrees being specified; use set cts_traverse_dont_touch_subtrees false to override this feature. Timer-Related Check Use report_disable_timing to make sure that the disabled timing arcs are intentional. Use report_case_analysis to make sure that the set_case_analysis are intentional and make sense; use remove_case_analysis to remove the incorrect ones. The set_timing_derate command is ignored by clock tree synthesis and report_clock_tree; use report_timing_derate to check. The report_clock_timing and report_timing commands honor set_timing_derate. The message "Invalid phase delay at pin xx/yy" implies a problem - open a STAR; this message is printed only in debug mode (set cts_use_debug_mode true).

dont_touch-Related Checks As of Y-2006.06-SP1, clock tree synthesis does not honor the dont_touch attribute on nets or cells; to force clock tree synthesis not to insert buffers on nets, use set_clock_tree_exceptions dont_buffer_nets. Clock tree synthesis honors dont_touch attribute on cells; clock tree synthesis does not size these cells. If you dont want the dont_touch on nets to be propagated to the cell on the net, use set dont_touch_cell_with_dont_touch_nets false. Other Checks Compile the most critical clock first (in IC Compiler, in Astro it should be compiled last). In IC Compiler, clock tree synthesis does not move the clock buffers of other clock trees; hence the most critical clock should be compiled first. Check that the layer constraint is a soft constraint; use set parameter -name hardMinLayercon for a tighter layer constraint. Nondefault rules: Use set_clock_tree_option -routing_rule <R> -use_default_routing_for_sinks to set the nondefault rule. Use report_clock_tree -settings to report nondefault rules. If you use set_net_routing_rule to set nondefault rules, report_clock -settings does not report them; use report_net_routing_rule instead. Clock shielding is considered a nondefault rule; see SolvNet article # 16899. Check clock gating; see SolvNet article # 17127. Nets beyond sequential cells and some combinational cells might not have an ideal net attribute, so place_opt might insert buffers on them. To avoid this, mark them as ideal before running place_opt. If you have buffers on clock nets in the incoming design, you can remove them with remove_buffer_tree. See SolvNet article # 18563.

Common Problems in Clock Tree Synthesis and Their Causes

Poor Skew? Do you have gate sizing and delay insertion on during clock tree synthesis? If you are using a version earlier than Y-2006.06-SP2, use a two-pass clock tree synthesis flow. Starting in version Y-2006.06-SP2, the two-pass flow is the default. Use block mode for better skew. Fanouts of integrated clock gating cells (ICGs) versus split - balanced fanout can help QoR. Balanced input to clock tree synthesis? Poor Insertion Delay? Did you try top mode? If you are using a version earlier than Y-2006.06-SP2, are you using the two-pass flow? Too Many Buffers? Check DRC constraints: Any dont_buffer_nets? Any constraints very large compared to target? Any nets after ignore pins? Mixed clock and data nets? Need On-Chip Variation (OCV)? Try logic-level balancing. Problems in remove_clock_tree?

Do not use remove_clock_tree until -Y2006.06-SP3. If there are buffers on clock nets from optimization, use remove_buffer_tree to remove them. Long Runtime? Turn off gate relocation. Out of Memory? Known issue in top mode in version Y-2006.06-SP1. Use version Y-2006.06-SP2 or versions earlier than Y-2006.06-SP1. Clock Buffers in Illegal Location? This happens in top mode in versions earlier than Y-2006.06-SP1 and has been fixed in Y-2006.06-SP2.