Documente Academic
Documente Profesional
Documente Cultură
M.V.Kasuni Perera
Thanks are due to President’s Fund of Sri Lanka, who has granted me with a
Scholarship to complete the Masters Degree in Electrical Engineering. Finally I would
like to thank all my colleagues both in Sweden & Sri Lanka, my parents for their
continuous encouragement.
December 2007.
i
Abstract
Quality of the output power delivered from the utilities has become a major
concern of the modern industries for the last decade. These power quality associated
problems are voltage sag, surge, flicker, voltage imbalance, interruptions and
harmonic problems. These power quality issues may cause problems to the industries
ranging from malfunctioning of equipments to complete plant shut downs. Those
power quality problems affect the microprocessor based loads, process equipments,
sensitive electric components which are highly sensitive to voltage level fluctuations.
It has been identified that power quality can be degraded both due to utility
side abnormalities as well as the customer side abnormalities. To overcome the
problems caused by customer side abnormalities so called custom power devices are
connected closer to the load end.
One such reliable customer power device used to address the voltage sag,
swell problem is the Dynamic Voltage Restorer (DVR). It is a series connected
custom power device, which is considered to be a cost effective alternative when
compared with other commercially available voltage sag compensation devices.
The main function of the DVR is to monitor the load voltage waveform
constantly and if any sag or surge occurs, the balance (or excess) voltage is injected to
(or absorbed from) the load voltage. To achieve the above functionality a reference
voltage waveform has to be created which is similar in magnitude and phase angle to
that of the supply voltage. Thereby during any abnormality of the voltage waveform it
can be detected by comparing the reference and the actual voltage waveforms.
A new control technique to detect and compensate for the single phase voltage
sags is designed in this project. The simulation was checked in the EMTDC/PSCAD
simulation software and has shown reliable results.
ii
Contents
Acknowledgement ……………………………………………………………. i
Abstract ……………………………………………………………………. ii
Contents ……………………………………………………………………. iii
List of abbreviations ……………………………………………………………. v
List of tables and figures ……………………………………………………. vi
Chapter 3 New control technique developed for single phase voltage sags
3.1 Background …………………………………………………… 28
3.2 Simplified control block diagram …………………………… 29
3.3 PSCAD Implementation of control circuit …………………… 30
3.4 PSCAD Implementation of power circuit …………………… 45
iii
4.6 System 6 …………………………………………………… 84
4.7 System 7 …………………………………………………… 86
4.8 Analysis of simulation results during different time intervals 88
References ……………………………………………………………………….. 96
List of publications ……………………………………………………………. 101
iv
List of Abbreviations
v
List of tables and figures
Table 2.1 : IEEE definitions for the voltage sags and swells
Table 3.1 : Harmonic content in the normal supply voltage
Table 4.2 : Different sag and load criteria
Figure 2.1 : Different types of voltage sags
Figure 2.2 : (a & b ) Basic operation of DVR (left) and APF (right)
Figure 2.3 : DVR Power circuit
Figure 2.4 : Three phase Graetz bridge and its switching arrangements
Figure 2.5 : NPC inverter configuration and its switching arrangement
Figure 2.6 : H-bridge inverter configuration and its switching arrangement
Figure 2.7 : Different filter placements
Figure 2.8 : Connection methods for the primary side of the injection transformer
Figure 2.9 : Simple power system with a DVR
Figure 2.10 : Pre-sag compensation technique
Figure 2.11 : In-phase compensation technique
Figure 2.12 : Energy optimization technique
Figure 2.13 : Combining both pre-sag and in-phase compensation techniques
Figure 2.14 : Simplified block diagram of a phase locked loop
Figure 2.15 : Block diagram of a Software Phase Locked Loop
Figure 2.16 : Simplified phasor representation of SPLL
Figure 3.1 : Simplified control block diagram for the single phase DVR
Figure 3.2 : Implementation method of block 1
Figure 3.3 : PSCAD implementation of block 1
Figure 3.4 : Integrator clear signal generation
Figure 3.5 : Integrator clear signal
Figure 3.6 : Phase angle variation of the supply voltage
Figure 3.7 : Output waveforms at different output channels
Figure 3.8 : Input waveform to the resettable integrator
Figure 3.9 : Simulation block for the reference phase angle wave form generation
vi
Figure 3.10 : Simplified diagram of control block 2
Figure 3.11 : Generation of angle error signal
Figure 3.11 : additional block to obtain the angle error
Figure 3.12 : Specifications of the comparator block
Figure 3.13 : Angle error calculation
Figure 3.14 : User defined parameters in the PI controller
Figure 3.15 : Synchronization process
Figure 3.16 : Left: Reference waveform generation & Right: Comparator
specifications
Figure 3.17 : Reference voltage waveform generation
Figure 3.18 : Simulation block for reference voltage waveform generation
Figure 3.19 : Control voltage waveform before the voltage sag
Figure 3.19 : (bottom left) Control voltage waveform during the sag (in phase
voltage sag)
Figure 3.19 : (bottom right) Control voltage waveform during the sag (voltage sag is
created with a phase shift)
Figure 3.20 : Simulation block 4
Figure 3.21 : Power circuit of the DVR
Figure 3.22 : Equivalent circuit of DVR power circuit
Figure 3.23 : Equivalent circuit used for parameter estimation
Figure 3.24 : Inverter leg switching signal generation
Figure 3.25 : Switching signals for inverter legs
Figure 3.26 : Low pass filter configuration
Figure 3.27 : Configuration data of the voltage injection transformer
Figure 3.28 : Left: Generating voltage sag for the power circuit
Right: Breaker parameters
Figure 3.29 : Equivalent circuit for the distribution line
Figure 3.40 : Equivalent circuit before the voltage sag
Figure 3.41 : Equivalent circuit during the voltage sag
Figure 3.42 : Supply voltage waveform with and without harmonics
Figure 3.43 : PSCAD implementation of supply harmonics
Figure 4.1 : Control circuit simulation block diagram
Figure 4.2 : Power circuit of the DVR
Figure 4.3 : Voltage waveforms for system 1 during synchronization
vii
Figure 4.4 : Voltage waveforms for system 1 when the DVR is engaged
Figure 4.5 : Voltage waveforms for subsystem 1a during the neighborhood of sag
Figure 4.6 : Voltage waveforms for subsystem 1a during the sag
Figure 4.7 : Voltage waveforms for subsystem 1b during the neighborhood of sag
Figure 4.8 : Voltage waveforms for subsystem 1b during the sag
Figure 4.9 : Voltage waveforms for subsystem 1b during the neighborhood of sag
Figure 4.10 : Voltage waveforms for subsystem 1b during the sag
Figure 4.20 : Voltage waveforms for subsystem 2c during the sag
Figure 4.21 : Voltage waveforms for subsystem 2d during the neighborhood of sag
Figure 4.22 : Voltage waveforms for subsystem 2d during the sag
Figure 4.23 : Voltage waveforms for system 3 during synchronization
Figure 4.24 : Voltage waveforms for system 3 when the DVR is engaged
Figure 4.25 : Voltage waveforms for subsystem 3a during the neighborhood of sag
Figure 4.26 : Voltage waveforms for subsystem 3a during the sag
Figure 4.27 : Voltage waveforms for subsystem 3b during the neighborhood of sag
Figure 4.28 : Voltage waveforms for subsystem 3b during the sag
Figure 4.29 : Voltage waveforms for subsystem 3c during the neighborhood of sag
Figure 4.30 : Voltage waveforms for subsystem 3c during the sag
Figure 4.31 : Voltage waveforms for subsystem 3d during the neighborhood of sag
Figure 4.32 : Voltage waveforms for subsystem 3d during the sag
Figure 4.33 : Voltage waveforms for system 4 during synchronization
Figure 4.34 : Voltage waveforms for system 4 when the DVR is engaged
Figure 4.35 : Voltage waveforms for subsystem 4a during the neighborhood of sag
Figure 4.36 : Voltage waveforms for subsystem 4b during the sag
Figure 4.37 : Voltage waveforms for subsystem 4b during the neighborhood of sag
Figure 4.38 : Voltage waveforms for subsystem 4b during the sag
Figure 4.39 : Voltage waveforms for subsystem 4c during the neighborhood of sag
Figure 4.40 : Voltage waveforms for subsystem 4c during the sag
Figure 4.41 : Voltage waveforms for subsystem 4d during the neighborhood of sag
Figure 4.42 : Voltage waveforms for subsystem 4d during the sag
Figure 4.43 : Voltage waveforms for subsystem 5a during the neighborhood of sag
Figure 4.44 : Voltage waveforms for subsystem 5b during the neighborhood of sag
Figure 4.45 : Voltage waveforms for subsystem 5c during the neighborhood of sag
Figure 4.46 : Voltage waveforms for subsystem 5d during the neighborhood of sag
viii
Figure 4.47 : Voltage waveforms for subsystem 6a during the neighborhood of sag
Figure 4.48 : Voltage waveforms for subsystem 6b during the neighborhood of sag
Figure 4.49 : Voltage waveforms for subsystem 6c during the neighborhood of sag
Figure 4.50 : Voltage waveforms for subsystem 6d during the neighborhood of sag
Figure 4.51 : Voltage waveforms for subsystem 7a during the neighborhood of sag
Figure 4.52 : Voltage waveforms for subsystem 7b during the neighborhood of sag
Figure 4.53 : Voltage waveforms for subsystem 7c during the neighborhood of sag
Figure 4.54 : Voltage waveforms for subsystem 7d during the neighborhood of sag
Figure 4.55 : Project settings window for system 1
Figure 4.56 : Top : Simulation of subsystem 1a with 0.9μs step time
Bottom : Simulation of subsystem 1a with 1μs step time
ix
Chapter 1
Introduction
Failure to provide the required quality power output may sometimes cause
complete shutdown of the industries which will make a major financial loss to the
industry concerned [4,5,6]. Thus the industries always demands for high quality
power from the supplier or the utility. But the blame due to degraded quality cannot
be solely put on to the hands of the utility itself [7]. It has been found out most of the
conditions that can disrupt the process are generated within the industry itself. For
example, most of the non-linear loads within the industries cause transients which can
affect the reliability of the power supply [8,9]. Following shows some abnormal
electrical conditions caused both in the utility end and the customer end that can
disrupt a process [7,10].
1
Chapter 1
1. Voltage sags
2. Phase outages
3. Voltage interruptions
4. Transients due to Lighting loads, capacitor switching, non linear loads,
etc..
5. Harmonics
Among those power quality abnormalities voltage sags and surges or simply
the fluctuating voltage situations are considered to be one of the most frequent type of
abnormality [4,12,13,14]. Those are also identified as short term under/over voltage
conditions that can last from a fraction of a cycle to few cycles [3,4,11]. Motor start
up, lightning strikes, fault clearing, power factor switching are considered as the
reasons for fluctuating voltage conditions [7].
As the power quality problems are originated from utility and customer side,
the solutions should come from both and are named as utility based solutions and
customer based solutions respectively [3]. The best examples for those two types of
solutions are FACTS devices (Flexible AC Transmission Systems) and Custom power
devices. FACTS devices are those controlled by the utility, whereas the Custom
power devices are operated, maintained and controlled by the customer itself and
installed at the customer premises [7].
Both the FACTS devices and Custom power devices are based on solid state
power electronic components [7]. As the new technologies emerged, the
manufacturing cost and the reliability of those solid state devices are improved; hence
the protection devices which incorporate such solid state devices can be purchased at
a reasonable price with better performance than the other electrical or pneumatic
devices available in the market [5]. Uninterruptible Power Supplies (UPS), Dynamic
Voltage Restorers (DVR) and Active Power Filters (APF) are examples for
2
Chapter 1
commonly used custom power devices. Among those APF is used to mitigate
harmonic problems occurring due to non-linear loading conditions, whereas UPS and
DVR are used to compensate for voltage sag and surge conditions [1,5,12,15].
In this thesis the control of a Dynamic voltage restorer for single phase voltage
sags has been studied. Voltage sag may occur from single phase to three phases. But it
has been identified single phase voltage sags are the commonest and most frequent in
Sri Lanka. Therefore the industries that use three phase supply will undergo several
interruptions during their production process and they are compelled to use some form
of voltage compensation equipment. In this research it was found that the most
common voltage compensation equipment used in Sri Lanka is the UPS; though it’s
considered to be an expensive alternative to move towards a full UPS system. This is
the basic reason to carry out this research in that particular area and focused into
single phase voltage sags.
A new control technique to detect and compensate for the single phase voltage
sags was developed and simulated using the EMTDC/PSCAD software. Combination
of both the pre-sag and in-phase compensation techniques was used in the above
developed control to optimize the real power requirement during compensation. In the
said control technique the system generates a random reference voltage waveform
with the nominal voltage amplitude and the frequency with automated synchronising
control. Once the DVR is connected to the system, the phase angle of this reference
signal is synchronized with the supply voltage phase angle by continuously
monitoring the reference phase angle using a feed back synchronsing control loop.
Then by comparing this reference voltage waveform with the measured voltage
waveform, any occurrence of voltage abnormalities was detected as an error. As the
system detect any voltage sags as error, the power circuit in the DVR generates a
voltage waveform to compensate for the voltage sag. The design of the power circuit
parameters and the control circuit is discussed in the preceding chapters in detail. The
simulation results show the very good performance of the controller.
One problem was notified as the internal voltage drop of the DVR and it
responds when harmonics presents in the supply voltage by becoming the injected
voltage being non sinusoidal even under normal operating conditions. However these
3
Chapter 1
cases were checked in the simulation. The simulation results show that at the normal
operating conditions, the injected voltage becomes less and their affect on the load
voltage due to distortion is less. Therefore this thesis has contributed a strong
knowledge to the research and development targeting industrial application to
compensate the single-phase voltage sags.
The basic flow of this report is as follows. Chapter 2 is about the Literature
review, which will describe the basic operation, structure and the existing control
techniques etc… This chapter will give the reader a general idea about the Dynamic
Voltage restorer and its functionality.
The simulation results were illustrated and discussed under Chapter 4. Several
simulations were carried out and analyzed in detail considering all the different cases
and possible combination to prove the reliability of the simulated system.
Chapter 5 will give the reader some hints about further development proposals
of this new control technique and further the technical limitations found during the
research work. Chapter 6 is the conclusion and discussed the author’s views about the
above research activity in overall.
4
Chapter 2
Literature Review
The abnormalities in the distribution system are load switching, motor starting,
load variations and non-linear loads [10]. Whereas lightning and system faults can be
regarded as transmission abnormalities [19].
5
Chapter 2
harmonic distortions, interruptions and flicker, which are the frequent problems
associated with distribution lines [7,17].
However, failure of such custom power devices cause equipment failing, mal-
operations, tripping of protective relays and ultimately plant shut downs, which
results huge financial loss to the industry [20]. Therefore proper design of control and
selection of the custom power device is very important.
Figure 2.1: top left - Voltage sag occurs at the zero crossing point & without a phase shift
top right - Voltage surge occurs at zero crossing point & without a phase shift
bottom left - Voltage sag not at the zero crossing point & without a phase shift
bottom right - Voltage sag at zero crossing point with a phase shift
6
Chapter 2
fault type and the location and also on the fault impedance [19]. The duration of the
fault depends on the performance of the relevant protective device [3].
Further it has been found that the voltage sags with magnitude 70% of the
nominal value are more common than the complete outages [35]. Sags and surges can
be identified by the voltage magnitude and the time duration it prevails. IEEE 519-
1992, IEEE 1159-1995 describes it as in Table 2.1 [10].
For a particular disturbance (voltage sag or swell), if the voltage and time
duration it remains is within the range given in Table 2.1, the custom power devices
are the optimized solution to overcome the problem and compensate for the
abnormality during the time period it prevails [16].
The most common custom power devices to compensate for the voltage sags
and swells are the Uninterruptible Power Supplies (UPS), Dynamic Voltage Restorers
(DVR) and Active Power Filters (APF) with voltage sag compensation facility.
Among those the UPS is the well known. DVRs and APFs are less popular due to the
fact that they are still in the developing stage, even though they are highly efficient
and cost effective than UPSs [3,14,21]. But as a result of the rapid development in the
power electronic industry and low cost power electronic devices will make the DVRs
and APFs much popular among the industries in the near future [1,22].
DVR and APF are normally used to eliminate two different types of
abnormalities that affect the power quality. They are discussed based on two different
load situations namely linear loads and non-linear loads. The load is considered to be
a linear when both the dependent variable and the independent variable shows linear
7
Chapter 2
changes to each other. Resistor is the best example for a linear device. The non-linear
load on the other hand does not show a linear change. Capacitors and inductors are
examples for non-linear devices.
(a) When the supply voltage/current consists of abnormalities, while the load is
linear:
In this case the custom power device together with the defected supply should
be capable of supplying a defect free voltage/current to the load. To be precise the
device should be able to supply the missing voltage/current component of the source.
A reliable device that can be used for the above case (for voltage abnormalities) is the
DVR. It compensates for voltage sags/swells either by injecting or absorbing real and
reactive power [15].
Figures 2.2a and b show the basic function of the DVR and the shunt APF.
Figure 2.2a & b: Basic operation of DVR (left) and APF (right)
8
Chapter 2
From Figures 2.2a, b and the references [11,15,23,25] it is clear that the DVR
is series connected to the power line, while APF is shunt connected.
Among the custom power devices, UPS and DVR can be considered as the
devices that inject a voltage waveform to the distribution line. When comparing the
UPS and DVR; the UPS is always supplying the full voltage to the load irrespective
of whether the wave form is distorted or not. Consequently the UPS is always
operating at its full power. Whereas the DVR injects only the difference between the
pre-sag and the sagged voltage and that also only during the sagged period. Thus
DVR operating losses and the required power rating are very low compared to the
UPS. Hence DVR is considered as a power efficient device compared to the UPS
[12,22,26].
The DVR basically consists of a power circuit and a control circuit. Control
circuit is used to derive the parameters (magnitude, frequency, phase shift, etc…) of
the control signal that has to be injected by the DVR. Based on the control signal, the
injected voltage is generated by the switches in the power circuit [11,27]. Further
power circuit describes the basic structure of the DVR and is discussed in this section.
Power circuit mainly comprising of five units as in Figure 2.3 and the function and the
requirement of each unit is discussed below [1,3,11,16,28].
9
Chapter 2
Energy storage device is used to supply the real power requirement for the
compensation during voltage sag. Flywheels, Lead acid batteries, Superconducting
magnetic energy storage (SMES) and Super-Capacitors can be used as energy storage
devices [3,11,13]. For DC drives such as SMES, batteries and capacitors, ac to dc
conversion devices (solid state inverters) are needed to deliver power, whereas for
others, ac to ac conversion is required.
The maximum compensation ability of the DVR for particular voltage sag is
dependent on the amount of the active power supplied by the energy storage devices
[8,13].
Lead acid batteries are popular among the others owing to its high response
during charging and discharging. But the discharge rate is dependent on the chemical
reaction rate of the battery so that the available energy inside the battery is determined
by its discharge rate [11,21].
10
Chapter 2
shown in Figure 2.4. This is referred to as two-level since the phase output voltage
waveform consists of two output levels; +Vd and 0 Volts [11,29].
Figure 2.4 : Three phase Graetz bridge and its switching arrangements
consists of three levels ⎛⎜ Vdc , 0 and − Vdc ⎞⎟ Volts. The inverter configuration and the
⎝ 2 2 ⎠
single phase output waveforms are shown in Figure 2.5.
output
11
Chapter 2
c) H bridge inverter
In the H bridge inverter, four switches are used. When it used for multilevel
arrangement specially for high voltage application, it is commonly called as chain
circuits. For fundamental switching each switch is on for a duty cycle of 50% and
shown in Figure 2.6 [29].
Low pass passive filters are used to convert the PWM inverted pulse
waveform into a sinusoidal waveform. This is achieved by removing the unnecessary
higher order harmonic components generated from the DC to AC conversion in the
VSI, which will distort the compensated output voltage [30]. These filters can be
placed either in the high voltage side (load side- shown in Figure 2.7-left) or in the
low voltage side (inverter side-shown in Figure 2.7-right) of the injection transformers
[3,15].
When the filters are in the inverter side higher order harmonics are prevented
from passing through the voltage transformer. And it will reduce the stress on the
injection transformer. But there can be a phase shift and voltage drop in the inverted
output. This can be reduced by placing the filter in the load side. But in this case since
the higher order harmonic currents do penetrate to the secondary side of the
transformer, a higher rating of the transformer is necessary. However the leakage
12
Chapter 2
reactance of the transformer can be used as a part of the filter, which will be helpful in
tuning the filter [11,15,21].
Since the DVR is a series connected device, any fault current that occurs due
to a fault in the downstream will flow through the inverter circuit. The power
electronic components in the inverter circuit are normally rated to the load current as
they are expensive to be overrated. Therefore to protect the inverter from high
currents, a by-pass switch (crowbar circuit) is incorporated to by-pass the inverter
circuit [9,11].
Basically the crowbar circuit senses the current flowing in the distribution
circuit and if it is beyond the inverter current rating the circuit bypasses the DVR
circuit components (DC Source, inverter and the filter) thus eliminating high currents
flowing through the inverter side. When the supply current is in normal condition the
crowbar circuit will become inactive [8].
13
Chapter 2
The high voltage side of the injection transformer is connected in series to the
distribution line, while the low voltage side is connected to the DVR power circuit.
For a three-phase DVR, three single-phase or three-phase voltage injection
transformers can be connected to the distribution line, and for single phase DVR one
single-phase transformer is connected [21]. For the three-phase DVR the three single-
phase transformers can be connected either in delta/open or star/open configuration as
shown in Figure 2.8 [15].
Figure 2.8: Connection methods for the primary side of the injection transformer
Left : delta/open configuration Right : Star/open configuration
14
Chapter 2
the voltage drop across the transformer. In order to reduce the saturation of the
injection transformer under normal operating conditions it is designed to handle a flux
which is higher than the normal maximum flux requirement [21].
The DVR injects the difference between the pre-sag and the sag voltage, by
supplying the real power requirement from the energy storage device together with
the reactive power. The maximum injection capability of the DVR is limited by the
ratings of the DC energy storage and the voltage injection transformer ratio. In the
15
Chapter 2
case of three single-phase DVRs the magnitude of the injected voltage can be
controlled individually. The injected voltages are made synchronized (i.e. same
frequency and the phase angle) with the network voltages [16].
Since the network is working under normal condition the DVR is not injecting
any voltages to the system. In that case, if the energy storage device is fully charged
then the DVR operates in the standby mode or otherwise it operates in the self-
charging mode. The energy storage device can be charged either from the power
supply itself or from a different source [11,21].
16
Chapter 2
voltage magnitude, phase shift and thus the wave shape. But depending on the
sensitivity of the load connected downstream, the level of compensation of the above
parameters can be altered. Basically the type of load connected influences the
compensation strategy. For example, for a linear load, only magnitude compensation
is required as linear loads are not sensitive to phase angle changes [11,13].
Further when deciding a suitable control technique for a particular load it
should be considered the limitations of the voltage injection capability (i.e. the rating
of the inverter and the transformer) and the size of the energy storage device [11].
The circuit for a simple power system with a DVR is shown in Figure 2.9
below. The supply voltage, Load voltage, Load current and the voltage injected by the
DVR are denoted by Vs , Vload , Iload and VDVR respectively.
When the system is in normal condition, the supply voltage (Vs) is identified
as pre-sag voltage and denoted by Vpre-sag. In such situation since the DVR is not
injecting any voltage to the system, load voltage (Vload) and the supply voltage will be
the same.
During voltage sag, the magnitude and the phase angle of the supply voltage
can be changed and it is denoted by Vsag. The DVR is in operative in this case and
the voltage injected will be VDVR. If the voltage sag is fully compensated by the DVR,
the load voltage during the voltage sag will be Vpre-sag.
17
Chapter 2
The DVR compensates only for the voltage magnitude in this particular
compensation method, i.e. the compensated voltage is in-phase with the sagged
voltage and only compensating for the voltage magnitude. Therefore this technique
minimizes the voltage injected by the DVR. Hence it is recommended for the linear
loads, which need not to be compensated for the phase angle [11,13]. This particular
compensation technique is shown in Figure 2.10. It is clear from the Figure 2.10, that
there is a phase shift between the voltages before the sag and after the sag.
18
Chapter 2
It should be noted that the techniques mentioned in 2.4.1 and 2.4.2 need both
the real and reactive power 1 for the compensation, and the DVR is supported by an
energy storage device.
In this particular control technique the use of real power is minimized (or
made equal to zero) by injecting the required voltage by the DVR at a 90° phase angle
to the load current. Figure 2.11 depicts the energy optimization technique. However in
this technique the injected voltage will become higher than that of the in-phase
compensation technique. Hence this technique needs a higher rated transformer and
an inverter, compared with the earlier cases [11,13]. Further the compensated voltage
is equal in magnitude to the pre sag voltage, but with a phase shift.
1
The reactive power is generated by converting part of the real power supplied into reactive power (by
the reactive components used for the DVR).
19
Chapter 2
Figure 2.12 gives an idea about the compensation control strategy when both
pre-sag and in-phase compensation techniques are combined. It is clear from the
Figure when the DVR injected voltage is VDVR_1 (at the beginning of the
compensation) the system used pre-sag compensation, and slowly the injected voltage
phasor is moved towards VDVR_4 (in-phase compensation) [11].
20
Chapter 2
1pu
_ 1
ad
lo
=V
g
sa
e-
pr
V
d_2
loa
load_3 R_
3
V DVVDVR_4
Vsag Vload_4
Iload
Figure 2.13: Combining both pre-sag and in-phase compensation techniques
21
Chapter 2
Out of the techniques mentioned above only the Fourier transform, Vector
control and wavelet transform methods provide both the voltage magnitude and phase
shift information. PLL method can provide only the phase shift information while
peak value detection technique enables to get the magnitude change (voltage sag)
information. Hence it is possible to combine one or more techniques mentioned above
to obtain accurate voltage sag compensation.
22
Chapter 2
Generally the DVRs use Phase Locked Loop (PLL) to keep a track of the
frequency and the phase angle of the healthy supply voltage, and thereby any change
from the normal operating condition can easily be detected [11,31]. Phase locked loop
is a closed loop feedback control system, that generates a signal with the same
frequency and the phase angle of the input signal. It consists of an oscillator which
provides the output signal. The PLL internal function can be categorized as phase
detector, variable oscillator and a feedback path. PLL responds to frequency changes
and phase angle changes of the input signal by increasing or decreasing the frequency
of the oscillator until it is matched with those of the reference input signal.
Simplified PLL is shown in Figure 2.13. The phase angle of the input signal is
compared with the feedback output of the oscillator and produces an error signal. The
error signal is generated in the form of voltage signal, proportional to the phase angle
difference between the input and output. The output of the phase detector consists of
harmonic components, thus it has to pass through a low pass filter. But this filtering
can introduce transient delays in detecting the voltage sags, which is undesirable
[4,32].
The controlled voltage output 2 of the loop filter is then feed in to the Voltage
controlled oscillator and provides a phase output. This output signal (in the form of a
phase angle) is negatively feedback into the phase detector. The output of the
oscillator is compared with the input and if the two frequencies are different, the
frequency of the oscillator is adjusted to match with the input frequency.
2
The controlled voltage output of the phase locked loop is a function of frequency.
23
Chapter 2
However reference [3] says that this method to track the phase angle is not
accurate and not suitable for fast synchronization. Further with this method it cannot
return the sag depth information and difficult to implement in real-time [4]. Hence a
more accurate method to detect the phase angle is introduced and referred to as
Software Phase Locked Loop (SPLL).
24
Chapter 2
The basic principal behind the operation of SPLL is regulating the Vsqn to zero
and to track the phase angle (θ) of the positive sequence voltage of the supply wave
form. Initial phase angle information of the supply waveform is given by this θ. Then
the voltage output of the SPLL will be equal to Vsd. By comparing Vsd with a set
reference point any occurrence of voltage sag magnitude can be detected. The same
way by comparing Vsq with a set reference zero the phase angle jump can be detected.
This is further explained in Figure 2.15. It is clear from the figure, when Vsqn tends to
zero Vsdn is in phase with Vsn (normalized supply voltage), hence any voltage sag can
easily be detected by the system.
β
ω
Vsqn
ω
d
θ б
Vsαn α
⎛ V sβ n ⎞
σ = tan −1 ⎜⎜ ⎟
⎟
V
⎝ sαn ⎠
(σ − θ ) ≈ sin (σ − θ ) = sin (γ )
Vsqn
sin γ =
Vsdn 2 + Vsqn 2
when Vsqn → 0, sin γ = 0,
γ = 0 and θ = σ
Step 1
The phase voltages (Vsa, Vsb and Vsc) are converted into stationary reference
frame voltage quantities (Vsα and Vsβ) using the following transformation.
25
Chapter 2
2
Assumption : Vs = v sα + jv sβ = (v sA + αv sB + α 2 v sC )
3
⎡V sa ⎤
⎡V sα ⎤ 2 ⎡1 −1 2 − 1 2 ⎤⎢ ⎥
⎢V ⎥ = V sb Eq. 2.1
⎣ sβ ⎦ 3 ⎢⎣0 3 2 − 3 2⎥⎦ ⎢ ⎥
⎢⎣V sc ⎥⎦
Step 2
The stationary reference frame voltage quantities are converted into
synchronous rotating reference frame voltage quantities (Vsd and Vsq) rotating by an
angle θ.
⎡Vsd ⎤ ⎡ cos θ sin θ ⎤ ⎡Vsα ⎤
⎢V ⎥ = ⎢ ⎢ ⎥ Eq. 2.2
⎣ sq ⎦ ⎣− sin θ cos θ ⎥⎦ ⎣Vsβ ⎦
Step 3
The Vsd and Vsq values obtained in step 2 are normalized as follows.
Vsd ⎫
Vsdn = ⎪
2 2
Vsd + Vsq ⎪
⎬ Eq. 2.3
Vsq ⎪
Vsqn =
2
Vsd + Vsq
2 ⎪
⎭
Step 4
The next step is to control the angle θ such that the normalized Vsqn=0. This is
achieved using a PI controller. The response time can be varied by changing Kp and
KI values of the PI controller. Then the output of the PI controller is added to ωs,
angular frequency at rated operating condition. Then pass it through a resettable
integrator to obtain the desired SPLL output θ.
26
Chapter 2
the Vd and Vq from their normally operated values. This is how the fast detection
normally implemented.
The peak value of any waveform is the point at which its gradient tends to
zero. This simple phenomenon is used in this technique. The point at which voltage
gradient is zero is identified as the peak value of the supply voltage [32]. It is
compared with a preset reference voltage. If the voltage difference between the supply
and the reference voltage exceeds a specified value (eg. 10%) then the DVR starts
operating (DVR inject the difference voltage). The voltage gradient can be calculated
as follows.
vt − vt −δt
Voltage Gradient = Eq. 2.4
δt
vt is the voltage at time instant t and vt −δt is the voltage at time t − δt where δt is a
As in reference [32], the drawbacks of this method are the time delay (up to
0.5 sec.) in getting the sag depth information and the noise that would affect the
measurements severely. Further to get the phase shift information a reference
waveform is needed which has to be generated separately.
The wavelet transform is similar to the Fourier transform with the basic
difference that in wavelet transform it is possible to represent a signal both in time
domain and frequency domain 3 , but the integral transform can perform only in one
direction [33]. The shortcomings of this technique are the difficulty in directly
interpreting the results and difficulty in real time implementation [4].
3
Fourier transform is a frequency domain representation of a signal and can perform the integral
transform in both directions.
27
Chapter 3
3.1 Background
The major drawback of the existing voltage sag detection techniques discussed
in section 2.5 is that, it is costly and complicated to control the voltage injection for a
single phase fault, where most frequent fault occurred in a targeted phase. As such it
will be an easier alternative to control the voltage injection in the phases individually
using three single phase DVRs. In this case the voltage injection in each phase is
controlled independently to the other phases. This arrangement of DVR gives
possibility of installing single-phase DVR if only one phase is identified with frequent
interruptions.
28
Chapter 3
device, which will directly affect the cost of the DVR, if the sag continues for a longer
duration. In-phase compensation technique compensates only for the voltage
magnitude and as a result the compensated load voltage will undergo a phase shift if
the voltage sag is associated with a phase jump. Thereby the requirement of a higher
capacity energy storage device can be bargained. In the developed control strategy, at
the beginning of the sag the DVR compensate both for the voltage magnitude change
and the phase shift as well, same as pre-sag compensation and restored the load
voltage back to the pre-sag voltage. Then the controller smoothly transfers the
compensation technique from pre-sag to in-phase technique thus the developed
control plays an intelligent role to minimize the DVR rating while maintaining load
voltage without experiencing any disturbance.
Further to detect the occurrence of voltage sag, peak value of the supply
voltage was constantly monitored. The measurement method was discussed under
section 2.5.4.
It is important to note that the small frequency variations (within the allowable
range defined by IEEE) of the supply voltage is tolerable and can be tracked by this
control mechanism without any compensation. The frequency variations beyond the
defined range (±1%) are assumed to be taken care by the system control of the utility.
29
Chapter 3
Then the reference voltage waveform was created from the reference phase
angle and rated rms load voltage. Finally, the voltage that needed to be injected by the
DVR was calculated by subtracting the measured supply voltage from the reference
voltage waveform.
The control block diagram related to the above is shown in Figure 3.1 below.
Figure 3.1: Simplified control block diagram for the single phase DVR
30
Chapter 3
Phase angle of
Rated Resettable the supply
2πf frequency integrator voltage
Clear signal to
Supply Zero crossing the integrator
voltage point Limiter
waveform detection
Input
1
314.1593
sT Ameas
Clear
Zero
Detector
Vs Clear_signal
ZCD
As shown in Figure 3.3, the input signal to this integrator is the angular
frequency of the input waveform, i.e. the 2πf=314.1593 (constant), with f being the
nominal supply frequency 50Hz. Then the output supply phase angle waveform (or
the integrator output) is a line with a gradient of 314.1593(or y=314.1593.t shape) 1 .
This signal is re-setted at every supply cycle in order to obtain the phase angle
information. This re-set function is achieved by introducing a clear signal. The clear
signal is obtained from the positive zero crossing detector, made of zero crossing
detector with positive side limiter, of the supply waveform This will ensure the clear
signal is activated per cycle.
Different components parameters of the above Figure 3.3 were selected as follows.
1
When a constant of magnitude m is integrated with respect to time the output will be in the form of
y=mt, where m being the gradient of the linear output signal.
31
Chapter 3
1) Supply voltage (Vs): This is the input voltage signal from the particular supply
phase feed from the distribution transformer. 240 V, 50 Hz sinusoidal input source
with an internal series impedence of 0.01 Ω was taken. During the sag this input
voltage reduced depending on the severity of the upstream fault.
2) Zero crossing detector (ZCD): This component produce an output of 1, when the
input crosses the zero value axis at its positive gradient and -1 at the negative
gradient zero crossing point. At all the other times the output will be zero. This is
shown in Figure 3.4.
3) Limiter: This limits the negative signal. Thus this will detect only the positive
part of the zero crossing detector’s output signal. This enables to detect the cycle
time of the supply voltage waveform. The output (as in Figure 3.5) is directly feed
into the integrator as the clear signal.
32
Chapter 3
PSCAD output waveforms at different output channels are shown in figure 3.7
and 3.8 below.
33
Chapter 3
Implementation of Block 1
Supply voltage ZCD Clear_signal Angle meas*0.1
1.00
voltage (kV) & phase angle (rad)
0.75
0.50
0.25
0.00
-0.25
-0.50
-0.75
-1.00
time(s) 0.450 0.460 0.470 0.480 0.490 0.500 0.510 0.520 0.530
Figure 3.7: Output waveforms at different output channels
34
Chapter 3
1
314.1593 D + -
Angle Error
sT Aref
A A
Aref D + - Ctrl = 1 Compar-
ator
P
F B * B 6.2832
0.0
Ameas 10.0
Figure 3.9: Simulation block for the reference phase angle wave form generation
In the block as shown in Figure 3.9, a random reference phase angle signal is
generated. The reference signal’s phase angle is synchronized with the measured
signal phase angle by slowly adjusting the gradient (angular frequency) of the
randomly generated reference phase angle signal.
The simulation block diagram shown in Figure 3.9 consists of 3 major blocks
and is shown in Figure 3.10 and discussed in 3.3.2.1-3.
3.3.2.1 Calculate the angle error between the reference and the supply phase
angle.
Initially a random reference phase angle wave from was created for a
frequency of 50Hz. Then a simple comparator block was used to calculate the angle
error. As seen in the Figure 3.11 below the angle error between the two waveforms
35
Chapter 3
are varying from positive to negative during each cycle. Further the average error is
zero.
Reference phase angle Measured phase angle
Angle error
A
Ctrl = 1
Angle error
B *
0.0 10.0 to the filter etc..
Ctrl
36
Chapter 3
The measured phase angle waveform was fixed during the normal operation.
Hence it can be used as a reference to calculate the angle error. Two points closer to
the middle of the phase angle waveform (2.5 rad to 3.5 rad) were selected and when
the measured phase angle waveform is within those limits, the block calculates the
angle error. When the measured phase angle was beyond the given limit the block
doesn’t calculate any angle error. This technique is used mainly to get the error which
clearly differentiates the angle lead or lag and proportional to its magnitude. A range
comparator was used to achieve this task and its specifications are as shown in Figure
3.12.
Comparator will generate an output of 1 when the input (supply phase angle in
radians) is between 2.5-3.5. Except this limits, it will generate a zero output as angle
error. When selecting the comparator limits care has to be taken to maintain the same
magnitude of the angle error. (i.e. within the selected limit the angle error should not
change its sign.)
It is clear from Figure 3.13; the angle error is definitely a negative value (or
can be definitely positive either if Aref is leading Ameas) as the points considered are
37
Chapter 3
only between 2.5 rad to 3.5 rad. If the comparator limits were selected closer to the
ends such as 0 rad or 6.2832 rad then the angle error varies its sign, which is not
desirable.
A two way input selector switch was used to generate an output only when the
triggering pulse is present i.e. when it is 1. The obtained angle error was multiplied by
a factor 10 to speed up the synchronization and obtain more accurate synchronization.
Then the angle error signal was passed through a filter and a PI controller.
The angle error wave form obtained above is a pulsed waveform consists of
harmonics. To achieve better synchronization the error has to be regulated to zero,
while converting the pulse signal into a smooth one. A low pass LC filter and a PI
control was added to achieve that purpose and explained below.
A filter with a second order transfer function was used. It attenuates the
frequencies above the characteristic frequency. A 500 Hz was selected as a reasonable
value for the characteristic frequency. This passes the frequency components below
the 500 Hz which will attenuate the harmonics to a reasonable level. Gain and the
damping ratio of this low pass filter were selected to be 1 to maintain the same
magnitude and the wave shape of the input during filtering.
3.3.2.3.2 PI controller
A Proportional Integrate controller was used to regulate the error between the
measured (supply) and the reference phase angle to zero.
Reasons for selecting a PI controller
38
Chapter 3
In the PSCAD simulation block for the PI controller following parameters has
to be defined as shown in Figure 3.14.
Among those parameters proportional gain (Kp) and the integral time constant
(KI) directly affect the performance of the PI controller. When tuning those two
parameters special attention has to be paid. The maximum and the minimum limits of
the PI controller was selected, as the output at any instant doesn’t exceed those two
values. (+10 and -10) At the beginning of the simulation (at t=0) the controller set to
zero output. Hence the initial output is assigned to zero.
2
The derivative action of the PID controller speeds up the system response.
39
Chapter 3
Initially KI (Integral time constant) was set at a high value and the simulations
were carried out for different Kp values. It has been observed that with increasing Kp
the time taken to reach the target decrease, Kp=0.5 was selected as reasonable. Then
by reducing the KI the simulation results were observed. The PI output reaches the
target and stabilizes after longer time. Hence KI was selected as 0.2, which is same as
5sec time constant.
40
Chapter 3
The next step is to generate the reference phase angle waveform. The gradient
of the reference signal is known and the reference phase angle should vary from 0 to
2π (6.2832) radians. Therefore the reference phase angle waveform should be cleared
when it reaches 2π. A comparator and a resettable integrator are used to achieve this
resetting. The integrator clear signal is given by the comparator output. This block is
shown in Figure 3.16 together with the comparator specifications.
1
output of the summing/ sT Aref
differncing junction Clear
A
Compar-
ator
B 6.2832
The function of the above block is similar to block 1 described in 3.3.1. The
comparator compares the magnitude of the Aref signal with the set value (6.2832) and
41
Chapter 3
when the Aref > 6.2832, the integrator clear signal is reset and thus the integrator
output set to zero.
The reference phase angle was generated and synchronized with the supply
(measured) phase angle. Next step is to generate the reference voltage waveform from
the reference phase angle information. From the phase angle information obtained a
sinusoidal waveform was generated with the nominal supply voltage magnitude as in
Figure 3.17. (240V rms = 340V peak)
Sin *
Aref Vref
0.34
42
Chapter 3
The block no. 4 was used to calculate the control voltage by taking the
difference between the reference and the supply voltage. When the supply voltage is
in normal condition (no voltage sag), both the supply and the reference voltage
waveforms are in phase and same in magnitude thus the voltage to be injected by the
DVR circuit would be zero.
The control voltage will be present only during the voltage sag. The shape of
the control voltage waveforms for different sag conditions are shown in Figures 3.19.
Control voltage during the voltage sag Control voltage during the voltage sag
(both the reference and the supply are in phase) (reference and the supply voltages are not in phase)
0.25 0.25
reference reference voltage
0.2 voltage 0.2
0.05 0.05
Voltage (kV)
Voltage (kV)
0 0
-0.05
-0.05 control voltage
-0.1
-0.1
-0.15
-0.15
-0.2
-0.2
-0.25
-0.25 0 0.005 0.01 0.015 0.02 0.025 0.03 0.035 0.04
0 0.005 0.01 0.015 0.02 0.025 0.03 0.035 0.04 time (sec)
time (sec)
43
Chapter 3
It is clear from the above figures irrespective of the type of voltage sag (in phase or
not with the reference voltage) the control voltage is a pure sinusoidal waveform with
varying magnitude during the sag period.
A
Vref D + -
Ctrl = 1
F B
Vs Vcontrol
Ctrl
0.0
TIME
The block shown in dashed lines is used to provide the time delay switching
signal to start operation of the DVR. When the input time signal is above the specified
value the comparator will generate a signal of 1 and 0 otherwise. When the
comparator output is 1 the block starts calculating the control voltage that needs to be
injected by the DVR circuit.
Further it should be noted that in the simulation, the synchronization time
depends on the initial phase shift between the supply voltage and the internally
generated reference voltage and also the parameters of the PI controller. If both the
44
Chapter 3
wave forms are in phase at the beginning, then theoretically two waveforms should
get synchronized from the beginning itself since the angle error is zero. But it was
realized that due to the involvement of the feedback control loop and its initial setting
values, still it takes some time for synchronization. By considering all of theses
effects, to eliminate the start up transients it has given 4 seconds in the simulation to
synchronize and stabilize the controller action. There after the controller will be ready
for the DVR operation.
In the block 4, the voltage that needs to be injected to the DVR was calculated.
Next step is to create a power circuit consisting of the units described in section 2.2,
which is capable of generating the above calculated control voltage.
The power circuit of the single phase DVR mainly consists of Energy storage
device, inverter, filter and a voltage injection transformer and is shown in Figure 3.21.
45
Chapter 3
Suitable values for VDC, C1, LF, CF, Rs, Rl and transformer turn ratio n have to be
determined.
46
Chapter 3
If the DVR is capable of compensating for a full voltage sag (when Vsup=0)
then,
Vinj_max =Vs=240V rms.
V1 1 I
For voltage transformer, = = L
Vinj n I 1
For safety point of view n is kept at a high value to maintain a low voltage at
the primary side of the transformer. Therefore the turn ratio of the transformer is
selected as 4.
Then,
230 2
V1 _ peak = = 81.31V
4
from (1) V1 _ peak < Einj
∴ Einj ≈ 100V is a reasonable value.
but, Einj = VDC = 100V
Two batteries of 50V each are used to provide the real power requirement
during the voltage sag compensation.
Two-leg inverter consisting four IGBTs and four diodes are used for single
phase voltage sag detection. Inverter legs are switched on and off accordingly, such
that the desired control voltage can be obtained at the filter output point.
47
Chapter 3
As can be seen from the Figure 3.24, the control voltage was reduced by a
factor of 4, before comparing it with the triangular waveform to compensate for the
transformation ratio of the voltage injection transformer. The level comparator
produces two output levels as shown in Figure 3.25.
Tri
A
Tri Compar- Pbot Ptop
ator
* B
Vcontrol 0.25 Vcontrol1
48
Chapter 3
The output signal of the comparator (Pbot) and the NOT operated inversion
(Ptop) is fed into the inverter legs.
To achieve a smooth control voltage (= injected voltage to the power line) and
to filter out the unwanted higher order harmonic components from that waveform a
LC filter was connected at the output of inverter.
1
f= Eq. 3.2
2π LC
Cut-off frequency should lie between the supply frequency (50Hz) and the
modulating triangular waveform frequency (5000Hz). Therefore 500Hz was selected
49
Chapter 3
as the cut-off frequency and capacitor value was calculated assuming L = 0.6 mH. By
applying L and f values to equation 3.1, the capacitor value was obtained as 168μF.
But during the simulation it has been identified that with the above calculated
LC values the compensated voltage could not block the harmonic up to the required
level. It has been observed that by modifying the filter, the quality of the output
waveform could be improved to a certain level. Therefore the filter configuration
shown in Figure 3.21 was slightly modified as in Figure 3.26 to remove the harmonic
effect.
For simplicity it has been assumed that the inductor value is halved for the
new filter configuration, while keeping the same value for capacitance. The DVR side
inductor smoothes the waveform while the grid side inductor block the harmonic
injection.
Further it has been observed that, better performance of the DVR could be
obtained by increasing the capacitance. After comparing the results of several
simulations for different Capacitances 1000μF was selected as a reasonable value.
Therefore subsequent simulations the capacitance value is taken as 1000μF.
50
Chapter 3
The voltage sag was created in the distribution line by switching on a shunt
connected circuit breaker together with a series reactance. This can either be a
resistance, inductance or a combination. In this case for simplicity of calculations
resistive fault impedance was taken for the fault and grid. This is presented in Figure
3.28.
51
Chapter 3
Timed
BRK
Breaker
0.01
Vs Logic
BRK
Open@t0
0.01
From the low VInj
#1 #2
pass filter Iload
100.0
VL
Figure 3.28: Left: Generating voltage sag for the power circuit, Right: Breaker parameters
From Figure 3.28 left, it is clear that the circuit breaker is initially in open
position. As such there will be no sag voltage applied. To create the sag the breaker
was closed at t = 5.21sec and the sag is remained for 70 msec. For further analysis the
above circuit simplified as shown in Figure 3.29
Before the voltage sag, the circuit breaker is kept at open position. An open
circuited path was created across the breaker. As the system is under normal
condition, the DVR is not injecting any voltage to the distribution line (Vinjected=0V).
The equivalent circuit for the above is as follows in Figure 3.30.
52
Chapter 3
Vs
I before =
Rs + RL
VLn = I before ⋅ RL
Vs RL
VLn =
Rs + RL
Assume a case when the voltage sag is present, but the DVR is not connected
to the circuit as in Figure 3.31.
Vs Vs
I sag = =
R s + (R L // R sag ) ⎛ R L ⋅ R sag ⎞
Rs + ⎜ ⎟
⎜ R L + R sag ⎟
⎝ ⎠
R sag
I 2 = I sag ⋅
R L + R sag
Vs ⋅ R sag ⋅ R L
VL sag = I 2 ⋅ R L =
R s (R L + R sag ) + R L ⋅ R sag
This analysis shows that by changing Rsag parameter, the magnitude of the sag
can be altered. The typical values selected for the simulation was RL=100Ω and
Rsag=0.01Ω. It can be seen that RL>>>>Rsag.
RL
Hence, + 1 >>>> 1
R sag
Vs ⋅ R L Vs ⋅ R L Vs ⋅ R L
VL sag = = <
R s (R L + R sag ) ⎛ R ⎞ Rs + RL
+ RL R s ⋅ ⎜ L + 1⎟ + R L
R sag ⎜ R sag ⎟
⎝14243⎠
>>>>1
Vs ⋅ R L
but, = VL n
Rs + RL
hence, VL sag < VL n
53
Chapter 3
The load voltage during the sag is less than the healthy load voltage.
Then Vinj = VL n − VL sag ; which is the voltage injected by the DVR during the sag
period.
The above calculations were performed assuming both the Rsag and RL are
resistive loads. By changing the magnitude and the type of the shunt connected fault
impedance, the severity of the voltage sag can be changed. For example, if an
inductive impedance is connected having the same reactance, (2πfL=Rsag ), the
voltage sag can be created with the same magnitude but with a phase shift. The
simulations were carried out by considering the following sag and loading conditions.
(i) Sag without a phase shift and the sag was created at the zero crossing point of the
voltage waveform.
(ii) Sag without a phase shift and the sag was created not at the zero crossing point of
the voltage waveform.
(iii) Sag with a phase shift and the sag was created at the zero crossing point of the
voltage waveform.
(iv) Sag with a phase shift and the sag was created not at the zero crossing point of
the voltage waveform.
54
Chapter 3
components present in the supply, a harmonic analysis was carried out for practical
the supply voltage using a digital power meter available in the laboratory. The
measured harmonic components and their magnitudes are shown in below Table 3.1.
The shape of the supply waveform with healthy and with those harmonics was
simulated in PSCAD and is shown in Figures 3.32 and 3.33 together with the
simulation block.
55
Chapter 3
Voltage (kV)
0.10
0.00
-0.10
-0.20
-0.30
-0.40
Supply voltage (with harmonics)
0.40
0.30
0.20
Voltage (kV)
0.10
0.00
-0.10
-0.20
-0.30
-0.40
Time ... 0.0000 0.0050 0.0100 0.0150 0.0200 0.0250 0.0300 0.0350 0.0400
Vs
100.0
Vs Supply voltage (with harmonics) Load
Due to the limitations in implementing all the harmonic components in PSCAD only
marked “*” major 15 harmonics were considered for the simulation. Those harmonic
components were added to the supply voltage as shown in Figure 3.43 and observed
the effect on the load voltage by introducing voltage sag.
56
Chapter 4
The simulation is carried out and the results are analyzed for different voltage
sag and load conditions as discussed in chapter 3 and briefly given below.
To simplify the analysis the simulations were carried out under the following
different cases as shown in Table 4.1.
57
Chapter 4
duration (s)
Harmonics
Phase shift
Subsystem
System
Start at[3]
supply[7]
in the
type[5]
Time
Fault
Load
PF[6]
[1]
[2]
[4]
1a 0.01Ω-R N zc 5.1-5.13 100Ω-R 1 N
1b 0.01Ω-R N nzc 5.105-5.135 100Ω-R 1 N
1
1c 0.01Ω-R N nzc 5.113-5.143 100Ω-R 1 N
1d 0.01Ω-R N nzc 5.102-5.189 100Ω-R 1 N
2a 0.01Ω-R N zc 5.1-5.13 80Ω+0.191H-RL 0.8 N
2b 0.01Ω-R N nzc 5.105-5.135 80Ω+0.191H-RL 0.8 N
2
2c 0.01Ω-R N nzc 5.113-5.143 80Ω+0.191H-RL 0.8 N
2d 0.01Ω-R N nzc 5.102-5.189 80Ω+0.191H-RL 0.8 N
3a 0.03183mH-L Y zc 5.1-5.13 100Ω-R 1 N
3b 0.03183mH-L Y nzc 5.105-5.135 100Ω-R 1 N
3
3c 0.03183mH-L Y nzc 5.113-5.143 100Ω-R 1 N
3d 0.03183mH-L Y nzc 5.102-5.189 100Ω-R 1 N
4a 0.03183mH-L Y zc 5.1-5.13 80Ω+0.191H-RL 0.8 N
4b 0.03183mH-L Y nzc 5.105-5.135 80Ω+0.191H-RL 0.8 N
4
4c 0.03183mH-L Y nzc 5.113-5.143 80Ω+0.191H-RL 0.8 N
4d 0.03183mH-L Y nzc 5.102-5.189 80Ω+0.191H-RL 0.8 N
5a 0.005Ω-R N nzc 5.102-5.189 100Ω-R 1 N
5b 0.005Ω-R N nzc 5.102-5.189 80Ω+0.191H-RL 0.8 N
5
5c 0.01592mH-L Y nzc 5.102-5.189 100Ω-R 1 N
5d 0.01592mH-L Y nzc 5.102-5.189 80Ω+0.191H-RL 0.8 N
6a 0.01Ω-R N nzc 5.105-5.135 50Ω-R 1 N
6b 0.01Ω-R N nzc 5.105-5.135 40Ω+0.096H-RL 0.8 N
6
6c 0.03183mH-L Y nzc 5.105-5.135 50Ω-R 1 N
6d 0.03183mH-L Y nzc 5.105-5.135 40Ω+0.096H-RL 0.8 N
7a 0.01Ω-R N nzc 5.102-5.189 100Ω-R 1 Y
7b 0.01Ω-R N nzc 5.102-5.189 80Ω+0.191H-RL 0.8 Y
7
7c 0.03183mH-L Y nzc 5.102-5.189 100Ω-R 1 Y
7d 0.03183mH-L Y nzc 5.102-5.189 80Ω+0.191H-RL 0.8 Y
Table 4.1: Different sag and load criteria
58
Chapter 4
Each system was selected in such a way that covers all possible practical situations
and explained as below:
[1]
Describes whether the sag is resistive (R), Inductive (L) or a combination of both
(RL) and the magnitude of it.
[2]
This specifies the sag is associated with a phase shift (Y) or not (N). This is a direct
result of criteria [1] above.
[3]
Whether the sag has commenced at zero crossing point of the voltage (zc) or not
(nzc).
[4]
This column indicates the duration of voltage sag.
[5]
The magnitude and type of load connected; resistive load (R), Inductive load (L) or
a combination (RL).
[6]
Load power factor
[7]
Indicates the harmonics in the supply voltage.
In the simulation, all four blocks, which were described in section 3.3 in the
control circuit, is common for all the cases considered above and is shown in Figure
4.1.
59
Chapter 4
1
314.1593
sT Ameas
Clear
Zero
Detector
Vs
Block 1
1
314.1593 D + Aref
- sT
F Clear
Aref D + -
F A A
Ameas Ctrl = 1 Compar-
ator
P
B * B 6.2832
0.0 10.0
Ctrl I
Block 2
Ameas
A
Vref D + - Ctrl = 1
F B
Vs Vcontrol
Sin * Ctrl
Aref Vref
0.0
0.34
TIME
Block 3
Block 4
The power circuit in Figure 4.2, only the blocks A (fault ), B (load ), C
(breaker operating conditions) and D (harmonic content in the supply) will change
depending on the different cases considered in Table 4.1.
60
Chapter 4
Tri
Timed
A Breaker
Tri Compar- Pbot Ptop BRK Logic
ator Open@t0
* B
Vcontrol 0.25 Vcontrol1 C
BRK
0.01
Vs
D A
R=0
0.01
I D I D
Pbot Ptop
0.0003 0.0003
1000.0
Eb #1 #2 VInj
10000.0
Ea
Iload
VL
100.0
R=0
B
I D I D
Ptop Pbot
Figure 4.2: Power circuit of the DVR indicating the components change for different cases
All the subsystems considered above can be identified by the parameters in the
above sections A, B, C and D.
61
Chapter 4
4.1 System 1
Load = 100Ω
Fault = 0.01Ω
Peak injected voltage during synchronization was about 11V. This is mainly
due to the DVR internal voltage drop. This can also be eliminated by adding an
auxiliary control to compensate the DVR internal voltage drop.
0.00
-0.10
-0.20
-0.30
-0.40
Time ... 0.040 0.060 0.080 0.100 0.120 0.140
0.00
-0.10
-0.20
-0.30
-0.40
Time ... 0.980 1.000 1.020 1.040 1.060 1.080
Figure 4.4: Voltage waveforms for system 1 when the DVR is engaged
62
Chapter 4
4.1.1 Subsystem 1a
This section shows the simulation results when fault occurred at the zero crossing
voltage point without any phase shift.
0.00
-0.10
-0.20
-0.30
-0.40
Time ... 0.560 0.580 0.600 0.620 0.640 0.660
Figure 4.5: Voltage waveforms for subsystem 1a during the neighborhood of sag
0.00
-0.10
-0.20
-0.30
-0.40
Time ... 0.600 0.610 0.620 0.630 0.640
63
Chapter 4
4.1.2 Subsystem 1b
This section shows the simulation results when fault occurred at peak of the supply
voltage without any phase shift.
0.10
0.00
-0.10
-0.20
-0.30
Figure 4.7: Voltage waveforms for subsystem 1b during the neighborhood of sag
0.10
0.00
-0.10
-0.20
-0.30
-0.40
Time ... 0.600 0.610 0.620 0.630 0.640
64
Chapter 4
4.1.3 Subsystem 1c
This section shows the simulation results when fault occurred at negative gradient
point of the supply voltage without any phase shift.
0.00
-0.10
-0.20
-0.30
-0.40
Figure 4.9: Voltage waveforms for subsystem 1b during the neighborhood of sag
0.00
-0.10
-0.20
-0.30
-0.40
65
Chapter 4
4.1.4 Subsystem 1d
This section shows the simulation results when fault occurred at positive gradient
point of the supply voltage without any phase shift.
0.00
-0.10
-0.20
-0.30
Figure 4.11: Voltage waveforms for subsystem 1b during the neighborhood of sag
0.00
-0.10
-0.20
-0.30
66
Chapter 4
4.2 System 2
Load = 80Ω+0.191H ( 0.8 lagging power factor)
Fault = 0.01Ω
0.00
-0.10
-0.20
-0.30
-0.40
Time ... 0.440 0.460 0.480 0.500 0.520 0.540
0.00
-0.10
-0.20
-0.30
-0.40
Time ... 0.980 1.000 1.020 1.040 1.060 1.080
Figure 4.14: Voltage waveforms for system 2 when the DVR is engaged
67
Chapter 4
4.2.1 Subsystem 2a
This section shows the simulation results when fault occurred at the zero crossing
voltage point without any phase shift.
0.00
-0.10
-0.20
-0.30
-0.40
Time ... 0.600 0.620 0.640 0.660 0.680 0.700
Figure 4.15: Voltage waveforms for subsystem 1b during the neighborhood of sag
0.00
-0.10
-0.20
-0.30
-0.40
Time ... 0.590 0.600 0.610 0.620 0.630 0.640
68
Chapter 4
4.2.2 Subsystem 2b
This section shows the simulation results when fault occurred at peak of the supply
voltage without any phase shift.
Peak injected voltage during the first cycle after the voltage sag ≈ 250V
Peak load voltage during the first cycle after the voltage sag ≈ 420V
Peak injected voltage during the second cycle after the voltage sag ≈175V
Peak load voltage during the second cycle after the voltage sag ≈ 360V
0.00
-0.10
-0.20
-0.30
-0.40
Figure 4.17: Voltage waveforms for subsystem 2b during the neighborhood of sag
0.00
-0.10
-0.20
-0.30
-0.40
Figure 4.18: Voltage waveforms for subsystem 2b during the neighborhood of sag
69
Chapter 4
4.2.3 Subsystem 2c
This section shows the simulation results when fault occurred at negative gradient
point of the supply voltage without any phase shift.
Peak injected voltage during the first cycle after the voltage sag ≈ 220V
Peak load voltage during the first cycle after the voltage sag ≈ 430V
Peak injected voltage during the second cycle after the voltage sag ≈ 180V
Peak load voltage during the second cycle after the voltage sag ≈ 370V
0.30
0.20
0.10
Voltage (kV)
0.00
-0.10
-0.20
-0.30
-0.40
Figure 4.19: Voltage waveforms for subsystem 2c during the neighborhood of sag
0.00
-0.10
-0.20
-0.30
-0.40
70
Chapter 4
4.2.4 Subsystem 2d
This section shows the simulation results when fault occurred at positive gradient
point of the supply voltage without any phase shift.
0.00
-0.10
-0.20
-0.30
-0.40
Time ... 0.600 0.620 0.640 0.660 0.680 0.700 0.720
Figure 4.21: Voltage waveforms for subsystem 2d during the neighborhood of sag
0.00
-0.10
-0.20
-0.30
-0.40
Time ... 0.600 0.610 0.620 0.630 0.640 0.650 0.660
71
Chapter 4
4.3 System 3
Fault = 0.03183mH
Load = 100Ω
0.00
-0.10
-0.20
-0.30
-0.40
Time ... 0.540 0.560 0.580 0.600 0.620 0.640
0.00
-0.10
-0.20
-0.30
-0.40
Time ... 0.980 1.000 1.020 1.040 1.060
Figure 4.24: Voltage waveforms for system 3 when the DVR is engaged
72
Chapter 4
4.3.1 Subsystem 3a
This section shows the simulation results when fault occurred at the zero crossing
voltage point with a phase shift.
0.00
-0.10
-0.20
-0.30
-0.40
Time ... 0.580 0.600 0.620 0.640 0.660
Figure 4.25: Voltage waveforms for subsystem 3a during the neighborhood of sag
0.00
-0.10
-0.20
-0.30
-0.40
Time ... 0.580 0.590 0.600 0.610 0.620 0.630 0.640
73
Chapter 4
4.3.2 Subsystem 3b
This section shows the simulation results when fault occurred at peak of the supply
voltage with a phase shift.
Peak injected voltage during the first cycle after the voltage sag ≈ 187V
Peak load voltage during the first cycle after the voltage sag ≈ 339V
Peak injected voltage during the second cycle after the voltage sag ≈193V
Peak load voltage during the second cycle after the voltage sag ≈ 341V
0.00
-0.10
-0.20
-0.30
-0.40
Time ... 0.580 0.600 0.620 0.640 0.660 0.680
Figure 4.27: Voltage waveforms for subsystem 3b during the neighborhood of sag
0.00
-0.10
-0.20
-0.30
-0.40
Time ... 0.610 0.620 0.630 0.640
74
Chapter 4
4.3.3 Subsystem 3c
This section shows the simulation results when fault occurred at negative gradient
point of the supply voltage with a phase shift.
Peak injected voltage during the first cycle after the voltage sag ≈ 200V
Peak load voltage during the first cycle after the voltage sag ≈ 338V
Peak injected voltage during the second cycle after the voltage sag ≈ 188V
Peak load voltage during the second cycle after the voltage sag ≈ 338V
0.00
-0.10
-0.20
-0.30
-0.40
Time ... 0.600 0.620 0.640 0.660 0.680 0.700
Figure 4.29: Voltage waveforms for subsystem 3c during the neighborhood of sag
0.00
-0.10
-0.20
-0.30
-0.40
Time ... 0.610 0.620 0.630 0.640 0.650 0.660
75
Chapter 4
4.3.4 Subsystem 3d
This section shows the simulation results when fault occurred at positive gradient
point of the supply voltage with a phase shift.
0.00
-0.10
-0.20
-0.30
-0.40
Time ... 0.600 0.620 0.640 0.660 0.680 0.700 0.720
Figure 4.31: Voltage waveforms for subsystem 3d during the neighborhood of sag
0.00
-0.10
-0.20
-0.30
-0.40
Time ... 0.600 0.610 0.620 0.630 0.640 0.650 0.660
76
Chapter 4
4.4 System 4
Fault = 0.03183mH
Load = 80Ω+0.191H (0.8 lagging power factor)
0.00
-0.10
-0.20
-0.30
-0.40
Time ... 0.580 0.600 0.620 0.640 0.660 0.680 0.700
0.00
-0.10
-0.20
-0.30
-0.40
Time ... 0.980 1.000 1.020 1.040 1.060 1.080 1.100
Figure 4.34: Voltage waveforms for system 4 when the DVR is engaged
77
Chapter 4
4.4.1 Subsystem 4a
This section shows the simulation results when fault occurred at the zero crossing
voltage point with a phase shift.
0.00
-0.10
-0.20
-0.30
-0.40
Time ... 0.560 0.580 0.600 0.620 0.640 0.660 0.680
Figure 4.35: Voltage waveforms for subsystem 4a during the neighborhood of sag
0.00
-0.10
-0.20
-0.30
-0.40
Time ... 0.600 0.610 0.620 0.630 0.640
78
Chapter 4
4.4.2 Subsystem 4b
This section shows the simulation results when fault occurred at peak of the supply
voltage with a phase shift.
Peak injected voltage during the first cycle after the voltage sag ≈ 185V
Peak load voltage during the first cycle after the voltage sag ≈ 334V
Peak injected voltage during the second cycle after the voltage sag ≈ 205V
Peak load voltage during the second cycle after the voltage sag ≈ 350V
0.00
-0.10
-0.20
-0.30
-0.40
Time ... 0.560 0.580 0.600 0.620 0.640 0.660
Figure 4.37: Voltage waveforms for subsystem 4b during the neighborhood of sag
0.00
-0.10
-0.20
-0.30
-0.40
Time ... 0.600 0.610 0.620 0.630 0.640 0.650
79
Chapter 4
4.4.3 Subsystem 4c
This section shows the simulation results when fault occurred at negative gradient
point of the supply voltage with a phase shift.
Peak injected voltage during the first cycle after the voltage sag ≈ 215V
Peak load voltage during the first cycle after the voltage sag ≈ 344V
Peak injected voltage during the second cycle after the voltage sag ≈ 196V
Peak load voltage during the second cycle after the voltage sag ≈ 335V
0.00
-0.10
-0.20
-0.30
-0.40
Time ... 0.600 0.620 0.640 0.660 0.680 0.700
Figure 4.39: Voltage waveforms for subsystem 4c during the neighborhood of sag
0.00
-0.10
-0.20
-0.30
-0.40
Time ... 0.610 0.620 0.630 0.640 0.650 0.660 0.670
80
Chapter 4
4.4.4 Subsystem 4d
This section shows the simulation results when fault occurred at positive gradient
point of the supply voltage with a phase shift.
0.00
-0.10
-0.20
-0.30
-0.40
Time ... 0.600 0.620 0.640 0.660 0.680 0.700 0.720
Figure 4.41: Voltage waveforms for subsystem 4d during the neighborhood of sag
0.00
-0.10
-0.20
-0.30
-0.40
Time ... 0.600 0.610 0.620 0.630 0.640 0.650 0.660
81
Chapter 4
4.5 System 5
4.5.1 Subsystem 5a
Fault = 0.005 Ω
Load = 100Ω
Sag created at, t = 5.102 – 5.189 s
0.10
0.00
-0.10
-0.20
-0.30
Figure 4.43: Voltage waveforms for subsystem 5a during the neighborhood of sag
4.5.2 Subsystem 5b
Fault = 0.005 Ω
Load = 80Ω+0.191H (0.8 lagging power factor)
Sag created at, t = 5.102 – 5.189 s
0.00
-0.10
-0.20
-0.30
-0.40
Time ... 0.580 0.600 0.620 0.640 0.660 0.680 0.700 0.720 0.740
Figure 4.44: Voltage waveforms for subsystem 5b during the neighborhood of sag
82
Chapter 4
4.5.3 Subsystem 5c
Fault = 0.01592mH
Load = 100Ω
Sag created at, t = 5.102 – 5.189 s
Sub system 5c : During sag (@ t=5.102-5.189s)
Supply voltage Load voltage Vinjected
0.40
0.30
0.20
0.10
Voltage (kV)
0.00
-0.10
-0.20
-0.30
-0.40
Time ... 0.580 0.600 0.620 0.640 0.660 0.680 0.700 0.720 0.740
Figure 4.45: Voltage waveforms for subsystem 5c during the neighborhood of sag
4.5.4 Subsystem 5d
Fault = 0.01592mH
Load = 80Ω+0.191H (0.8 lagging power factor)
Sag created at, t = 5.102 – 5.189 s
0.00
-0.10
-0.20
-0.30
-0.40
Time ... 0.580 0.600 0.620 0.640 0.660 0.680 0.700 0.720 0.740
Figure 4.46: Voltage waveforms for subsystem 5d during the neighborhood of sag
83
Chapter 4
4.6 System 6
4.6.1 Subsystem 6a
Fault = 0.01 Ω
Load = 50Ω
Sag created at, t = 5.102 – 5.189 s
Sub system 6a : During sag (@ t=5.102-5.189s)
Supply voltage Load voltage Vinjected
0.40
0.30
0.20
0.10
Voltage (kV)
0.00
-0.10
-0.20
-0.30
-0.40
Time ... 0.580 0.600 0.620 0.640 0.660 0.680 0.700 0.720
Figure 4.47: Voltage waveforms for subsystem 6a during the neighborhood of sag
4.6.2 Subsystem 6b
Fault = 0.01 Ω
Load = 40Ω+0.096H (0.8 lagging power factor)
Sag created at, t = 5.102 – 5.189 s
Sub system 6b : During sag (@ t=5.102-5.189s)
Supply voltage Load voltage Vinjected
0.40
0.30
0.20
0.10
Voltage (kV)
0.00
-0.10
-0.20
-0.30
-0.40
Time ... 0.600 0.620 0.640 0.660 0.680 0.700 0.720
Figure 4.48: Voltage waveforms for subsystem 6b during the neighborhood of sag
84
Chapter 4
4.6.3 Subsystem 6c
Fault = 0.03183mH
Load = 50Ω
Sag created at, t = 5.102 – 5.189 s
Sub system 6c : During sag (@ t=5.102-5.189s)
Supply voltage Load voltage Vinjected
0.40
0.30
0.20
0.10
Voltage (kV)
0.00
-0.10
-0.20
-0.30
-0.40
Time ... 0.600 0.620 0.640 0.660 0.680 0.700 0.720
Figure 4.49: Voltage waveforms for subsystem 6c during the neighborhood of sag
4.6.4 Subsystem 6d
Fault = 0.03183mH
Load = 40Ω+0.096H (0.8 lagging power factor)
Sag created at, t = 5.102 – 5.189 s
Sub system 6d : During sag (@ t=5.102-5.189s)
Supply voltage Load voltage Vinjected
0.40
0.30
0.20
0.10
Voltage (kV)
0.00
-0.10
-0.20
-0.30
-0.40
Time ... 0.560 0.580 0.600 0.620 0.640 0.660 0.680 0.700
Figure 4.50: Voltage waveforms for subsystem 6d during the neighborhood of sag
85
Chapter 4
4.7 System 7
System 7 was simulated assuming the supply voltage contains harmonic
components. The magnitudes of respective harmonics were obtained using a digital
power analyzer connected to the normal laboratory supply. The harmonics and its
magnitudes are tabulated and described in section 3.4.3.
4.7.1 Subsystem 7a
Fault = 0.01 Ω
Load = 100Ω
Supply voltage = 240V rms (contain harmonics)
Sag created at, t = 5.102 – 5.189 s
0.10
0.00
-0.10
-0.20
-0.30
Figure 4.51: Voltage waveforms for subsystem 7a during the neighborhood of sag
4.7.2 Subsystem 7b
Fault = 0.01 Ω
Load = 80Ω+0.191H (0.8 lagging power factor)
Supply voltage = 240V rms (contain harmonics)
86
Chapter 4
0.10
0.00
-0.10
-0.20
-0.30
-0.40
Time ... 0.580 0.600 0.620 0.640 0.660 0.680 0.700 0.720
Figure 4.52: Voltage waveforms for subsystem 7b during the neighborhood of sag
4.7.3 Subsystem 7c
Fault = 0.03183mH
Load = 100Ω
Supply voltage = 240V rms (contain harmonics)
Sag created at, t = 5.102 – 5.189 s
0.10
0.00
-0.10
-0.20
-0.30
Time ... 0.580 0.600 0.620 0.640 0.660 0.680 0.700 0.720
Figure 4.53: Voltage waveforms for subsystem 7c during the neighborhood of sag
87
Chapter 4
4.7.4 Subsystem 7d
Fault = 0.03183mH
Load = 80Ω+0.191H (0.8 lagging power factor)
Supply voltage = 240V rms (contain harmonics)
Sag created at, t = 5.102 – 5.189 s
Sub system 7d : During sag (@ t=5.102-5.189s)
Supply voltage Load voltage Vinjected
0.40
0.30
0.20
0.10
Voltage (kV)
0.00
-0.10
-0.20
-0.30
-0.40
Time ... 0.580 0.600 0.620 0.640 0.660 0.680 0.700 0.720
It should be noted that all the above simulations were carried out by applying
the voltage sag exactly at the time duration specified in Table 4.1. Due to the
technical limitations in the EMTDC/PSCAD Simulation software the simulations
were carried out in time steps of 1.5sec. After the first 1.5sec the final values of the
simulation will be stored in the memory as a snapshot. For the second 1.5sec time
interval the simulation starts from the saved snapshot file, but the software was not
upgraded to count the time from 1.5sec onwards. Instead it counts from the 0 sec
onwards.
88
Chapter 4
The system 5 is simulated by reducing the fault by 50%, while keeping the
load unchanged. Whereas in system 6 the load is halved, without changing the fault .
When analyzing all the systems considered above it can be identified that there
is an injected voltage of sinusoidal form of peak value 11V, during the synchronizing
stage. And this will be added to the load voltage. Theoretically there shouldn’t be any
voltage injected to the system during synchronization until the comparator block
(described in section 3.3.4) is activated. Until the control voltage is zero, voltage
injected will also be zero.
This injected voltage is the drop across the impedance of the power circuit
components, basically the filter. This injected voltage (≈3% of the supply) is
neglected assuming this drop is tolerable by the load. Further according to IEEE
definitions (for voltage sag given in 2.1.1) this is considered to be a normal condition.
Further at the developed stage of this DVR, this voltage drop can be eliminated by
adding an additional circuit which will be explained in chapter 5.
89
Chapter 4
The DVR now is in the engaged state with the system. After the
synchronization, the injected voltage is increased compared with the case before the
synchronization. Theoretically there cannot be any injected voltage since the load and
the supply voltage waveforms are now in the synchronized state (both in time and
voltage magnitude). The same reasoning did in the previous section valid for this case
too. But it can be observed that the injected voltage is slightly increased in this case
due to the involvement of more power electronic components than earlier. The
comparator in block 4 is switched on now.
In all the above simulated systems a time period of 4sec. was allowed as the
synchronization time. It can be observed after the synchronization the waveform is
slightly disturbed, even though theoretically it should be a pure sinusoidal shape.
Reason for this is the limitations in the EMTDC/PSCAD software. In the above
simulation, the simulation time and the plot time step was set to 1 μs. If this time step
is reduced the results will be more accurate and more ripple free. However, it was
found that the system overall performance can be checked with these settings. For all
the cases following simulation and plot time settings were used as shown in Figure
4.55.
90
Chapter 4
Figure 4.54 shows the same simulation of subsystem 1a with same run time
and reduced solution time and channel plot step (0.9μs). The synchronization
completed at 1s and the shape of the waveform during the engaged state is slightly
improved than the earlier with a step time of 1s (closer to a sinusoidal waveform than
a rippled one).
Supply voltage Load voltage Vinjected
0.40
0.30
0.20
0.10
Voltage (kV)
0.00
-0.10
-0.20
-0.30
-0.40
Time ... 0.940 0.960 0.980 1.000 1.020 1.040 1.060 1.080
0.00
-0.10
-0.20
-0.30
-0.40
Time ... 0.980 1.000 1.020 1.040 1.060 1.080
91
Chapter 4
When considering the systems 1-4 simulated above the following observations can
be made.
During the sag, the injected voltage increased and compensated the voltage
sag.
The stepped nature of the injected voltage is still prevailing during the sag.
During the first few cycles (<1 cycles) the load voltage waveform contains
some transients, and it has the same shape of the injected voltage during the
sag. Hence it can be identified that the transient nature of the load voltage is
directly due to the abnormalities in the injected voltage during this transient
period.
When the sag prevails for longer time duration, the transient nature disappears
and the load voltage obtained almost the same shape of the reference voltage.
I.e. The level of compensation improved within one cycle.
After the supply restores the voltage to the normal condition, during the first
two cycles the injected voltage has the harmonic nature. But the load voltage
is not much affected from it.
Even though this is beyond the scope of this project, the compensation level of
the DVR under the real supply conditions is also simulated by considering the
harmonics present in the normal supply voltage. It has been observed that during the
voltage sag, the load voltage is compensated for voltage magnitude but shows more
ripple at zero voltage injection from the DVR. This is mainly due to the DVR injects
the voltage to compensate for the harmonics and keeps the load voltage at its
fundamental. However, in this control no special attention was made to compensate
the harmonics injection are phase shifted. And the phase angle can be seen as not
correctly matched. This is mainly due to the DVR internal impedance shows different
impedances at harmonic frequencies.
92
Chapter 5
Conclusion
Voltage sags and surges are a common problem faced by the electricity
consumers. As many industries have already making their product from the row
materials, solution to this electricity problem has been identified as the potential issue
to reduce their production cost. When considering the scenario in Sri Lanka it has
been identified that single phase voltage sags and surges are the most common than
the three phase voltage abnormalities. The commonest solution for the above problem
is moving into a full UPS system, which is a costly alternative.
In the above master thesis project voltage sag compensation using Dynamic
Voltage Restorer was considered. Even though three phase DVR system and its
control techniques are popular among the researchers, very less consideration was
given to single phase DVRs and its control techniques.
This thesis describes a voltage sag compensation technique for a single phase
DVR. The control technique was designed by combining both the in-phase and pre-
sag compensation techniques to minimize the requirement of real power and voltage
ratings of the DVR when the voltage sag prevails for a longer period of time .It uses a
closed loop control system to detect the phase angle and magnitude errors between the
voltages during and before the sag.
93
Chapter 6
In the above work, due to the time limitation hardware implementation was not
carried out. The control circuit can be implemented using electronic components and
power electronic switches can be used to generate DVR injected voltages. Then the
simulation results can be compared with that of the hardware and the effectiveness of the
simulated model can be ensured.
The above simulated work was done without giving much attention to the cost
factor of the components (such as PWM components, injection transformer) involved. By
selecting the ratings of the components with worst case analysis, the cost and the
performance are optimized, better results could be obtained.
94
Chapter 6
It can be seen from the simulation results for the voltage sag 100% compensation was
not achieved. However this was within the acceptable limit in this study, when the
DVR rating is increased then the drop increases and thus affects the load voltage. The
reason for this is there is no continuous monitoring and feedback is carried out at the
load voltage. This problem can be eliminated by introducing another separate feed
back control loop for checking the load voltage magnitude compensation to improve
the compensation.
6.2 Limitations
In this thesis work, it has been identified that the simulation results heavily
dependent on the time step considered in the simulation software. By reducing the
time step beyond 1μs (for a run time of 1.5s) the oscillatory and the stepped nature of
the output waveform can be minimized. Due to the limitations in the PSCAD
simulation software and also the limitations in the processing speed of the computer
the time step could not be reduced as desired.
95
References
[1] Il-Yop Chung, Dong-Jun Won, Sang-Young Park, Seung-Il Moon, Jong-Keun
Park, “The DC link energy control method in dynamic voltage restorer
system”, ELSEVIER Electrical Power and Energy Systems (25), 2003,
pg.525-531.
[2] Dong-Myung Lee, Thomas G. Habetler, Ronald G. Harley, Joe Rostron, Tom
Keister, “A voltage sag supporter utilizing a PWM switched autotransformer”,
IEEE Power Electronics Specialists Conference,2004 Aachen, Germany,
pg.4244 – 4250.
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dynamic voltage restorer”, IEEE transactions on Industry applications, Vol.40,
No.1 Jan/Feb. 2004, pg.203- 212.
Formatted: Swedish
[5] Alexander Domijan, Alejandro Montenegro, Albert J. F. Keri, Kenneth E. Mattern, (Sweden)
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[7] Narain G. Hingorani, “Introducing custom power” IEEE spectrum, June 1995
pg. 41-48.
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[15] P.T.Nguyen, Tapan K.Saha, “Dynamic voltage restorer against balanced and
unbalanced voltage sags: Modelling and simulation”, IEEE transactions on
Power Delivery, 2004, pg.1-6.
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industries” IEEE Transactions on Industry applications, Vol.29, No.4, July
1993, pg 696-699.
[19] John Godsk Nielsen, Frede Blaabjerg, Ned Mohan, ”Control Strategies for
Dynamic Voltage Restorer compensating voltage sags with phase jump”,
IEEE transactions on Power Electronics, 2001, pg.1267-1273.
[20] Hongfa Ding, Shu Shuangyan, Duan Xianzhong, Gao Jun, “A novel dynamic
voltage restorer and its unbalanced control strategy based on space vector
PWM”, ELSEVIER Electrical Power and Energy Systems (24), 2002, pg.693-
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[22] John Godsk Nielsen, Michael Newman, Hans Nielsen, Frede Blaabjerg,
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[30] D.Mahinda Vilathgamuwa, A.A.D.Ranjith Perera, ”Voltage sag compensation
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100
List of Publications
101
COMPENSATION TECHNIQUES OF THE DYNAMIC VOLTAGE RESTORER
FOR SINGLE PHASE VOLTAGE SAG WITH IN-PHASE COMPENSATION
Power quality associated problems such as voltage sag, surge (swell), flicker,
imbalance, interruptions and harmonics become a major concern. These power quality
problems affect the performance of the microprocessor based loads as well as the electric
devices that are sensitive to load variations. Among those power quality problems the
most frequent is the voltage sags & swells. Dynamic Voltage Restorer (DVR) is the best
device to compensate for voltage sags/swells in the distribution line. It is a series
connected custom power device, which has been proved as a cost effective device.
The function of the DVR is to inject the difference between the pre-sag & the sag
voltage. The voltage sag can be identified as a change in voltage magnitude and the phase
angle during a small period of time (0.5 – 30 operating cycles). Hence the DVR should
compensate both for the voltage magnitude & the phase angle shift. Three DVR control
techniques are available such as pre-sag compensation, in-phase compensation & energy
optimization technique.
This paper presents a smooth control technique which combined presage and in
phase compensation. Figure 1 shows the block diagram of the control technique. Here the
reference voltage is produced based on the phase angle of the measured voltage. This
phase angle was tracked by feedback action. This control technique has simulated in
using EMTDC/PSCAD and its result is shown in Figure 2. The result showed that an
excellent performance with smooth compensation of the DVR without any phase jump.
-0.10
-0.20
-0.30
-0.40
1.120 1.140 1.160 1.180 1.200 1.220 1.240 1.260 1.280
Fig. 2 Simulation Results
102
Proceedings of the International Conference on Information and Automation, December 15-17, 2006, Colombo, Sri Lanka.
103
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Proceedings of the International Conference on Information and Automation, December 15-17, 2006, Colombo, Sri Lanka.
c) Energy optimization technique: This technique Figure 7: Simplified control circuit of the DVR
compensates with minimized energy requirement. In order
to minimize the use of real power the voltages are injected By analyzing the above circuit Equation 1 can be obtained.
at 90o phase angle to the supply current. Therefore the DVR
R( s)
supplies only the reactive E ( s) = where G ( s ) = G p ( s ) ⋅ G c ( s ) …. (1)
power. However, it is true 1 + G(s)
that the voltage injected Gp(s) and Gc(s) are the plant and the open loop controller
from DVR will be higher transfer functions respectively.
than that of in-phase
compensation strategy. Calculation of Plant transfer function - Gp(s)
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A n g le E rro r
sT Aref
A n g le E rro r in p u t
the input sinusoidal reference. According to this result, a PI output
F Clear
A n g le E rro r filte re d
Ctrl I
voltage
Ameas triggering pulse
Figures 10 and 11 illustrate the simulation block diagram
and results of determining the phase angle of the supply Figure 12: Simulation draft for phase angle determination
voltage. of reference voltage
1 The results of the above simulation (Figure 12) are shown in
314.1593
sT Ameas
Figures 13 and 14.
Clear
Main : Graphs
Ameas Aref Angle Error triggering p...
Zero 7.0
Detector 6.0
5.0
Vs ZCD
4.0
3.0
Figure 10: Simulation draft for phase angle determination 2.0
of the supply voltage 1.0
0.0
-1.0
Main : Graphs
Vs ZCD Ameas*0.1
Figure 13: Simulation results of figure 9 (at the beginning
1.00
of the simulation)
0.80
0.60 Main : Graphs
0.40 Ameas Aref Angle Er... triggerin...
7.0
0.20
6.0
0.00 5.0
-0.20 4.0
-0.40 3.0
0.230 0.240 0.250 0.260 0.270 0.280 0.290 2.0
1.0
Figure 11: Simulation results of figure 7 0.0
-1.0
The supply voltage Vs is passed through a zero crossing
Figure 14: Simulation results of figure 9 (t sec. after the
detector and a limiter respectively to detect the positive
simulation)
gradient zero crossing points of the supply waveform. This
ZCD signal is used to clear the resettable integrator, to
It is clear from the Figures 13 and 14 that, at the
which the input signal is a constant of 314.1593 (= 2.π.f).
beginning of the simulation there is a phase shift between
Since the integrator is resetted during each cycle of the
the supplied voltage and the internally generated reference
supply waveform, the phase angle of the supply voltage can
voltage. After few cycle, the control shifts the phase angle
be identified.
of the reference voltage to track and finally synchronized
with the phase angle of the supply voltage.
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BRK
Block 3: Calculation of the reference voltage
0.01
Vs
R=0
Sin *
0.01
Aref Vref I D I D
Pbot Ptop
0.34 0.002
47.0
#1 #2 VInj
10000.0
Figure 15: Calculation of the reference voltage waveform Ea
Iload
from the reference phase angle VL
100.0
R=0
Phase angle of the reference voltage is calculated from the I I
D D
block 2 described in Figure 12. The result is converted into
Ptop Pbot
a sinusoidal waveform with a peak value of 340V (=240V
rms) as shown in Figure 15.
Figure 17: Power circuit of the DVR
Block 4: Calculation of the control voltage
Voltage sag is created by closing the contacts of a circuit
A breaker, which is connected parallel to the source. The
Vref D + - Ctrl = 1
series resistor is connected to the circuit breaker, the
Vs
F B
Vcontrol resistance of which can be varied depending on the severity
Ctrl
of the voltage sag required.
0.0
TIME
VII. CONVERTER CONTROL
Figure 16: Simulation draft for the calculation of control
voltage
Tri
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occurred across the internal impedance of the DVR. This [2] Chi-Seng Lam, Man-Chung Wong, Ying-Duo Han, “Stability study
on Dynamic Voltage Restorer (DVR)”, Proceedings of First
can be eliminated by using another PI controller to regulate
International Conference on Power Electronics Systems and
the magnitude error or using pre calculation method of Applications 2004, Nov. 2004, pp 66 – 71.
voltage drops. [3] Agileswari K. Ramasamy; Rengan Krishnan Iyer; Dr. Vigna K
Ramachandramurthy, Dr.R.N.Mukerjee, “Dynamic Voltage Restorer
However, these methods make the control more for voltage sag compensation”, Conference on Power Electronics and
Drive Systems, Vol.2, Nov. 2005, pp 1289 – 1294.
complicated. And also from the simulation results, the load [4] Changjiang Zhan, Vigna Kumaran Ramachandaramurthy,
voltage during the voltage sag is kept above 90% of its Atputharajah Arulampalam, Chris Fitzer, Stylianos Kromlidis, Mike
rating. According to the IEEE standards listed in Table 1, Barnes and Nicholas Jenkins, “Dynamic Voltage Restorer based on
this drop is falling under accepted operating condition. Voltage-Space-Vector PWM control” IEEE Transactions on Industry
Applications, Vol.37, No.6, Nov./Dec. 2001, pp 1855 -1863.
[5] V.K.Ramachandaramurthy, C.Fitzer, A.Arulampalam, C.Zhan,
Therefore the proposed DVR control technique is the M.Barnes, N.Jenkins, “Control of a battery supported dynamic
efficient simplified method to compensate single phase voltage restorer” ,IEE Proceedings on Generation, Transmission and
voltage sags. Distribution, Vol.149, No.5, September 2002, pp 533 – 542.
[6] Neil H. Woodley, Ashok Sundaram, “Field experience with the new
Main : Graphs
platform-mounted DVR” IEEE Transactions on Power quality
0.40
Supply voltage Vref Vcontrol Load voltage improvement methods, 2000, pp. 1323–1328.
0.30
[7] N.H.Woodley, “Field experience with Dynamic Voltage Restorer
0.20
(DVR MV) Systems”, Power Engineering Society Winter Meeting
2000, IEEE, Vol.4, Jan. 2000, pp 2864 -2871.
0.10
[8] Changjiang Zhan, Atputharajah Arulampalam, Nicholas Jenkins,
“Four-wire Dynamic Voltage Restorer based on a three-dimensional
0.00
-0.10
voltage Space Vector PWM algorithm”, IEEE Transactions on Power
-0.20
Electronics, Vol.18, No.4, July 2003, pp 1093 -1102.
-0.30 [9] V.K.Ramachandaramurthy, C.Fitzer, A.Arulampalam, C.Zhan,
-0.40 M.Barnes, N.Jenkins, “Control of a battery supported dynamic
0.40
Supply voltage Vcontrol Vinjected Load voltage Load current
voltage restorer” ,IEE Proceedings on Gneeration, Transmission and
0.30 Distribution, Vol.149, No.5, September 2002, pp 533 – 542.
0.20
0.10
0.00
-0.10
-0.20
-0.30
-0.40
0.400 0.450 0.500 0.550 0.600 0.650 0.700 0.750
IX. CONCLUSION
REFERENCES
108