Subject: VLSI Technology & Design Course: M.

TECH, I-SEM (ES & VLSI, ECE)

1. Write about architecture testing ? 2. Write about power optimization methods of sequential systems ? 3. Draw the layouts for CMOS inverter and NAND and NOR gates? 4. Write about design validation and testing of sequential systems ? 5. Write about architecture design of SOCs ? 6. Explain about floor planning methods and off - chip connections?
Subject : Advanced Data Communication

Course : M.TECH, I-SEM (ECE) 1. Explain (a) FDMA (Frequency division multiple access) (b) CDMA (Code division multiple access) 2. Explain (a) Error detection code Cyclic redundancy check (b) Error correction code - Hamming code 3. Explain (a) Binary Synchronous communication (b) HDLC, Link access protocol 4. Explain (a) Circuit switching (b) Packet switching 5. Explain (a) ALOHA & Token Passing. (b) CSMA/CA (Carrier sense multiple access with collision avoidance) 6. Explain the following Data link protocols (a) Sliding window protocol (b) Stop and wait protocol
Subject : CPLD & FPGA Technologies

Course : M.TECH, I-SEM (ES & VLSI) 1. Explain extended petrinetes for parallel controller? 2. Explain design flow using FPGAs? 3. Explain one hot state machine with state diagram? 4. Explain basic concepts and properties of petrinetes for state machines? 5. Explain the structure of alternative state machine and state diagram for traffic light controller? 6. Explain Xilinx implementation of (a) Parallel full adder. (b) Max bus controller.

Subject : Algorithmic VLSI Design & Automation Course : M.TECH, I-SEM (ES & VLSI) 1. Write notes on (a) MCM technologies (b) Multiple Stage Routing

2. Explain about Iterative Data Flow. 3. Give the physical Design cycle for FPGAs and explain about the same.
4.(a) Discuss the basic issues and terminology employed in logic synthesis inVLSI design. (b) Explain about ROBDD principles.

5. Explain about assignment and scheduling relevant to High-level

synthesis. 6.Explain about partitioning for segmented models.
Subject: Advanced Digital Signal Processing Course: M.TECH, I-SEM (ES & VLSI, ECE)

Logic

1. Write about finite word-length effect in IIR digital filters ? 2. Write about analysis of finite word-length effects in fixed point dsp systems? 3. Write about levinson durbin & Schur algorithms ? 4. Write about properties of linear Prediction filters ? 5. Write about finite word-length effects in FFT algorithms ? 6. Briefly discuss about forward and backward linear Prediction ?
Subject: Microcontrollers for Embedded Systems Design Course: M.TECH, I-SEM (ES & VLSI, ECE)

1. ARM processor architecture ? 2. Context switching and interrupt latency ? 3. Device drivers for internal programmable timing divices ? 4. Explain briefly about device drivers ? 5. Interrupt handling mechanism ? 6. Explain about Ethernet protocol and SDMA?

Subject: ERTOS Course: M.TECH, I-SEM (ECE) 1. Explain interrupt routine in RTOS? 2. Explain COS-II? 3. Explain the need of testing & debugging RTOS? 4. Explain the study of an embedded system for smart card? 5. In VX works of countin watch-dogs. Explain? 6. Explain management task state transition diagram and I/O system?

Subject : Digital system Design Course: M.TECH, I-SEM (ES & VLSI, ECE)

1. Describe about
(a) The elimination of Redundant states (b) Equivalent states

2. Explain about Test generation Algorithms for PLAs. 3. Write a short note on race free assignments. 4. (a)
(b) Explain about the capabilities and limitations of FSM. Explain about Hazards.

5. Explain about the design of fault detection experiment. 6. Explain about machine identification. M.Tech TIME TABLE FOR II MID
BRANCH ECE ECE ECE DATE 12-04-2012 13-04-2012 14-04-2012 SUBJECT DSD,ADSP MCESD,ADC VLSI&Design,ERTOS

BRANCH ES & VLSI ES &VLSI ES & VLSI

DATE 12-04-2012 13-04-2012 14-04-2012

SUBJECT DSD,MCESD CPLD & FPGA, VLSI&Design AVDA,ADSP

BRANCH:- ECE,ES&VLSI Seminars

14-04-2012