DigitalDesignAssignment(20 marks)

AnaloganddigitalVLSIdesign

Objective:Trytokeepspecificationsassimpleaspossibleandjustmeatthefunctionality.

Tomakeyoulearnwritingsynthesizableverilog/VHDLcode Youshouldbeabletovaryyoursynthesisasperspeed/power PracticalunderstandingofASIC UsingEDAtoolsefficientlyinsystemdesign

GeneralInstructions: Youaregiven10digitalsubsystemsthataremostlyusedinprocessordesign.Youcan chooseanyoneofthemandfollowthedesignmethodologygivenbelow. TherehastobeTWOstudentspergroupatthemaximum. Only5groups(atthemaximum)canregisterforanyparticularcircuitoutof6projects listed.Projectswouldbeallottedbasedonfirstcomefirstregisterbasis. Pleasechooseyourtopicby30march.2012. YouneedtoworkonSOCencounter,modelsim,RCcompiler

Extrareadingisrequiredforunderstandingofthesecircuits.

Designinstructions:

Understandthefunction.Designthearchitecture(importantpart)yourself .Refertorecentpapers.Chooseyourownspecs.Astheassignmentwillbebasedonrelativegrading,the morechallengingyoumakefromothersthemoremarksyouwillbeawarded.Challengingrefersthathow closeareyourspecstothedesiredone.

Characterizeyourdesignbytabulatingobtainedvaluesofall(maximum)parameters(specs)whichyou studiedintheclass.

Ifyouarenotabletomeetyourspecs,youcangoaheadwithsystemdesign,butyouneedtoexplainwhyit hashappenedatthetimeofdemonstration.

Ifrequired,youcanchangespecifications.Howeveryouneedtogiveaclearjustification ValidateyourdesignforallprocesscornersandtemperatureVariation.Keepthepowerdissipationassmallas possible.

YoushouldsubmitasoftcopyofDETAILEDreportofyourassignmenttoIC. Yourdesignshouldmeetspecificationatallprocesscornerswithtemperaturevaryingfrom40oto125oC.

Whiledesigninginrtlcompiler,constraintsshouldbeseton Clock(max.Possible), Clockskew(min.Possible), Max.Fanout(4), Inputoutputpindelay(worstcase), Operatingconditionsworstcase(temp,processandvoltage)

CommonSpecifications: Technologynode:umc180nmCMOS VDD=3V

TOPIC1:Programmable8tapFIRfilter
Afiniteimpulseresponse(FIR)filterisafilterstructurethatcanbeusedtoimplementalmostanysortoffrequency responsedigitally.AnFIRfilterisusuallyimplementedbyusingaseriesofdelays,multipliers,andadderstocreate thefilter'soutput.

USEFULREFERENCE: Usefulreference:HighperformanceFIRfilterdesign,IEEEtransactiononVLSIsystems,vol11no.2april2003 TOPIC2:4KB4WaysSetAssociativeCacheMemory

The implementation of a 4way setassociative cache is shown in the following diagram. (An nway set associativecachecanbeimplementedinasimilarmanner.)Theindexpartoftheinputaddressisusedtofindthe properrowinthedatamemoryarrayandthetagmemoryarray.Inthiscase,however,eachrow(set)corresponds tofourcachelines(fourways).Arowinthedatamemoryholdsfourcachelines(for32bytescachelines,128 bytes),andarowinthetagmemoryarraycontainsfourtagsandstatusbitsforthosetags(2bitspercacheline). Thetagmemoryandthedatamemoryareaccessedinparallel,buttheoutputdatadriverisenabledonlyifthere isacachehit.

Applytechniquesthatcanbeusedtohelpachievetheincreasinglystringentdesigntargetsandconstraintsofmodern processors.Inparticular,considertechniquesthatenablethecachetobeaccessedquicklyandstillachieveagoodhit ratiowithnearlynilleakagepower.Alsoconsiderissuessuchasareacostandbandwidthrequirements.

TOPIC3:DualLoopDelayLockedLoop
Insynchronoussystems,theintegratedcircuitsinthesystemaresynchronizedtoacommonreferenceclock.This synchronisationoftencannotbeachievedbydistributingasinglereferenceclocktoeachoftheintegratedcircuitsfor thefollowingreasons,amongothers.Whenanintegratedcircuitreceivesareferenceclock,thecircuitoftenmust conditionthereferenceclockbeforethecircuitcanusetheclock.E.g.thecircuitmaybuffertheincomingreference clockormayconverttheincomingclockfromonevoltageleveltoanother.Theprocessingintroducesitsowndelay, withtheresultthattheprocessedreferenceclock,whichwillbereferredtoasalocalclock,oftenwillnolongerbe adequatelysynchronisedwiththeincomingreferencedclock.Thetrendtowardsthefastersystemclockspeedsfurther aggravatesthisproblemsincefasterclockspeedsreducetheamountofdelay,orclockskew,whichcanbetolerated. Toremedythisproblem,anadditionalcircuitistypicallyusedtosynchronisethelocalclocktothereferenceclock. TwocommoncircuitswhichareusedforthispurposearethePLLandtheDLL. USEFULREFERENCE:

Uploadedonsite

TOPIC4:Jitterbounded,fastlock,Alldigitalphaselockedloop
USEFULREFERENCE:

Thedesignofanalldigitalphaselockedloop Melester,M.T.; VehicularTechnologyConference,1988IEEE38th 1517June1988Page(s):471477 DigitalObjectIdentifier10.1109/VETEC.1988.195403 Analldigitalphaselockedloopforhighspeedclockgeneration ChingCheChung;ChenYiLee; CircuitsandSystems,2002.ISCAS2002.IEEEInternationalSymposiumon Volume3,2629May2002Page(s):679682 DigitalObjectIdentifier10.1109/ISCAS.2002.1010315 AnAllDigitalPhaseLockedLoopwithHighResolutionforSoCApplications DuoSheng;ChingCheChung;ChenYiLee; VLSIDesign,AutomationandTest,2006InternationalSymposiumon April2006Page(s):14 DigitalObjectIdentifier10.1109/VDAT.2006.258161

TOPIC5:PEREIRAS16bitBARRELSHIFTER
Ingeneral,abarrelshiftercanimplementarithmeticshifting,logicalshiftingandrotationfunctions.Forinstance,an NbitbarrelshiftercanshiftleftorrightbyN1bits.Thefunctionalityoftheshiftershouldincludelogicalshifting, arithmeticshifting,androtation.DesignoftheBarrelshiftershouldallowforanincreaseinthenumberofinputbits withouthavingtomodifytheexistingdesign. UsefulReferences: 1.) A16BitBarrelShifterImplementedinDataDrivenDynamicLogic(D3L)RaminRafati,SiedMehdi Fakhraie,Member,IEEE,andKennethCarlessSmith,LifeFellow,IEEE. 2.) ImplementingBarrelShiftersUsingMultipliersAuthor:PaulGigliotti,XAPP195(v1.1)August17,2004

TOPIC6:DesignaHIGHSPEEDSIXOPERANDS32BITSCARRYSAVEADDER
Themostimportantapplicationofacarrysaveadderistocalculatethepartialproductsinintegermultiplication.This allowsforarchitectures,whereatreeofcarrysaveadders(asocalledWallacetree)isusedtocalculatethepartial productsveryfast.One'normal'adderisthenusedtoaddthelastsetofcarrybitstothelastpartialproductstogive thefinalmultiplicationresult.Usually,averyfastcarrylookaheadorcarryselectadderisusedforthislaststage,in ordertoobtaintheoptimalperformance. UsefulReferences: 1. CarrySaveAddition,Prof.Loh,CS3220ProcessorDesign,February2,2005

TOPIC7:Designofalowpowerhighspeed32x32bitmultiplier
YoushouldtrytoreduceswitchingactivityandachievelowpowerdissipationthroughtheSignMagnitude(SM) notationforthemultiplicandandthroughanoveldesignoftheRedundantBinary(RB)adderandBoothdecoder.The highspeedoperationmaybeachievedthroughtheCarryPropagationFree(CPF}accumulationofthePartial Products(PP)byusingtheRBnotation. USEFULREFERENCE:

[l]N.Takagi,etal,HighSpeedVLSIMultiplicationAlgorithmwithaRedundantBinaryAdditionTree,IEEE Trans.onComputers,Vol.C34,No.9,pp.789796,September1985. [2]H.Makino,etal,A8.8ns54x54bitMultiplierUsingNewRedundantBinaryArchitecture,Proceedingsof1993 InternationalConferenceonComputerDesign,Cambridge,MA,USA,pp.202205,October36,1993.\

Topic8:DesignaLowPowerLogarithmicConverter
USEFULREFERENCE: 1.) CMOSVLSIImplementationofaLowPowerLogarithmicConverterKhalidH.Abed,SeniorMember, IEEE,andRaymondE.Siferd,Member,IEEE

Topic9:Designa32bitx32Radix4SRTdivider
UsefulreferenceComputerArithmeticalgorithmsandhardwaredesign.By:BehroozParhami

Topic10:DesignofafullypipelinedCORDICPROCESSORforOFDMbasedWLAN UsefulreferenceEuropeanJournalofScientificResearch,ISSN1450216XVol.27No.4(2009),pp. 588596 Topic11:CMOSImplementationofa32bitbinarytobinarylogarithmconverter UsefulreferenceIEEETRANSACTIONSONCOMPUTERS,VOL.52,NO.11,NOVEMBER 2003 Topic12:DesignofAutocorrelationfunctionforOFDMBasedWLAN (chooseanyreference)

Topic13:DesignofFloatingPointMultipilerusingIEEE754format. (HennessyPatterson:ComputerArchitecture) Topic14:DesignofHighspeedDDRSDRAMcontroller.(only2batches) (Chooseanyreference)

Topic15:DesigningofProgrammablePeripheralInterface(PPI)usingVerilogHDL (MicroprocessorReferencebook) Topic16:DesigningofProgrammableTimerInterface(PTI)usingVerilogHDL (MicroprocessorReferencebook)

Topic17:ALowPowerLowAreaMultiplierBasedonShiftandAddArchitecture (ChooseAnyreference) Topic18:FastHardwareApproachforApproximate,EfficientLogarithmandAntilogarithm Computations (Chooseanyreference)

Topic19:VLSIDesignandImplementationofDMAusingVHDL/VerilogHDL (Chooseanyrefernce) Topic20: Design an 16-bit integrated ALU chip to perform basic tasks like AND, OR, ADD, SUB, MUL, DIV.Your ALU should accept two 16-bit input values and a 3-bit opcode. (Chooseanyreference)