Cordic Demo

Last updated: 19-Nov-2003 CORDIC, which stands for Coordinate Rotation Digital Computer, is an algorithm developed by Volder in the fifties which allows you to calculate trigonometric functions using simple shift and add operations. This is an advantage for hardware implementations were multipliers are normally resource demanding (unless you use e.g. a Virtex-II :-). The algorithm can be adapted to also compute fix/floating point multiply, divide, log, exponent and square root. This webpage describes a simple serial fix point CORDIC VHDL implementation using Mentor Graphics HDL designer (not required though). The module computes fix point sin and cos values from a given angle. The resolution can be changed using generics. The testbench compares the output with pre-calculated values from a textfile. There is so much information on the web about CORDIC that I won't repeat the algorithm here. Have a look at some of the following links:

CORDIC FAQ from DSPguru Ray Andraka Consulting group (read his excellent paper here) MAPLD paper (PDF, 345KB) CORDIC VHDL/Verilog/C generator from Opencores Adelante's A|RT generated VHDL/Verilog CORDIC modules Another Free CORDIC implementation from Free-IP Cores A commercial CORDIC core from Digital Core Design Free implementation from ASICS (Also available from opencores.org) Floating Point CORDIC Paper from PARL NCO Implementation paper using CORDIC CORDIC Paper by Evatronix

Source files

Download the VHDL/C sources files from here (117KB, zipped)

Tools used

Modelsim 5.7c SE, note PE and OEM versions can also be used. HDL_Designer 2002.1b, this is optional, you can run the demo using just Modelsim C-Compiler if you want to re-compile the testvector generator. Binaries are supplied for Windows (DOS box/Cygwin)

Note that this is a good design example were graphics gives a better design overview than text would do. Click on the HDL Designer image below to show how the individual modules (shifters/adders/LUT/registers) are connected

Figure: Serial Cordic Module in HDL Designer (click to see high resolution version)

Running the demo using HDL Designer

Download the source files and unzip to a suitable directory Invoke HDL Designer and add a library mapping for the design, map the Modelsim work library to work_mti. Select the cordic_tb module and click on the Modelsim (or other 3rd party simulator) button for simulation When the simulation dialog box pops up enter tb.do in the do box (Initialization command -do) For synthesis, select the Cordic module and click on the Spectrum/Precision (or other 3rd party synthesiser) button Example: Post P&R result targeting a small Virtex V50-4 (24 bits Cordic) # Using target part "v50bg256-4" # Device utilization summary: # Number of External GCLKIOBs 1 4 25% # Number of External IOBs 75 180 41% # Number of SLICEs 210 768 27% # Number of GCLKs 1 4 25% # Design statistics: # Minimum period: 22.348ns (Maximum frequency: 44.747MHz)

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Running the demo using Modelsim

Invoke Modelsim and navigate to the work_mti directory source compile.scr followed by the tb.scr file Example: Modelsim simulation result # Comparing from bit 23 downto 8 # Angle=5CB63E Sin=3F85E1 Expected=3F85E0 Cos=07CCB4 Expected=07CCB5 PASS # Angle=5DD432 Sin=3FA63F Expected=3FA63F Cos=06B097 Expected=06B098 PASS # Angle=5EF227 Sin=3FC1A8 Expected=3FC1A7 Cos=0593F2 Expected=0593F5 PASS # Angle=60101B Sin=3FD815 Expected=3FD816 Cos=0476E0 Expected=0476E3 PASS # Angle=612E10 Sin=3FE98D Expected=3FE98B Cos=035976 Expected=035978 PASS # Angle=624C04 Sin=3FF603 Expected=3FF604 Cos=023BCB Expected=023BCB PASS # Angle=6369F8 Sin=3FFD7E Expected=3FFD81 Cos=011DF3 Expected=011DF0 PASS # ** Failure: *** End of Test *** # Time: 414528 ns Iteration: 3 Process: /cordic_tb/i1/line__69

For synthesis navigate to the work_ps directory where you will find add_files.tcl. Source/modify this file from/for your own synthesis script.

Changing the bit resolution

Modify the WIDTH generic in the testbench, maximum is 32 bits (default is 24 bits) Change the COMPARE_END generic if required. The COMPARE_END generic is used in the testbench to compare the generated value against a pre-calculated value located in the testvec.txt file. Since the accuracy is, amongst others, depended on the angle you can limit the number of bits in the comparison.

Regenerate the vector file using genvect.bat located in the C-source directory Example: gen_testvector ..\src\cordic_tester\behavioral.vhd.info\testvec.txt 32 The testvec.txt file is located in the so-called HDL Designer side data directory. You can change the filename/directory by changing the FILENAME generic in the testbench file.