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ME3241/ ME3241E Mi cr opr ocessor and Appl i cat i ons

Part 1: Digit al Elect ronics



















BY
A/PROF HONG GEOK SOON
Control & Mechatronics Group
Mechanical Engineering Department
NATIONAL UNIVERSITY OF SINGAPORE
DECEMBER 2011
ME3241/ME3241E Microprocessor and Applications
Page: ii 2011, ME, NUS

ME3241/ME3241E MICROPROCESSOR APPLICATIONS
By: A/P GS Hong (Digital Electronics) Dr. Xu Huan (MicroP)
Room: EA-05-24 E1-05-17
Phone: 6516 2272 65161604
E-mail: mpehgs@nus.edu.sg mpecck@nus.edu.sg


ME3241 ME3241E
Start Date: 09 Jan 2012 13 Jan 2012

Time: Monday 10:00-012:00
Friday 9:00-11:00 Friday 18:0021:30

Venue: E1-06-04 (Monday) LT7A




Examination Date: 24 April 2012 (pm)


Reference books:
1. RL Tokheim,
"Digital electronics: Principles and applications",
7th edition, 2008, McGrawHill.
2. RJ Tocci,
"Digital systems: Principles and applications",
6th edition, 1995, Prentice-Hall, Inc.
3. S Brown and Z Vranesic,
"Fundamentals of digital logic with Verilog design",
2nd edition, 2008, McGrawHill.
4. LD Jones,
"Principles and applications of digital electronics",
Macmillan, 1986.
5. TF Bogart, Jr.,
"Introduction to digital circuits",
McGraw-Hill International Student Edition, 1992
6. H-W Huang,
"PIC microcontroller: an introduction to software and hardware interfacing",
Clifton Park, NY: Thomson/Delmar Learning, 2005.


2011, ME, NUS Page: iii

Contents
Chapt er 1 Number System and Codes ..................................................................................... 5
1.1 Number Systems .............................................................................................................. 5
1.1.1 Number System Representation .............................................................................. 5
1.2 Conversion between number systems ............................................................................. 7
1.2.1 Binary to Decimal ..................................................................................................... 7
1.2.2 Decimal to Binary ..................................................................................................... 7
1.2.3 Octal to Decimal ....................................................................................................... 9
1.2.4 Decimal to Octal ....................................................................................................... 9
1.2.5 Octal to Binary ........................................................................................................ 10
1.2.6 Binary to Octal ........................................................................................................ 10
1.2.7 Hexadecimal to Decimal ......................................................................................... 11
1.2.8 Decimal to Hexadecimal ......................................................................................... 11
1.2.9 Hexadecimal to Binary ........................................................................................... 11
1.2.10 Binary to Hexadecimal ........................................................................................... 11
1.3 Codes and Coding ......................................................................................................... 12
1.3.1 Binary Coded Decimal Code .................................................................................. 12
1.3.2 Gray Code .............................................................................................................. 13
1.3.3 Alphanumeric Codes - ASCII Code ........................................................................ 16
1.3.4 Error Detection ....................................................................................................... 17
1.3.5 Error Correction ...................................................................................................... 19
1.4 Binary Arithmetic ............................................................................................................ 21
1.4.1 Binary Addition ....................................................................................................... 21
1.4.2 Binary Subtraction .................................................................................................. 21
1.4.3 Binary Multiplication ............................................................................................... 22
1.4.4 Binary Division ....................................................................................................... 22
1.4.5 Representing Signed Numbers .............................................................................. 22
1.5 Numeric Notation Used in Computers ............................................................................ 27
1.5.1 Integer Notation ...................................................................................................... 27
1.5.2 Floating Point Notation ........................................................................................... 27
Chapt er 2 DIGITAL ELECTRONICS ....................................................................................... 31
2.1 Introduction .................................................................................................................... 31
2.2 Boolean algebra ............................................................................................................. 31
2.2.1 Definition ................................................................................................................ 31
2.2.2 Boolean Identities ................................................................................................... 31
2.3 Integrated Circuit Logic .................................................................................................. 32
2.3.1 Digital IC Terminology ............................................................................................ 32
2.3.2 TTL Logic ............................................................................................................... 35
2.4 Logic Gates .................................................................................................................... 39
2.4.1 Some Properties of NAND Gate ............................................................................. 40
2.4.2 Some combinatorial logic examples ....................................................................... 40
2.5 Flip-flops and Latches .................................................................................................... 41
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2.5.1 NAND gate Latch: .................................................................................................. 42
2.5.2 Clocked Flip-Flops: ................................................................................................. 43
2.5.3 Making of Clocked S-C Flip-Flop ............................................................................ 43
2.5.4 Clocked J-K Flip-Flop ............................................................................................. 45
2.5.5 Clocked D Flip-Flop ................................................................................................ 46
2.5.6 D Latch (Transparent Latch) ................................................................................... 47
2.5.7 Timing Consideration for Flip-flop ........................................................................... 47
2.6 Counters and Registers.................................................................................................. 48
2.6.1 Registers ................................................................................................................ 48
2.6.2 Counters ................................................................................................................. 50
2.7 Encoders, Decoders ....................................................................................................... 60
2.7.1 Decoders ................................................................................................................ 60
2.7.2 Encoders ................................................................................................................ 64
2.8 Multiplexers & demultiplexers ......................................................................................... 65
2.8.1 Multiplexers ............................................................................................................ 65
2.8.2 Multiplexer Applications .......................................................................................... 66
2.8.3 Demultiplexers........................................................................................................ 67
2.8.4 Demultiplexer Applications ..................................................................................... 68
Chapt er 3 Microprocessor Architecture ................................................................................... 69
3.1 Making of a microprocessor ........................................................................................... 69
3.1.1 Registers, ROMs, Rams and Buses ..................................................................... 69
3.1.2 Digital Arithmetic Circuits ........................................................................................ 72
3.1.3 A Very Simple microprocessor ............................................................................... 73



2011, ME, NUS Page: 5
Chapt er 1 Number System and Codes
1.1 Number Systems
A number system is a quantifying system ones adopted for counting. The quantity involved can be
the number of people attending this class, the number of elective modules a student has to take,
etc.. The study of number systems is not just limited to computers. We apply numbers every day,
and knowing how numbers work will give us an insight into how a computer manipulates and stores
numbers.
Amount many number system, the commonest is the system known as weighted position
representation. Human start their ways of counting in many different ways and finally evolved to the
current approach of number system representation. For a good appreciation of the historical
number system representation, please refer to
http://www-groups.dcs.st-andrews.ac.uk/~history/Indexes/Number_Theory.html

1.1.1 Number System Representation
Consider the number 6557, we read six thousand five hundred and fifty seven, that is
6 x 1000 + 5 x 100 + 5 x 10 + 7 x 1
The above example demonstrated a common number system we adopted. It is known as
weighted position representation.
Definition:
A number,
r
N
,
in a number system with the base r is represented in the form of

=

= =
n
m i
i
i m n n r
r A A A A A A N
1 0 1
. ( 1.1.1)
where
i = number of places the digit is relative to the radix point
r = radix or the base of the system
{ } 1 , , 1 , 0 e r A
i


This number representation is also known as weighted position number system. The following
subsections show a few common examples of such representation.

1.1.1.1 Decimal System (Base 10)
The decimal system is the number system we (human being) are familiar with. In this case, the
base
r = 10, and
{ } 9 , 8 , 7 , 6 , 5 , 4 , 3 , 2 , 1 , 0 e
i
A

Examples:
825
10
= 8 x 10
2
+ 2 x 10
1
+ 5 x 10
0

368.49
10
= 3 x 10
2
+ 6 x 10
1
+ 8 x 10
0
+ 4 x 10
-1
+ 9 x 10
-2

Decimal system is the current Universal Standard used by human being. For convenience, we
normally just omit the subscript 10 in our notation.

1.1.1.2 Binary System (Base 2)
The binary system is the number system that computer is using. In this case
r = 2, and
{ } 1 , 0 e
i
A .
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In binary system there are only two states (zero and one), these binary states make it easy for
Boolean implementation in the computer.

Example:
The number 1101
2
has the representation
Weightage
3
2
2
2
1
2
0
2
+ + + +
Number 1 1 0 1
It has an equivalent decimal value of
1101
2
= 1 x 2
3
+ 1 x 2
2
+ 0 x 2
1
+ 1 x 2
0

= 13
10
Also
110.01
2
= 1 x 2
2
+ 1 x 2
1
+ 0 x 2
0
+ 0 x 2
-1
+ 1 x 2
-2
= 4 + 2 + 0 + 0 + 0.25
= 6.25
10


1.1.1.3 Octal System (Base 8)
Octal system is a number system that is commonly used by the low level programmer for better
visual recognition of the codes. In this case,
r = 8
{ } 7 , 6 , 5 , 4 , 3 , 2 , 1 , 0 e
i
A

Example:
The number 405.3
8
has the representation of
Weightage
2
8
1
8
0
8
1
8

+ + + +
Number 4 0 5. 3

It has an equivalent decimal value of
405.3
8
= 4 x 8
2
+ 0 x 8
1
+ 5 x 8
0
+ 3 x 8
-1

= 4 x 64 + 0 + 5 x 1 + 3 x 0.125 = 261.375
10
Also
102.21
8
= 1 x 8
2
+ 0 x 8
1
+ 2 x 8
0
+ 2 x 8
-1
+ 1 x 8
-2
= 64 + 0 + 2 + 2 x 0.125 + 0.015625 = 66. 265625
10

1.1.1.4 Hexadecimal System (Base 16)
Like the octal system, hexadecimal system is a number system that is commonly used by the low
level programmer for better visual recognition of the codes. In this case,
r = 16
{ } F E D C B A A
i
, , , , , , 9 , 8 , 7 , 6 , 5 , 4 , 3 , 2 , 1 , 0 e

Noting that, in hexadecimal system, we are running out of symbol to represent the values 10~15.
We use the alphabets A~F to represents these values.

Example:
The number 3B.4
16
has the representation of
Weightage 16
1
16
0
16
-1

+ + +
Number 3 B. 4

Number System and Codes
2011, ME, NUS Page: 7
3B.4
16
= 3 x 16
1
+ 11 x 16
0
+ 4 x 16
-1

= 3 x 16 + 11 x 1 + 4 x 0.0625
= 59.25
10
Also,
102.2
16
= 1 x 16
2
+ 0 x 16
1
+ 2 x 16
0
+ 2 x 16
-1


= 1 x 256 + 0 x 16 + 2 x 1 + 2 x 0.0625
= 258.125
10
1.2 Conversion between number systems
We now see that a numerical value can be represented in many different bases of representation.
When you are given with a number in one base, say, r
a
. What is the equivalent representation in
another base, say, r
b
? A quick solution to this will be the use of the weighted position
representation definition in (1.1.1).
Given a number
a
r
N represented by
m n n r
A A A A A N
a

=
1 0 1
.
.
( 1.2.1 )
Then, this number can be represented in another base of radix value
b
r
N by

=
=
a
a
b
n
m i
i
a i r
r A N ( 1.2.2)
with the arithmetic be computed in base r
b
.
Such formulation implies the requirement of a base that the computer is familiar with. For instance,
the human being is familiar with the decimal system (i.e. r = 10). We can use this to convert a
number of any bases into a decimal system.

1.2.1 Binary to Decimal
We use the weighted sum approach as in (1.2.2) with r
b
= 10.

=
=
2
2
2
10
n
m i
i
i
b N ( 1.2.3 )
Example:
The number 1010.01
2
can be converted to a decimal as
1010.01
2
= 1 x 2
3
+ 0 x 2
2
+ 1 x 2
1
+ 0 x 2
0
+ 0 x 2
-1
+ 1 x 2
-2

= 8 + 0 + 2 + 0 + 0 + 0.25 = 10.25
10

1.2.2 Decimal to Binary
The above examples showed the conversion from binary system to decimal system. How about the
reverse process? To do this, we can also use the same weighted sum approach as in (1.2.3). For
instance, the decimal number 34
10
can be converted to its binary equivalence by

10
34

0 1
10 4 10 3 + =


0
2 2
1
2 2
1010 100 1010 11 + =


2 2 2
100010 110 11110 = + =

However the above method involves binary arithmetic. Such approach is not practical as we are
not familiar with arithmetic with any bases other than 10. There are two other methods to convert a
decimal number to binary number.

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1.2.2.1 Method 1
Express the decimal number as a sum of powers of 2 and then 1s and 0s are written in the
appropriate bit position.
Example:
45.5
10
= 32 + 8 + 4 + 1 + 0.5
= 2
5
+ 0 + 2
3
+ 2
2
+ 0 + 2
0
+ 2
-1
= 101101.1
2
76
10
= 64 + 8 + 4
= 2
6
+ 0 + 0 + 2
3
+ 2
2
+ 0 + 0 = 1001100
2


Note: This method require you to be familiar with the various $2^i$ values.

1.2.2.2 Method 2
Consider a 3-digit based-r integer,
0
0
1
1
2
2
r A r A r A N
r
+ + = . Dividing N
r
by its radix value yields
( )
r
A
r A r A
r
r A r A r A
r
N
r
0 0
1
1
2
0
0
1
1
2
2
+ + =
+ +
=

Or, alternatively, we say
0
0
1
1
2
remainder A r A r A
r
N
r
+ =

Similarly,
1
0
2
0
1
1
2
remainder A r A
r
r A r A
=
+


Hence, we can use successive division technique to convert a decimal number to a base-r
representation.
For the case of fractional number, consider a base-r fractional number with 3 radix
places
3
3
2
2
1
1

+ + = r A r A r A N
r
. Multiplying N
r
by its radix r yields
( )
2
3
1
2
0
1
3
3
2
2
1
1

+ + =
+ + =
r A r A r A
r r A r A r A r N
r

Noting that, the first radix place of the fractional number becomes the integer part in the result. That
is, we can use successive multiplication technique to convert a fractional decimal number into a
base-r representation.

Example:
Convert the decimal number 26.6875
10
to its binary representation.
26.6875
10
= 26
10
+ 0.6875
10

For the integer part, we have
26 2 = 13 R 0 Least significant bit
13 2 = 6 R 1
6 2 = 3 R 0
3 2 = 1 R 1
1 2 = 0 R 1 Most significant bit

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2011, ME, NUS Page: 9

For fractional part, we have
0.6875 x 2 = 1.375
0.375 x 2 = 0.750
0.75 x 2 = 1.500
0.5 x 2 = 1.000

Hence, the binary representation is
26.6875
10
= 11010.1011
2

Example:
Convert the decimal number 43.6
10
to its binary representation.
43.6
10
= 43 + 0.6
By repeated division by 2 for the integer part and multiplication by 2 for the fractional part.
For the integer part, we have
43 2 = 21 R 1 Least significant bit
21 2 = 10 R 1
10 2 = 5 R 0
5 2 = 2 R 1
2 2 = 1 R 0
1 2 = 0 R 1 Most significant bit

For the fractional part, we have

0.6 x 2 = 1.2
0.2 x 2 = 0.4
0.4 x 2 = 0.8
0.8 x 2 = 1.6
0.6 x 2 = 1.2
: :
: :
: :

Noting that the fractional conversion never ends, this implies that 0.6
10
does not has an exact
binary representation. Hence, the binary representation with 5 digits approximation is
43.6
10
= 101011.10011
2
(up to 5 digits approx.)

1.2.3 Octal to Decimal
Similarly, we use the weighted sum approach to convert Octal number to decimal number.

=
=
n
m i
i
i
A N 8
10
( 1.2.4 )
Example:
The octal number 326.4
8
can be converted to a decimal number by
326.4
8
= 3 x 8
2
+ 2 x 8
1
+ 6 x 8
0
+ 4 x 8
-1

= 192 + 16 + 6 + 0.5 = 214.5
10


1.2.4 Decimal to Octal
For decimal to octal conversion, we use repeated division by 8 for the integer part and repeated
multiplication by 8 for the fractional part.

MSB
LSB
MSB
Repeated
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Example:
Consider the decimal number 379.546875
10
, it consists of
379.546875
10
= 379
10
+ 0.546875
10

For the integer part, we have
379 8 = 47 R 3 Least significant digit
47 8 = 5 R 7
5 8 = 0 R 5 Most significant digit

For the fractional part, we have
0.546875 x 8 = 4.375
0.375 x 8 = 3.000

Hence, the octal representation is
379.546875
10
= 573.43
8


1.2.5 Octal to Binary
In general, for conversion from a non-decimal system to decimal system, we use the weighted
position method to do the conversion. On the other hand, the conversion from decimal to non-
decimal system use the method of successive division and multiplication by the radix value for
integer and fractional parts, respectively. How about the conversion between two non-decimal
systems? Say, from base-r to base-p, we can first convert the base-r number to its decimal
representation by weighted position method and followed by the successive and division by p to
base-p number.
However, for a special case of p and r that has the relationship of
i
r p = ( 1.2.5 )
For instance, the octal number has a radix of 8 and binary has a radix of 2 which has the
relationship of 8 = 2
3
. Table 1.2.1 shows that, each octal digit is matched to unique 3-bits binary
pattern.
Hence, we can simplify the conversion process by matching technique.
Table 1.2.1Octal digit to binary pattern
Octal digit 0 1 2 3 4 5 6 7
Binary pattern 000 001 010 011 100 101 110 111

Example:
The octal number 271.65
8
can be converted to its binary presentation by simple pattern matching
as show below.
271.658 = 010 111 001.110 1012

1.2.6 Binary to Octal
As each octal digit has a unique 3 binary bits code, we can convert the binary number to its octal
representation by first grouping the binary number in groups of 3 bits starting from the radix point.
Then, for each of the 3 bits pattern, match it with its corresponding octal value.
Example:
The binary number 1111100101.001110
2
can be converted to its octal representation by
1111100101.001110
2
= 001 111 100 101 . 001 110
2

= 1 7 4 5 . 1 6
8

= 1745.16
8

Most significant digit
Least significant digit
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2011, ME, NUS Page: 11
1.2.7 Hexadecimal to Decimal
Similarly, we use the weighted sum approach to convert hexadecimal number to decimal number.

=
=
n
m i
i
i
A N 16
10
( 1.2.6 )
Example:
The hexadecimal number 3B.4C
16
can be converted to its decimal representation by
3B.4C
16
= 3 x 16
1
+ 11 x 16
0
+ 4 x 16
-1
+ 12 x 16
-2

= 48 + 11 + 0.25 + 0.046875
= 59.296875
10


1.2.8 Decimal to Hexadecimal
For decimal to hexadecimal conversion, we use repeated division by 16 for the integer part and
repeated multiplication by 16 for the fractional part.

Example:
Consider the decimal number 379.546875
10
, it consists of
379.546875
10
= 379
10
+ 0.546875
10

For the integer part, we have
379 16 = 23 remainder 11 = B Least significant digit
23 16 = 1 remainder 7
1 16 = 0 remainder 1 Most significant digit

For the fractional part, we have
0.546875 x 16 = 8.75
0.75 x 16 = 12.00 = C.00
379.546875
10
= 17B.8C
16


1.2.9 Hexadecimal to Binary
Similarly, the hexadecimal number has a radix of 16 and binary has a radix of 2. Noting that 16 = 2
4,

this implies one hexadecimal digit will map to four binary bits. Table 1.2.2 shows that, each octal
digit is matched to unique 3-bits binary pattern.
For such case, we can simplify the conversion process by matching technique.
Table 1.2.2 Hexadecimal digit to binary pattern
Hex digit 0 1 2 3 4 5 6 7
Bin pattern 0000 0001 0010 0011 0100 0101 0110 0111
Hex digit 8 9 A B C D E F
Bin pattern 1000 1001 1010 1011 1100 1101 1110 1111

Example:
The hexadecimal number A94.65
16
can be converted to its binary representation as follows:
A94.6516 = 1010 1001 0100.0110 01012


1.2.10 Binary to Hexadecimal
Similarly, each hexadecimal digit has a unique 4 binary bits code; we can convert the binary
number to its octal representation by first grouping the binary number in groups of 4 bits starting
from the radix point. Then, for each of the 4 bits pattern, match it with its corresponding
hexadecimal value.
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Example:
1111100101.00111
2
= 0011 1110 0101 . 0011 1000
2

= 3 E 5 . 3 8
16

= 3E5.38
16

1.3 Codes and Coding
1.3.1 Binary Coded Decimal Code
While computers work in binary, humans work in decimal. This implies that, when computers
interface with people, conversions are needed to/from decimal/binary. In addition, to make thing
easier for programmer and to make equipment with read-outs compatible with computer interfaces,
numbers, letters or words are represented by group of symbols called code. There are many
different internationally accepted standard codes. Among them, binary coded decimal (BCD) is
one of the popular codes used in industries.
BCD is a code used to represent a decimal digit by its binary equivalent. There are many
variances of BCD code, the most common BCD is the 8421-BCD.

1.3.1.1 8-4-2-1 BCD Code
In 8421-BCD, each decimal digit is represented by a 4-bit binary number which also has the binary
numerical value of the decimal digit as shown in
Table 1.3.1.

Table 1.3.1 8421-Binary Coded Decimal
Decimal Digit BCD
0 0000
1 0001
2 0010
3 0011
4 0100
5 0101
6 0110
7 0111
8 1000
9 1001

Noting that 8421-BCD only used 10 out of the 16 possible combination of 4-bits binary number.
Some vendor use these remaining combination for some special characters likes '.', '-', 'E', '+' and
other symbols which might be associated with communicating a value.
Example:
39
10
0011 1001

107
10
0001 0000 0111

Note that conversion from BCD code to decimal is straight forward.
e.g.
0110 1000 0011 1001 (BCD Code) = 6839
10
6 8 3 9


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1.3.1.2 Comparison of BCD Code and Binary Number
BCD is not another number system like binary, octal or hexadecimal. It is not the same as straight
binary number. A straight binary code takes the complete decimal number and represents it in
binary. Whereas, the BCD Code converts each individual decimal digit to a set 4 bits binary code.
Example:
Decimal Number Binary Number BCD Code
137
10
10001001
2
0001 0011 0111
Noting that BCD requires more binary bits than straight binary number. To represent decimal
number 137 in BCD we need 12 bits of code (4+4+4). Whereas, for straight binary number
representation, an 8-bits binary number has the range of 0~255.

1.3.1.3 Other variance of BCD Code
There are many other variance of BCD used for some specific reasons. A few popular variances of
it is listed in Table 1.3.2 below.
Table 1.3.2 Variance of BCD Codes
Decimal
Digit
BCD
8-4-2-1 Excess-3
Biquinary
5 0 4 3 2 1 0
0 0 0 0 0 0 0 1 1 0 1 0 0 0 0 1
1 0 0 0 1 0 1 0 0 0 1 0 0 0 1 0
2 0 0 1 0 0 1 0 1 0 1 0 0 1 0 0
3 0 0 1 1 0 1 1 0 0 1 0 1 0 0 0
4 0 1 0 0 0 1 1 1 0 1 1 0 0 0 0
5 0 1 0 1 1 0 0 0 1 0 0 0 0 0 1
6 0 1 1 0 1 0 0 1 1 0 0 0 0 1 0
7 0 1 1 1 1 0 1 0 1 0 0 0 1 0 0
8 1 0 0 0 1 0 1 1 1 0 0 1 0 0 0
9 1 0 0 1 1 1 0 0 1 0 1 0 0 0 0

- 8-4-2-1: Most straightforward BCD representation, with the weight of each digit
corresponding to the same value as in the binary system
- Excess 3: Each value exceeds the normal binary value by three simplifies the carry
logic in parallel addition
- Biquinary: Used in communication
the numbers from 0 to 9 are divided into two groups and one position of the
code is used to determine in which group a given number is, and a five position
code is used to determine the number in the group.

1.3.2 Gray Code
Gray code, named after Frank Gray who introduce this code in 1947, is an encoding such that two
successive code differ in only one bit. It was originally designed to prevent spurious output from
electromechanical switches. It is often used in situations where other codes, such as binary, might
produce erroneous or ambiguous results during those transitions in which more than one bit of the
code is changing. A popular application of Gray code is in instrumentation and data acquisition
systems where absolute linear or angular displacement is measured. For instance, absolute optical
shaft encoders used in angular measurement.
Table 1.3.3 Example of a 4 bit Gray Code
Decimal Binary Gray Code Decimal Binary Gray Code
0 0000 0000 8 1000 1100
1 0001 0001 9 1001 1101
2 0010 0011 10 1010 1111
3 0011 0010 11 1011 1110
4 0100 0110 12 1100 1010
5 0101 0111 13 1101 1011
6 0110 0101 14 1110 1001
7 0111 0100 15 1111 1000
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Gray code is often referred as binary reflected code or cyclic code. Table 1.3.3 shows an example
of 4-bits Gray code with its corresponding 4-bit binary representation. A specific property of Gray
code is that the difference between two successive pair of number will only have only one bit
change only.
For instance, a change from 7
10
to 8
10
has all 4 bits changed in the case of binary number.
Whereas, the same situation will only has one bit change in the case of Gray code.

1.3.2.1 Advantage of Gray Code
This one-bit change feature of the Gray code has been utilized in many applications. For example,
it is used in absolute encoder. Figure 1.3.1 Comparison between Gray code and binary code. It
shows how the sensor values are read in both binary coded and Gray coded encoders. In position
1, both sensors read the value of 7 (binary=0111 and Gray=0100). Similar, in position 3, both
sensors read the value of 8 (binary=1000 and Gray=1100). However, in position 2, the sensor for
the binary coded encoder reads the value of 15 (binary=1111). Whereas, the Gray coded encoder
reads the value of 8 (Gray=1100). Hence, it can be seen that the binary coded encoder can get an
erroneous reading while the Gray coded encoder is more clean and less erroneous.

Figure 1.3.1 Comparison between Gray code and binary code.

1.3.2.2 Generation of Gray Code
The binary-reflected Gray code for n bits can be generated recursively by reflecting the bits (i.e.
lists them in reverse order and concatenates the reverse list onto the original list), prefixing the
original bits with a binary 0 and then prefixing the reflected bits with a binary 1. The base case, for
n = 1 bit, is the most basic Gray code, G = {0, 1}. The base case can also be thought of as a single
zero-bit Gray code (n = 0, G = {" "}), which is made into the one-bit code by the recursive process.

Method 1: Gray code construction
To generate the Gray Code, we utilize the reflected code properties as follows:
Step 1:
To generate an n-digit (say, n=4) Gray Code, we start by a 1 digit Gray Code
Decimal Gray Code
0 0
1 1

Step 2:
For 2 digits Gray Code, we first repeat the 1 digit Gray Code in the reverse order. Then insert 0s
to the left of these codes on the upper half and 1s on the lower half.
Decimal Gray Code
0 0 0
1 0 1
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2011, ME, NUS Page: 15
2 1 1
3 1 0

Step 3:
For 3 digits Gray Code, repeat Step 2 with 2-digit Gray Code and so on.
Decimal Gray Code
0 0 0 0
1 0 0 1
2 0 1 1
3 0 1 0
4 1 1 0
5 1 1 1
6 1 0 1
7 1 0 0

Step 4:
For 4 digits Gray Code, repeat Step 2 with 3-digit Gray Code and so on.
Decimal Gray Code
0 0 0 0 0
1 0 0 0 1
2 0 0 1 1
3 0 0 1 0
4 0 1 1 0
5 0 1 1 1
6 0 1 0 1
7 0 1 0 0
8 1 1 0 0
9 1 1 0 1
10 1 1 1 1
11 1 1 1 0
12 1 0 1 0
13 1 0 1 1
14 1 0 0 1
15 1 0 0 0


Method 2: Binary to Gray Code Conversion
The reflected code properties suggested a simple and fast method of translating a binary value into
the corresponding Gray code. Each bit is inverted if the next higher bit of the input value is set to
one. This can be interpreted as follows:
To convert a Binary number
0 2 1
b b b B
n n


= , to its corresponding Gray code
0 2 1
g g g G
n n


= , we use the formula

=
=
=
+
+
,
0 ,
1 , 1
1
1
i i
i i
i
b b
b b
g for i = 0, 1, , n-1 with b
n
= 0 ( 1.3.1 )


Method 3: Gray Code to Binary Conversion
To convert from Gray Code
0 2 1
g g g G
n n


= to its corresponding binary
number
0 2 1
b b b B
n n


= , we first define
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|
|
.
|

\
|
=

+ =
2 , mod
1
n
i j
j i
g S with 0 =
n
g . ( 1.3.2 )
Then, the binary number B can be calculated from

=
=
=
0 ,
1 , 1
i i
i i
i
S g
S g
b , for i = 0, 1, , n-1 ( 1.3.3 )

1.3.3 Alphanumeric Codes - ASCII Code

Table 1.3.4 ASCII Table
HEX MSD 0 1 2 3 4 5 6 7
LSD Bits 000 001 010 011 100 101 110 111
0 0000 NUL DLE SP 0 @ P ` p
1 0001 SOH DC1 ! 1 A Q a q
2 0010 STX DC2 " 2 B R b r
3 0011 ETX DC3 # 3 C S c s
4 0100 EOT DC4 $ 4 D T d t
5 0101 ENQ NAK % 5 E U e u
6 0110 ACK SYN & 6 F V f v
7 0111 BEL ETB ' 7 G W g w
8 1000 BS CAN ( 8 H X h x
9 1001 HT EM ) 9 I Y i y
A 1010 LF SUB * : J Z j z
B 1011 VT ESC + ; K | k {
C 1100 FF FG , < L \ l |
D 1101 CR GS - = M } m }
E 1110 SO RS . > N ^ n -
F 1111 SI US / ? O _ o DEL
Special ASCII Symbols
NUL Null VT Vertical Tabulation CAN Cancel
SOH Start of heading FF Form feed EM End of medium
STX Start of text CR Carriage return SUB Substitute
ETX End of text SO Shift out ESC Escape
EOT End of transmission SI Shift in FG File separator
ENQ Enquiry DLE Data link escape GS Group separator
ACK Acknowledge DC Device control RS Record separator
BEL Bell NAK negative ac knowledge US Unit separator
BS Back space SYN synchronous idle SP Space
HT Horizontal tab ETB end of transmission block DEL Delete
LF Line feed


In addition to numerical data, a computer need to handle non-numerical information. That is, in
addition to decimal digits, we also need codes to represent characters of the alphabet, punctuation
marks, and other special characters. These codes are called alphanumeric codes. These codes
are used primarily for data transfer from computer to input/output devices such as printers,
keyboards, modem etc.

To standardize on the representation of symbols, international codes are used. The most widely
used alphanumeric code is the American Standard Code for Information Interchange (ASCII), it is
the normally referred as askee code (ASCII). It is a seven-bit code which provides 128 (2
7
=128)
representation as shown in
Table 1.3.4 ASCII Table. The code covers 26 lowercase alphabet, 26 uppercase alphabet, 10
decimal digits, punctuation marks and a set of special characters which is normally known as
control characters. These control characters, as the name calls, are used to control the machine
via communication channel.
Number System and Codes
2011, ME, NUS Page: 17


Example 1:
The following is a message in ASCII.
100 1000 100 0101 100 1100 101 0000
+ + + +
H E L P

It represents the message HELP.

Example 2:
An operator is typing in a Basic program at the keyboard of a computer. Determine the ASCII
Code that will be entered into memory when the operator types GOTO 25.
Answer:
G 100 0111
O 100 1111
T 101 0100
O 100 1111
010 0000
2 011 0010
5 011 0101



1.3.4 Error Detection
The transfer of binary data and codes from one location to another is the most common operation
in digital systems. For examples:
- Transmission of digitized voice over a microwave link.
- Storage and retrieval data from external memory devices such as magnetic disks and tapes
- Transmission of information from a computer to a remote user terminal and another computer.

Figure 1.3.2 Noise on transmitted data
Whenever information is transmitted from one device (transmitter) to another device (receiver),
there is a possibility that errors can occur such that the receiver does not receive the identical
information that was sent by transmitter, due to noise disturbance. For instance, a 0 may be read
as 1 or vice versa. It would be nice if we can implement some kind of coding such that any
transmission error can be detected or corrected.
One example is the Biquinary Code in earlier section which has the format of
F
5
F
0
U
4
U
3
U
2
U
1
U
0
For a given number, there is only one 1 is each of the groups. That is, one 1 from F
5
F
0
and
another one 1 from U
4
U
3
U
2
U
1
U
0
. For instance, the number 7 will have the code 10 00100. So,
any single-bit error will make the code invalid. For example, say, there is an error on U
1
, resulted
Exercise:
1. Encode in ASCII, the string Cost = $72
2. The following ASCII message is stored in the memory. What is the message?
101 0011 101 0100 100 1111 101 0000
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in the code received as 10 00110. As there is two 1s in U
4
U
3
U
2
U
1
U
0
. This indicated that the
Biquinary Code is invalid, hence error is detected.

Parity Bit:
A common practice used is the introduction of parity bit. A parity bit is an extra parity bit appended
to the code group that is being transferred from one location to another. This additional bit can be
either 0 or 1, depends on the number of 1's that are contained in the code group. There are two
methods used, that is,
- Even Parity: add another 1 or 0 to ensure total number of 1's is even.
- Odd parity: add another 1 or 0 to ensure total number of 1's is odd.


Example:
Suppose that the character 'C' is to be transmitted, the code group is 100 0011. There are three 1's
in the ASCII code of 'C'.

Case 1:Even Parity
The value of the parity bit is chosen such that the total number of 1s in the code group (including
the parity bit) is even.
To make it even, 1 is added to the code as follows
1 100 0011
ASCII Code
Parity bit is 1 in even
parity mode

Case 2: Odd Parity
The value of the parity bit is chosen such that the total number of 1s in the code group (including
the parity bit) is odd.
To make it odd, 0 is added to the code as follows
0 100 0011
ASCII Code
Parity bit is 0 in odd
parity mode

Say, if the receiver actually receives the code 0100 0001, the receiver will know that an error has
occurred in the transmission because the received code has even number of 1s.
Note: The parity bit can only detect single-bit error only.


1.3.4.1 Effect of Parity Check
Parity checking may be employed at major interfaces in a digital system. Since redundancy is
added to each message, parity checks are used only when the probability of errors occurring and
the risk associated with an error is high enough to warrant it.
Consider a case that we are transmitting a 7-bit ASCII code between two devices.

Case I: (Without parity bit)
For a given transmission technique, the probability of a bit be transmitted wrongly is p (say, p = 3.1
x 10
-5
). Transmission rate is r (say, r = 400 bps)
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By transmitting without parity bit, the probability of transmitting an 7-bits ASCII code is P
7
,
P
7
= 1 (1 - p)
7
= 1- 0.999969
5
= 2.17 x 10
-4

and the transmission rate of R
7
,
R
7
= r/7 = 400/7 = 57.14 word per second
Alternatively, the average error rate is E
7
is
E
7
= 1/ P
7
x 1/ R
7
= 80 sec.

Case II: (With parity bit)
With the parity bit implemented, the single bit error will always be detected. Therefore we only look
at chances that 2 bits or more errors happen together. Hence, by transmitting with parity bit, the
probability of transmitting an 8-bits ASCII code is P
8
,
P
8
= 1 - (1-p)
8
8p(1-p)
7
= 2.69 x 10
-8

and the transmission rate of R
8
,
R
8
= r/8 = 50 word per second
Alternatively, the average error rate is E
8
is
E
8
= 1/ P
8
x 1/ R
8
= 743273 sec. = 8.6 days!
Clearly, with an additional bit used as in Case II, the reliability has increased tremendously.

1.3.5 Error Correction
Sometime, besides detecting the error, we want to be able to correct the error such that we can
save the time for re-sending the message. Or, there may be situation that the message cannot be
re-sent. For example, reading a corrupted CD-ROM, no matter how many time you re-read the
code, it is still invalid. It will be preferred that an auto-correction can be implemented in this case.
A popular error correction technique is the so-called Hamming Code.

1.3.5.1 Hamming Code
Hamming code involves the design of a code that combine m message bits (
0 1 2 1
M M M M
m m


)
with r extra parity bits (
0 1 2 1
P P P P
r r


) such that single-bit error in the code can be corrected.
r is chosen as the smallest number that satisfy the condition

r
r m 2 1s + +

( 1.3.4)

The r + m bits of code are arranged in the order by the following rules:
1. Add r parity bits to an m-bit message to form an r+m bits Hamming code.
2. Number the bit position from 1 to (r+m).
3. Place parity bit
i
P in (2
i
)
th
position, for i = 0,1, ... , r-1.
4. Fill the remaining m positions by the message bits.
5. Performs parity operation for each parity bit with the position correspond to the 2
i

positions.

The following example illustrate how a BCD code can be Hamming coded.

Example:
Consider the implementation of the Hamming Code on a 4 bit 8421-BCD code.
For 4 bit BCD code m = 4, therefore
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r
r 2 1 4 s + +
.
Clearly, a choice of r = 3 will satisfy the above condition.
Hence, we need 3 parity bits in position 2
0
=1, 2
1
=2 and 2
2
=4. And the code is arranged as follows:
Position 1 2 3 4 5 6 7
Code P0 P1 M3 P2 M2 M1 M0
For parity assignment, we view the parity bits P
2
P
1
P
0
as a 3-bit number, and P
i
will performs parity
operation with the position number with P
i
=1.
In this case,
Position Bit P2 P1 P0
1 (001) P0 \
2 (010) P1 \
3 (011) M3 \ \
4 (100) P2 \
5 (101) M2 \ \
6 (101) M1 \ \
7 (111) M0 \ \ \
Hence, the parity bits will check on
P
0
checks on {M
3
, M
2
, M
0
}
P
1
checks on {M
3
, M
1
, M
0
}
P
2
checks on {M
2
, M
1
, M
0
}
Say, for even parity and the code is 0110 (BCD 6)
P
0
= even { M
3
, M
2
, M
0
} = even { 0, 1, 0} = 1
P
1
= even { M
3
, M
1
, M
0
} = even { 0, 1, 0} = 1
P
2
= even { M
2
, M
1
, M
0
} = even { 1, 1, 0} = 0
Hence the code is 11 0 0 110

Error Correction
Say, during transmission, the code 110 0110 becomes 110 1110. We check for the even parity of
each parity bits
C
0
= even { M
3
, M
2
, M
0
} = even { 0, 1, 0} = 1 = P
0
E
0
=0
C
1
= even { M
3
, M
1
, M
0
} = even { 0, 1, 0} = 1 = P
1
E
1
=0
C
2
= even { M
2
, M
1
, M
0
} = even { 1, 1, 0} = 0 P
2
E
2
=1
Hence, the error position
E
2
E
1
E
0
= 100 = 4
Position 4 has error, it should be a 0 instead of 1.
the corrected code should be 110 0110

Graphical interpretation of Hamming Code
Effectively, Hamming codes uses the technique of elimination to identify the error bit. Hence the
detected error bit can be identified. Figure 1.3.3 shows graphically how each message bit is
associated with each parity bit. By simple interception, the error bit can be isolated. Hamming code
has strategically arranged the message bits and parity bits in such a way that the error code
(
0 1 2
E E E ) reflect the error bits position.
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Figure 1.3.3 Graphical interpretation of Hamming Code
- Homework: Any error in this code? if any, correct them, 10 1 0 011
1.4 Binary Arithmetic
1.4.1 Binary Addition
Binary addition works in the similar way as we do our decimal addition. We first has an addition
table which give the results of addition of two decimal digits combination. In fact, it is easier to
performs binary addition, as binary number has only two elements {0,1}. We first have the binary
addition table as shown below
0 + 0 = 0
0 + 1 = 1
1 + 1 = 0 plus carry of 1
1 + 1 + 1 = 1 plus carry of 1
Examples:
Consider the addition of two numbers 3
10
and 6
10
, we have

0 1 1
2
= 3
10
+ 1 1 0
2
= 6
10
1 0 0 1
2
= 9
10

Similarly, for the numbers 3.375
10
and 2.75
10
, we have

11.011
2
= 3.375
10
+ 10.110
2
= 2.75
10
110.001
2
= 6.125
10

- Exercise: Find the sum of 101.01 + 110 + 10.1.


1.4.2 Binary Subtraction
Similarly, We first have the binary subtraction table as shown below

0 - 0 = 0
1 - 1 = 0
1 - 0 = 1
0 - 1 = 1 with a borrow of 1
Example:
Consider the subtraction of the number 5
10
from 11
10
, we have
1011
2
= 11
10
- 0101
2
= -5
10
0110
2
= 6
10

Similarly, for the subtraction of 6
10
from 9.5
10
, we have
1001.1
2
= 9.5
10
- 0110.0
2
= -6.0
10
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0011.1
2
= 3.5
10

- Exercise: Find the sum of 101.01 - 10.1.

1.4.3 Binary Multiplication
The multiplication of binary numbers is carried out in the similar manner as the multiplication of
decimal numbers. It is in fact easier for binary multiplication as the multiplier digits are either 0 or 1
and nothing else.

Example:
Consider the multiplication of two numbers 45
10
and 5
10
, we have
101101
2

multiplicand 45
10

x 101
2

multiplier x 5
10

101101
2

Partial Products
225
10

000000
2

101101
2

11100001
2

Product

1.4.4 Binary Division
The binary division is the same as the decimal numbers except it is simpler in the case of binary
number. The following examples illustrate how binary division is carried out.

Example:
Consider the division of 9 by 3, we have
0011
2
=3
10
11
2
1001
2
011
0011
0011
0000
Similarly, the division of 10 by 4 yields
0010.1
2
=2.5
10
100
2
1010
2
100
0010
0000
0010.0
0010.0
0000.0


1.4.5 Representing Signed Numbers
In our daily life, we encounter negative values in many different forms. For instance, over draft in
your bank account, when you go to the basement of a building, in an extreme cold (below freezing
point) condition, etc.. These are just different forms of negative value representation. In general,
negative value can be represented in four forms as follows and is used by the computer in the
binary context.
- Signed magnitude representation
- By pre-pending a sign indicator in the number
N N
sm
=

( 1.4.1)
- Excess (Offset) representation
- By adding a bias to the number
B N N
xs
+ =

( 1.4.2)
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2011, ME, NUS Page: 23
- Radix complement representation
- By taking radix complement of an n-digit number is defined as
N r N
n
rc
=

( 1.4.3)
- Diminished radix complement representation
- By taking diminished radix complement of an n-digit number is defined as
N r N
n
drc
= 1

( 1.4.4)

Note: radix complement = diminished radix complement + 1.

1.4.5.1 Negative number representation for decimal number system
Signed-Magnitude Representation
This is by far, the most common way of signed representation that human has used. It is
represented by a sign symbol in front of the numeric number. The sign symbol {-.+} tells the sign of
the value and the number tells the magnitude of the value.
N N
sm
=

Example: + 456.4 , -564.4 , 56.3 , etc

Excess (Offset) Representation
Excess representation is also called biased representation, it uses a pre-specified number B as a
biasing value. A value is represented by the unsigned number which is B greater than the intended
value. Thus 0 is represented by B, and B is represented by 0.
B N N
xs
+ =
Example:
A bias of 0.5 for the number in the range of 0 to 1.
0.6 +0.1, 0.2 -0.3, etc

Radix Complement Representation
It is called the ten's complement in the decimal system. Say, for a 2 digit decimal number, its radix
complement is


N N
rc
=
2
10
10

( 1.4.5)

Example:
The 10s complement of a 2-digit decimal number 75 is 10
2
75 = 25.

Diminished Radix Complement Representation
The diminished radix complement in the decimal system is called the nines' complement. Say, for a
2 digit decimal number, its diminished radix complement is

N N
drc
= 1 10
2
10

( 1.4.6)

Example:
The 9s complement of a 2-digit number 75 is 10
2
1 - 75 = 24.

1.4.5.2 Negative number representation for binary number.
Signed-Magnitude Representation
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Similarly, it is represented by a sign symbol in front of the numeric number. The sign symbol {-.+}
tells the sign of the value and the number tells the magnitude of the value.

N N
sm
=

( 1.4.7)
For signed-magnitude representation of binary number, one way is to use the MSB of the number
as a sign bit. In general, the common convention is that a 0 in the sign bit represents a positive
number and a 1 in the sign bit represents a negative number.
The Figure below illustrates how the +104
10
and 104
10
are represented by an 8-bit signed
magnitude representation. Bit-7 is used as the sign bit to indicate the sign of the number. The
magnitude of the number is represented 7-bit binary number (b
6
-b
0
).
b
7
b
6
b
5
b
4
b
3
b
2
b
1
b
0

0 1 1 0 1 0 0 0 = + 104
10
Positive number
|

Magnitude = 104

Sign bit (+)

b
7
b
6
b
5
b
4
b
3
b
2
b
1
b
0

1 1 1 0 1 0 0 0 = - 104
10
Negative number
|

Magnitude = 104

Sign bit (+)

However, such notation requires very complicated logic and not commonly used in computer.
Noting that this notation will has a case for negative zero when we have the value of 1000 0000!

Excess (Offset) Representation
In the binary context, the bias value B is usually chosen to be around the middle of the range. Say,
for an n-bit binary number, we choose B = 2
n-1
1. Hence, Excess representation will have the
number
1 2
1
+ =
n
xs
N N

( 1.4.8)
The excess representation will have a range of -(2
n-1
- 1) ~ (2
n-1
). We call it an excess (2
n-1
1)
representation.

Example:
For 8-bit binary number, we have
B = 2
7
1 = 127
and the number will have the representation of
127 + = N N
xs
.
We call this Excess-127 representation. It will have the range of -127~128.


- Diminished Radix Complement Representation
In the binary context, it is called 1s complement form. For an n-bit number, the diminished radix
complement is defined as

2
1
2
1 2 N N
n
= .

( 1.4.9)
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2011, ME, NUS Page: 25
The 1s complement is also known as the logical complement. This is because, the value 2
n
1
will all the bits of the binary number equal to ones. The operation of 2
n
-1 N
2
will results in
inverting every bits of the binary number N
2
.

Example:
The 1s complement of a 4-bit binary number, say, 1001
2
will be
( )
2
2 2
2
4 1
2
0110
1001 1111
1001 1 2
=
=
= N

Hence, the digital implementation of 1s complement will be a simple NOT operation on every bits
of the number as shown in Figure 1.4.1.


Figure 1.4.1 Digital Ones Complement Implementation

Radix Complement Representation for binary number
In the binary context, it is also called 2s complement form. For an n-bit number, the radix
complement is defined as

2
2
2
2 N N
n
=

( 1.4.10)
This is sometime known as the arithmetic complement. Noting from (1.4.9) and (1.4.10) that

1 1 1 2
2
1
2 2
2
2
2
+ = + =
=
N N
N N
n
n

( 1.4.11)
Hence, the 2s complement can be computed by first computing its 1s complement and followed
by adding a 1 to the result as shown in the example below.
Example:
For a 4-bit number N
2
= 0110
2
0110

1001

1001
+ 1
1010
number 1s complement 2s complement

The 2s complement has the problem of double representation. For an n-bit binary number N
A
in
the range of 0~2
n
-1, there exist another number
A
n
B
N N = 2 also in the range of 0~2
n
-1 (Except
for the cases of N
A
=0 or N
A
=2
n-1
). Noting that, by definition, N
B
is the 2complement of N
A
and vice
versa. This implies that the number N
A
represents both the value of N
A
and the 2complement of
N
B
. Table 1.4.1 illustrates the case of a 3-bits representation. To avoid the duplicated
representation, the shaded cells are not used in the representation. That is, the 3 bit-binary with
2s complement signed representation has the range of -4~3.
Table 1.4.1 2Complement of 3-bit binary number
Decimal Binary 2s Complement
0 000 000 (-0)
1 001 111 (-1)
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2 010 110 (-2)
3 011 101 (-3)
4 100 100 (-4)
5 101 011 (-5)
6 110 010 (-6)
7 111 001 (-7)

Table 1.4.2 Shows the various sign representation for a 4-bit binary number. Sign magnitude an
1s complement notation have the negative zero presentation which is meaningless in practice.
Also, without the explicit setting of sign bit like the sign magnitude notation, all representation has
the most significant bit reflecting the sign of the number. All representations has 0 indicating a
positive number and 1 indicating a negative number except the Except the Excess-7 with the
indication reversed.

Table 1.4.2 Comparison between various signed representation
Decimal Unsigned Sign Magnitude Excess-7 1s Complement 2s Complement
+15 1111
+14 1110
+13 1101
+12 1100
+11 1011
+10 1010
+9 1001
+8 1000
+7 0111 0111 1110 0111 0111
+6 0110 0110 1101 0110 0110
+5 0101 0101 1100 0101 0101
+4 0100 0100 1011 0100 0100
+3 0011 0011 1010 0011 0011
+2 0010 0010 1001 0010 0010
+1 0001 0001 1000 0001 0001
+0 0000 0000
0 0000 0111 0000
-0 1000 1111
-1 1001 0110 1110 1111
-2 1010 0101 1101 1110
-3 1011 0100 1100 1101
-4 1100 0011 1011 1100
-5 1101 0010 1010 1011
-6 1110 0001 1001 1010
-7 1111 0000 1000 1001
-8 1000


1.4.5.3 Binary Arithmetic with 2s Complement.
Consider the subtraction of an n-bit binary number N
B
from another n-bit binary number N
A
, we
have
( )
n
B A
n
B
n
A B A
N N
N N N N
2
2 2
2
+ =
+ =

where
B
n
B
N N = 2
2
denotes the 2s complement of N
B
. The above expression can be re-
arranged as
n
B A B A
N N N N 2
2
+ = + . ( 1.4.12)
Noting that 2
n
is outside the n-bit binary range of 0~2
n
-1. Hence, the performance of
2
B A
N N + will
result in subtracting N
B
from N
A
with the value 2
n

store in the carry-over bit which will not be
reflected in the sum register.
Example:
Subtracting 4
10
from 12
10
in an 8-bit operation will has the following:
Number System and Codes
2011, ME, NUS Page: 27
12
10
= 0000 1100
2

4
10
= 0000 0100
2

2s complement of 4
10
= 1111 1100
2

We have
12
10 0000 1100
2

- 4
10 + 1111 1100
2

1 0000 1000
2

|
This carry is disregarded.

1.5 Numeric Notation Used in Computers
It is known that the computer uses binary arithmetic. That is, numbers are stored in its binary form.
Depending on the kind of problem we are solving, we may require values of different range. In
computer systems, numbers can be stored in the following notations
- Integer Notation
- Floating point notation

1.5.1 Integer Notation
In computer, integer variable refers to integer representation usually in forms of multiple byte(s) of
integer size. It has two forms of representation, i.e., unsigned integer or signed integer.

Unsigned Integer
This is the weighted position representation for binary number. For an n-bit binary representation
will have the range of 0~2
n
-1. The size of the integer is usually chosen with n equals to multiple of 4.
For examples, 4 (nibble), 8 (byte), 16 (word), etc..
The figure below shows an 8-bit unsigned integer representation with a range from 0 to 255.
b
7
b
6
b
5
b
4
b
3
b
2
b
1
b
0

0 1 0 1 0 1 0 1 =85
10

8-bit unsigned integer

Singed Integer
In computer, signed integer uses the 2s complement representation. Say, for 8-bit signed
integer as shown below, it has the range from -128 to 127. As illustrate in earlier section, the most
significant bit (b
7
) will have the properties of a sign bit due to 2s complement notation used.
The figure below shows an 8-bit signed integer representation with a range from -128 to 127.

b
7
b
6
b
5
b
4
b
3
b
2
b
1
b
0

1 0 1 0 1 0 1 1 =-85
10


Sign bit number


1.5.2 Floating Point Notation
1

A floating-point number N
f
in radix r has the general form

E
f
r F N =

( 1.5.1)

1
Dorf, R. C. (1993). The Electrical Engineering Handbook. CRC Press.

ME3241/ME3241E Microprocessor and Applications
Page: 28 2011, ME, NUS
where 1 0 < s F is the fraction (or mantissa) and E is the exponent.
For example, electron mass m
e
= 9.109 x 10
-31
Kg can be represented as follows.
m
e
= .9109 x 10
-30
Kg

= .09109 x 10
-29
Kg

= .009109 x 10
-28
Kg

All these adhere to the form as described by (1.5.1) are correct floating point representation. In
order to be more consistent, a further constrain has been imposed on F such that the most
significant digit must be a non-zero digit except in the case of F=0. That is, the standard
representation is m
e
= .9109 x 10
-30
Kg and is called the normalised floating point representation.

In the computer, binary system is used, an n-bit normalised floating point representation is defined
as
( )
2
2 1
2
E s
f
F N =
where { } 1 , 0 e s is the sign bit. 1 1 . 0
2 2
< s F is the mantissa which has the value of
m
m
m
m
n
n
n
n
i
i
i
F
b F

=
+ =

|
|
.
|

\
|
+ =

2 1 . 0
2 2 1 . 0
, 2 2
2
0
2 2

where n
m
is the number of significant binary places and
m
n
F
, 2
is the n
m
- 1 bit mantissa value stored
in the computer. Noting that, for an m binary places fractional number, only the n
m
-1 least
significant digits are stored. This is because the condition of 1 1 . 0
2 2
< s F implies that the most
significant digit is always a one and is there not stored.
E
2
is the exponent of the floating point representation which needed to be a signed number. That is
E
2
>>0 for large value representation and E
2
<<0 for small value representation. For the
convenience of floating point addition and subtraction implementation, E
2
is stored in the computer
as an n
e
-bit signed number in excess representation with the bias value of 1 2
1
=

e
e
n
n
B . That is,
the n
e
-bit signed number,
e e
n n
B E E + =
2 , 2

will have the range of 1~ ( ) 2 2
e
n
which corresponds to the exponent E
2
with the range of
( ) 2 2
1


e
n
~( ) 1 2
1

e
n
.
In computer the floating number are stored by packing { }
m e
n n
F E s
, 2 , 2
, , into a
m e
n n n + = bits
memory. Table 1.5.1 shows how nm and ne are distributed for various precisions by IEEE
standard for floating point representation.



Table 1.5.1 IEEE implementations of floating point number
Precision N n
m
n
e
E
2
(Min) E
2
(Max)
Single 32 23+1 8 -126 127
Double 64 52+1 11 -1022 1023
Quadruple 128 112+1 15 -16382 16383

Number System and Codes
2011, ME, NUS Page: 29
31 30 thru 23 22 through 0
Sign
Bit
Exponent Mantissa
Assumed position of radix
point, with 0.1
2
hidden

Figure 1.5.1 32-bit normalised floating point representation

Figure 1.5.1 shows the IEEE standard defined for a normalised 32-bit floating representation. The
most significant bit, b
31
, is used as the sign bit, s. The mantissa is represented by a 24-bit fractional
binary representation with
m
n
F
, 2
stored in b
0
to b
22
. The exponent uses an 8-bit Excess-127
representation. It is stored in b
23
-b
30
. It has a range of -126~127.
In this representation, s defines the sign of the number, F
2
defines the significant of the number
and E
2
tells the order of the number. It can represent a range of
38 127 127
10 70141 . 1 2 2 111 111 . 0 = = . The smallest normalised representation it can
represents is when E
2
= -126 and F
2
= 0.1
2
. This will gives a value of
39 126
10 5.87747 2 5 . 0

= .
This normalised representation has a problem that the exact zero can not be represented since the
most significant binary place of F
2
is always a one. To address this problem, we note that the n
e
-bit
excess form exponent,
e
n
E
, 2
, only uses the range of 1~( ) 2 2
e
n
. The values 0 and ( ) 1 2
e
n
(0
and 255 in this case) have been reserved for special use. The case of 0
, 2 , 2
= =
m e
n n
F E has been
used to represent the exact zero. Whereas the case of 255 1 2
, 2
= =
e
e
n
n
E and 0
, 2
=
m
n
F is
used to represent the infinity (). In the case of 0
, 2
=
m
n
F , 0
, 2
=
e
n
E indicates a subnormal
representation (or floating point underflow situation) and 255 1 2
, 2
= =
e
e
n
n
E indicates an invalid
floating point representation or NaN (Not a Number). These various cases are summarised in the
Table below.
e
n
E
, 2
(
2
E )
m
n
F
, 2
=0
m
n
F
, 2
= 0
0 (-127) 0 Subnormal numbers
1~254 (-126~127) Normal floating point number
255 (128) Nan


Example1:
The number 45.78125
10
is stored in the 32-bit normalised floating point number as follows:
45.78125
10
= 101101.11001
2

Shifting the binary places yields
101101.11001
2
= 0.10110111001
2
x 2
6

From the above, we have
s = 0
2
E = 6
e
n
E
, 2
= 6
10
+127
10
= 10000101
2

2
F = 0.10110111001
2

m
n
F
, 2
= 011 0111 0010 0000 0000 0000
The floating point representation is the packing of { }
m e
n n
F E s
, 2 , 2
, , as follows:
Floating point number = 0 10000101 01101110010000000000000

ME3241/ME3241E Microprocessor and Applications
Page: 30 2011, ME, NUS

Example2:
Determine the decimal value of the normalised 32-bit floating point representation
1 01111101 11000000000000000000000.
From the above, the sign bit
s = 1.
The exponent in excess-127 notation is
e
n
E
, 2
= 01111101
2
= 125
10

2
E = 125
10
- 127
10
= -2
10

The mantissa with the implied 0.5 removed is
m
n
F
, 2
= 11000000000000000000000
2
= 6291456
10

2
F = 0.5 + 2
-24
x 6291456
10
= 0.875
10

Hence the floating point representation has the decimal value of
( )
2
2 1
2
E s
f
F N = = (-1)
1
x 0.875
10
x 2
-2
= -0.21875
___________________________



2011, ME, NUS Page: 31
Chapt er 2 DIGITAL ELECTRONICS

2.1 Introduction
Engineers generally classify electronic circuits as being either analogue or digital in nature. A brief
guideline to differentiate between analogue and digital is look at the transistor used in circuit. If the
transistor is operating in the linear region, it is lightly that the circuit is an analogue circuit. Whereas, if
the transistor operator in saturated region, it is lightly that it is a digital circuit. In practical context, the
signs of a device contains digital circuitry can be deduce by observing the any existence of
alphanumeric display, memory and programmability.
2.2 Boolean algebra
In digital systems, the information being processed is usually presented in binary form. Binary
quantities can be represented by any device that has only two operating states. In Boolean context,
the two states are TRUE and FALSE. Many real life examples can be expressed in these binary
states. For example, a creature is either alive or dead, a door is either open or closed, etc. In digital
logic circuits, it often uses predefined voltages to represent these binary states. For example, in TTL
logic, 5 v represents a true case and 0 v represent a false case.
The concept of logical decision has been formalized by the mathematician, George Boole (1854),
which expressed logical decision in the form of symbols operated by various logical operators. Such
expression is commonly referred as Boolean expression or Boolean algebra. The main purpose of
this logical expression is to describe the relationship between a logical circuits output (decision) and
its input (circumstances).
These are summarized as follows:

2.2.1 Definition
A Boolean Algebra is an algebra ( { } 1 , 0 = B ; -,+,
-
,0,1) consisting of a set B together with three
operations, the AND (Boolean product) operation -, the OR operation (Boolean sum) operation +, and
the NOT (complement) operation
-
defined on the set, such that for any B e y x, , B e - y x (AND
operation), B e + y x (OR operation) and B e x (complement operation).
For the Boolean algebra, the following Axioms hold:
1. Commutative: x.y = y.x x + y = y + x
2. Associative: x.(y.z) = (x.y).z (x + y) + z = x + (y + z)
3. Distributive: x.(y + z) = x.y + x.z x + (y.z) = (x + y).(x + z)
4. Identity: Identify for - (1)
x-1 = x
Identify for + (0)
x + 0 = x
5. Complement:
0 = - x x 1 = + x x

2.2.2 Boolean Identities
With the axioms above, further Boolean identities can be derived as follows. The proofs of these
theorems are left to the reader as an exercise.
Involution Laws
( ) x x = , B e x
Idempotent Laws x x x = + , x x x = - , B e x
Bound laws 1 1= + x , 0 0 = - x , B e x
Absorption laws x y x x = - + , ( ) x y x x = + - , B e x
0 and 1 laws
1 0 = , 0 1 =
DeMogans laws
( ) y x y x - = + , y x y x + = - , B e x

Chapter 2 DIGITAL ELECTRONICS
Page: 32 2011, ME, NUS
2.3 Integrated Circuit Logic
2.3.1 Digital IC Terminology
The IC technology has advanced rapidly with more and more gates packed within a single chip so that
the overall size of all digital system is reduced. These advancements have made digital circuit very
easy to implement with user only focus on the functional aspect of the IC modules. However, there are
some basic important properties of digital circuits that is important for the user. Some terms are
defined and discussed below:

2.3.1.1 Current and Voltage Parameters
+
VOH
-
+
VIH
-
IOH IIH
+
VOL
-
+
VIL
-
IOL IIL
+5V

V
IH
(min) High-Level Input Voltage
- The minimum input voltage level required for a logical 1 to be read. Any voltage below this
level will not be guaranteed as a HIGH by the logic circuit.
V
IL
(max) Low-Level Input Voltage
- The maximum input voltage level required for a logical 0 to be read. Any voltage above
this level will not be accepted as a LOW by the logic circuit.
V
OH
(min) High-Level Output Voltage
- The minimum output voltage that is generated at a logic circuit output in the HIGH or
logical 1 state. Typical output voltage will be higher than V
OH
.
V
OL
(max) Low-Level Output Voltage
- The maximum voltage that is generated at a logic circuit output in the LOW or logical 0
state. Typical value will be lower than V
OL
.
I
IH
High-Level Input Current
- The current that flows into an input when a specified high-level voltage is applied to that
input.
I
IL
Low-Level Input Current
- The current that flows into an input when a specified low-level voltage is applied to that
input. For TTL, it is usually negative indicating that the current flows out of the input
(current sourcing).
I
OH
High-Level Output Current
- The current that flows from an output in the logical 1 state under specified load condition.
I
OL
Low-Level Output Current
- The current that flows from an output in the logical 0 state under specified load condition.

2.3.1.2 Fan-out
The fan out or sometime referred as loading factor is defined as the maximum number of standard
logic inputs that an output can drive reliably. If a logic gate has a fan out of 10, then it can drive 10
standard inputs. If this number is exceed, the output voltage level can not be guaranteed.

2.3.1.3 Transition Times and Propagation Delays
While some digital circuits respond to logic levels (level triggered) at their input, others respond to a
rapid change in voltage(edge triggered). In the latter type, it is essential that input signals have
sufficiently fast level transitions, otherwise, the circuit may not respond properly. For this reason, the
RISE TIME (T
R
) and the FALL TIME (T
F
) of a circuit output is often specified. These values are not
always equal, and are both dependent on the output loading.
ME3241/ME3241E Microprocessor and Applications
2011, ME, NUS Page: 33
A logical signal always experiences a delay in traveling through a circuit. The two propagation delay
times are defined as:
- t
PLH
: delay time in going from a logical 0 to a logical 1. (i.e. LOW to HIGH)
- t
PHL
: delay time in going from a logical 1 to a logical 0. (i.e. HIGH to LOW)

1
0
1
0
50%
50%
Input
Output
tPHL tPLH


Propagation times are used as a measure of the speed of response of logic circuits. Typical values
are of the order of 10 to 20 nanoseconds (ns). In general, t
PLH
and t
PLH
are not the same value and
both will vary depending on capacitive loading conditions.

2.3.1.4 Power Requirements
ICCL
+VCC
ICCL
1
1
1
1
1
1
1
1
1
0
0
0
ICCH
+VCC
ICCH
0
1
1
0
1
1
0
1
1
1
1
1

Every IC chip needs electrical power to operate. The amount of power supplied to and consumed by
an IC is very important because many circuits are made up of very large numbers of ICs and thus the
power requirements could become astronomical. Therefore, it is highly desirable to have ICs that
have extremely low power requirements. The power requirements of an IC are given in the
manufacturers specifications. Sometimes it is given as average power dissipation (P
D
). But, more
commonly, it is indirectly specified in terms of the current drain (I
CC
) from the power supply. The
power dissipation can then be determined by multiplying I
CC
by the power supply voltage (V
CC
).
P
D
= I
CC
V
CC
For some ICs the supply current is different for the two logic states. When this is the case, two values
for I
CC
are specified. I
CCH
is the supply current when all of the outputs are HIGH; I
CCL
is the supply
current when all of the outputs are LOW. Thus, an average current drain can be expressed as
I
CC
(avg) =
2
CCL CCH
I I +

or
P
D
= I
CC
(avg) V
CC


2.3.1.5 Noise Immunity
In logic systems, noise is any unwanted signal appearing at the input gate. The NOISE MARGIN
specifies the allowable magnitude of input noise. If this input is exceeded, the data may be switched
spontaneously creating an incorrect output resulting in system failure.
Chapter 2 DIGITAL ELECTRONICS
Page: 34 2011, ME, NUS
Input noise can originate from many sources such as arc or spot welding equipment, fluorescent lights,
etc. Avoid running cables in noisy environments, keep all leads as short as possible, and use
shielded cable. Ensure good connections and use well regulated poser supplies.
The HIGH STATE NOISE MARGIN is defined as:
V
NH
= V
OH
(min) - V
IH
(min)
The LOW STATE NOISE MARGIN is defined as:
V
NL
= V
OL
(max) - V
IL
(max)
Some Typical noise margins are illustrated in the figure below.
LOGIC 1
Indeterminate
range
LOGIC 0
LOGIC 1
Indeterminate
range
LOGIC 0
V
OH
(Min)
V
IH
(Min)
V
NH
V
IL
(Max)
V
OL
(Max)
V
NL
2.4
0.4
2.0
0.8
Output Voltage Range Input Voltage Range


Example: (some typical TTL characteristics)
Parameter Min (V) Typical (V) Max (V)
V
OH
2.4 3.4
V
OL
0.2 0.4
V
IH
2.0
V
IL
0.8

V
NH
= V
OH
(min) - V
IH
(min)
= 2.4 2.0
= 0.4 V
V
NL
= V
OL
(max) - V
IL
(max)
= 0.8 0.4
= 0.4 V

2.3.1.6 Current Sourcing and Current Sinking Logic
Logic families can be categorized according to how current flows from the output of on logic circuit to
another. The figures below illustrate the difference between the two types.
Low
IIH Low
VOH

High
IIL
High
VOL
+VCC


Current Sinking
receives current from load gate in
LOW state
Current Sourcing
Supplies current to load gate in
HIGH state
ME3241/ME3241E Microprocessor and Applications
2011, ME, NUS Page: 35
2.3.2 TTL Logic
2.3.2.1 Operation of TTL Logic Devices (Totem-pole Output Circuits)
Since the transistor-transistor logic (TTL) family is widely used, we will examine the operation of a
typical TTL NAND gate. Because NAND gate can be used to generate many types of logic functions,
an understanding of the operation of this simple gate provides a good insight into the operation of
most TTL devices.
The figure below shows the circuit diagram for a basic two input TTL NAND gate.
The input to the device is a multiple-emitter transistor (Q
1
). Because of the way in which it is used in
the circuit it can be simplified, for analysis purposes, by using its diode equivalent. This equivalent is
shown in the shaded box to the right of the figure below. Diodes D
2
and D
3
represent the two E-B
junctions of Q
1
, and D
4
is the collector-base (C-B) junctions.
Noting that the output of the circuit consist of two transistors Q
3
and Q
4
stacked on top of one another
and resemble a Totem pole, thus the terminology of a totem pole arrangement for this kind of
configuration is used.
The job of Q
3
is to connect V
cc
to the output, making a logic HIGH. Whereas, the job of Q
4
is to
connect the output to ground, making a logic LOW. The importance of this output arrangement will be
discussed shortly.

Case I: Output Low-State
When the inputs A and B are both HIGH, the two diodes D
2
and D
3
which represent the two base-
emitter diodes will not conduct. Therefore the current from the +5v supply through resistor R
1
will flow
through diode D
4
into the base of transistor Q
2
. This base current into Q
2
will turn Q
2
ON. The emitter
current from Q
2
will produce a base current into Q
4
which turns Q
4
ON while at the same time the
voltage at the collector of Q
2
is kept low enough to ensure that no base current flows into the base of
Q
3
. Thus, ensures that Q
3
remains turned OFF. Diode D
1
is the insurance that the output will be very
LOW since the emitter of Q
4
is shorted to the ground. Therefore, if both input A and B are HIGH, the
output of the gate is LOW.

Chapter 2 DIGITAL ELECTRONICS
Page: 36 2011, ME, NUS
Case II: Output HIGH case
Consider the case when A is HIGH and B is LOW as shown below. Current will flow from V
cc
through
R
1
and diode D
3
to ground. This will clamp the voltage at point X as shown below too low to generate
a base current into Q
2
to turn it ON. Hence, Q
2
is OFF. This will results in no sufficient base current
into Q
4
and implies Q
4
will also be turned OFF. Since Q
2
is OFF, the voltage at the collector of Q
2
is
now sufficiently high to generate base current into Q
3
to turn Q
3
ON. Since Q
3
is ON, it produces a
produces a high voltage via the pull up resistor R
4
and results in turning the Diode D
1
ON. As a result,
the output will has the HIGH output voltage. (approx. 3.6v).


Further analysis will shows that the above circuit behave like a NAND gate. There are a few points
regarding Totem pole output circuit. The circuit would in fact operate if Q
3
and D
1
are eliminated from
the circuit and the bottom of the resistor is connected directly to the collector of Q
4
. However, under
this circumstance, Q
4
would conduct a fairly high current in its saturation state. Using the totem-pole
configuration with Q
3
present, there will be no current through R
4
in the LOW output state. This will
reduce the power dissipation of the circuit.
Another advantage of totem-pole arrangement occurs in the HIGH output state. Since Q
3
is acting as
an emitter-follower, its associated low output impedance (typically 10O) results in a short rise time
constant for charging up any capacitive load on the output. This action is called active pull-up and
provides very fast rise times at TTL outputs.
One disadvantage of totem-pole arrangement occurs during a LOW to HIGH transition. Q
4
turns OFF
more slowly than Q
3
turns ON. As a result, there is a period of a few nanoseconds when both
transistors are conducting and resulting in a relatively large current surge (30-40mA). It is for this
reason that in many IC circuits you will see numerous small capacitors connected from V
cc
to ground.
This is termed power supply decoupling which prevents a voltage spike from occurring on the V
cc
line.
Another important note to take is never tie the outputs of conventional TTL totem-pole output
circuitry together. Such connection may cause excessive current draw through the transistor Q
4
(ON)
of the gate in the LOW output state while other output are in the HIGH state.

2.3.2.2 TTL loading and Fan-out

R4
Q3
Q4
D1
OFF
ON
IOL
IIL IIL

R4
Q3
Q4
D1
OFF
ON
IOH
IIH IIH

ME3241/ME3241E Microprocessor and Applications
2011, ME, NUS Page: 37
If a high state output of a driving chip can source X amount of current and the input of the driven chip
can sink Y amount of current, then the high state fan-out or the number of inputs the output can drive
is simply the integer value of X/Y. i.e.
Fan-out (High) =
I
OH
(max)
I
IH
(max)

Similarly, the low state fan-out is defined as,
Fan-out(Low) =
I
OL
(max)
I
IL
(max)

Example:
How many 7400 NAND gate inputs can be driven by a 7400 NAND output?
Solution:
From the data sheet, we can see that
I
OL
(max) = 16 mA, I
IL
(max) = 1.6 mA
I
OH
(max) = 400 A, I
IH
(max) = 40 A
Therefore,
Fan-out(Low) =
I
OL
(max)
I
IL
(max)
=
16 mA
1.6 mA
= 10
Fan-out(High) =
I
OH
(max)
I
IH
(max)
=
400 A
40 A
= 10
i.e. the fan-out is 10

Unit Load:
Since all ICs do not have the same current characteristics or specifications, and the actual fan-out
depends on the combination of driving and driven ICs. It would be impossible to specify an absolute
fan-out value. As a result, standardized input and output loading factors have been established which
allow the input and output currents been expressed in terms of standard unit loads. Some
manufacturers specify the device input and output currents in terms of a unit load (UL), where a unit
load is defined as follows:
1 unit load (UL) =

40 A in the HIGH state


1.6 mA in the LOW state

These unit load factors are used to express the output drive capability and input loading requirement
for TTL circuits. The following examples show how these concepts are used.

Example1:
Say, if a given IC is specified as having a fan-out of 10 UL in both states, this implies that:
I
OL
(max) = 10 x 1.6 mA = 16 mA
I
OH
(max) = 10 x 40 A = 400 A

Example2:
For the 7400 NAND gate in previous slide we have,
I
OL
(max) = 16 mA, I
IL
(max) = 1.6 mA, I
OH
(max) = 400 A, I
IH
(max) = 40 A
The output drive capability is
drive capability(Low) =
I
OL
(max)
1.6 mA
=
16 mA
1.6 mA
= 10 UL
drive capability (High) =
I
OH
(max)
40 A
=
400 A
40 A
= 10 UL
Chapter 2 DIGITAL ELECTRONICS
Page: 38 2011, ME, NUS
Therefore, in both HIGH and LOW states, the output can drive 10 UL.
The input requirement for this IC can be expressed as
Loading(Low) =
I
IL
(max)
1.6 mA
=
1.6 mA
1.6 mA
= 1 UL
Loading (High) =
I
IH
(max)
40 A
=
40 A
40 A
= 1 UL
Therefore, in both HIGH and LOW states, the input has a loading factor of 1 UL.
That is, if the output of 7400 is connected to identical 7400 IC, the fan-out in both LOW and HIGH
states is (10 UL/ 1 UL) = 10.

Example3:
Consider now the 74S00 IC. The specs are as follows:
I
OL
(max) = 20 mA, I
IL
(max) = 2 mA, I
OH
(max) = 1000 A, I
IH
(max) = 50 A
The output drive capability is
drive capability(Low) =
I
OL
(max)
1.6 mA
=
20 mA
1.6 mA
= 12.5 UL
drive capability (High) =
I
OH
(max)
40 A
=
1000 A
40 A
= 25 UL
Therefore, 74S00 can drive 25 UL in HIGH state and 12.5 UL in LOW state.
The input requirement for this IC can be expressed as
Loading(Low) =
I
IL
(max)
1.6 mA
=
2 mA
1.6 mA
= 1.25 UL
Loading (High) =
I
IH
(max)
40 A
=
50 A
40 A
= 1.25 UL
Therefore, 74S00 has a loading factor of 1.25 in both HIGH and LOW states. That is, if the output of
74S00 is connected to identical 74S00 IC, the fan-out in the HIGH state will be 25/1.25 = 20 and the
fan-out in the LOW state will be 12.5/1.25 = 10.

Example4:
Consider now the output of 7400 driving the input of 74S00.
From the unit load calculated in previous examples, the fan-out of 7400 to drive 74S00 in both HIGH
and LOW states will be
10/1.25 = 8.
Home work:
How about 74S00 driving 7400?

2.3.2.3 Unused and unconnected inputs
Sometimes it occurs that not all of the inputs on logic gate are required to perform the required logic
function. Any unconnected input will be treated as a HIGH. When an input is left unconnected, it is
said to be floating. It is not advisable to let the input floating. Although it behave like a HIGH, but this
unconnected input also serve as an antenna which can pick up stray signals causing the gate to
operate improperly.
Some common method to unconnected inputs is by
ME3241/ME3241E Microprocessor and Applications
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Use a pull-up resistor

Connect to ground

Connect the input together
X = A + B
A
B
or

2.3.2.4 Tri-state logic devices
Tri-state digital integrated circuit devices are extremely important particularly with respect to their use
in computer circuits. As the name implies, these device have three output states. In addition to
having the normal HIGH or LOW output state, it has an additional HIGH IMPEDANCE output state.
When the output of the device is in this high impedance state, for all intensive purposes, it can be
considered that its output is disconnected from the circuit.
A tri-sate device has one additional input which is called a control input. If the control input is LOW,
the gate operates in exactly the same manner as a conventional TTL gate and the output will have the
usual HIGH or LOW depending on the gates input(s) present. The control input is HIGH, the output
gate is disabled and no longer depends on the inputs but acts as a high impedance since both
transistor Q
3
and Q
4
are both cut off and the output is almost an open circuit. Thus the control input
can be thought as a switch which either permits the device to as a normal IC or disconnects its output
from the circuit. The logic symbol for a tri-state device is shown in the figure below.
Input
Enable
Output

2.4 Logic Gates
The table below shows the logic symbol and their truth table for the common TTL gates.
Operators AND NAND OR NOR XOR
TTL # 7408 7401 7432 7402
Symbols


A
B
Y

Truth Table
B A Y =
B A Y =
B A Y + =
B A Y + =
B A Y =
A B
0 0 0 1 0 1 0
0 1 0 1 1 0 1
1 0 0 1 1 0 1
1 1 1 0 1 0 0

- Three-State Outputs


A Y
C

A Y
C

Y
A
Off
=

,
,
if C is high
if C is low
Y
A
Off
=

,
,
if C is low
if C is high

74126 74125

Chapter 2 DIGITAL ELECTRONICS
Page: 40 2011, ME, NUS
2.4.1 Some Properties of NAND Gate
The NAND gate is the most versatile digital logic device. All of the Boolean logic gates we have
discussed can be constructed using only NAND gates. The logic diagrams below illustrate the NAND-
equivalence of various logic gates.
Single Gate NAND Equivalence
Inverter


AND

OR


NOR


Exclusive OR


Exclusive NOR Gate


2.4.2 Some combinatorial logic examples
2.4.2.1 Half Adder
We know from previous chapter that binary addition satisfy the
following condition:
Truth Table
A B S C
0 0 0 0
0 1 1 0
1 0 1 0
1 1 0 1
From the truth table above we can derive that the sum, S, and the carry, C, are as follows

B A C
B A B A B A S
=
= + =

2.4.2.2 Full Adder
Beside the input A and B, addition usually involves the carry forward from the lesser significant
position of the digit. Hence, the truth table of a full adder is as follows:
Cn-1 A B S Cn
0 0 0 0 0
0 0 1 1 0
0 1 0 1 0
0 1 1 0 1
1 0 0 1 0
1 0 1 0 1
1 1 0 0 1
1 1 0 1 1
Half Adder
A
B
C
S
ME3241/ME3241E Microprocessor and Applications
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From the truth table, we have
S =
1 1 1 1
+ + +
n n n n
C B A C B A C B A C B A
= ( ) ( )
1 1 1 1
+ + +
n n n n
C B C B A C B C B A
= ( ) ( )
1 1
+
n n
C B A C B A
=
1

n
C B A
Also,

n
C =
1 1 1 1
+ + +
n n n n
C B A C B A C B A C B A
= ( ) B A B A C B A
n
+ +
1

= ( ) B A C B A
n
+
1

Therefore, the full adder (FA) can be constructed from two half adder as shown below.

Full Adder
Half Adder
A
n
B
n
Half Adder
S
n
C
n-1
C
n

FA
B
C
-1
C
S
A


A 4-bit adder can be constructed by cascading 4 FAs as shown below.

FA
0
A B
C
-1
C
S
FA
1
A B
C
-1
C
S
FA
2
A B
C
-1
C
S
FA
3
A B
C
-1
C
S
Carry
S
0
S
1
S
2
S
3
B
0
B
1
B
2
B
3
A
3
A
2
A
1
A
0


Note:
The parallel adder above performs additions at a relatively high speed. However, its speed is limited
by an effect called carry propagation or carry ripple. The carry bits have to propagate from one stage
to the next. Hence, the output of each FA is therefore not stable until the carry-in from the previous
stage is calculated. Each output stabilize in the order from right to left as the carries ripple through the
chain. An commercial example of 4-bit adder is 74283.

2.5 Flip-flops and Latches
The logic gates discussed in earlier section are what we called as memory-less devices. Circuits
made out of these devices are usually called combinational logic.
In general, digital systems are made up of combinational circuits and memory elements as shown in
the diagram below. The circuit consists of inputs from external signals and feedback from the outputs
of the memory elements. Some of the outputs are stored in the memory elements which outputs are
feedback to the circuit.
An important memory element is the flip-flop (FF), which is made up of an assembly of logic gates.
The most basic FF circuit can be constructed from two NAND gates or two NOR gates. The NAND
Chapter 2 DIGITAL ELECTRONICS
Page: 42 2011, ME, NUS
gate version is called a NAND gate latch whereas the NOR gate version is called NOR gate latch.
This is sometime referred as latch or bi-stable multi-vibrator.
Combinational
logic gates
Memory
elements
Combinational
outputs
Memory outputs
External inputs


2.5.1 NAND gate Latch:
The figure below shows a NAND gate latch, in which, two NAND gates are cross-coupled so that the
output of one NAND gate is connected to the input of the NAND gate and vice versa. The table below
shows the truth table of the flip-flop. When both inputs SET and CLEAR are normally set at HIGH
such that the output Q retains its pre-stored value. The output can be set to HIGH or clear to LOW
by pulling the SET or CLEAR pin to LOW, respectively. Noting that both SET and CLEAR are
not allowed to be pulled to LOW simultaneously!

SET
Q
Q
CLEAR


Example1:
The waveform below shows how the output responses the pins SET and CLEAR .


Example2:
An application of the SC latch is to use it to prevent phenomena called the contact bounce.
V
OUT
+5V
1
2

Switch to
position 2
Switch come
to rest in
position 2
Bouncing
V
OUT
+5V
1
2
S
C
Q
+5V

Switch to
position 2
Switch back
to position 1


S E T CLEAR Q
1 1 No Change
0 1 1
1 0 0
0 0
Invalid!
Q = Q = 1
ME3241/ME3241E Microprocessor and Applications
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2.5.2 Clocked Flip-Flops:
Digital systems can operate either asynchronously or synchronously.
- Asynchronous systems: outputs can change state at any time.
- Synchronous systems: outputs state change determined by clock.
NGT
Clk
PGT
Time

In synchronous systems, the output changes its state by a signal called clock. It is a square pulse
train that is distributed to most part of the system such that the outputs change state only when the
clock makes a transition (also called edges). When the clock changes from 0 to 1, it is called a
Positive-going transition (PGT). Similarly, when the clock changes from 1 to 0 it is called a
Negative-going transition (NGT).
The Synchronizing action of the clock is accomplished by clocked flip-flops that are designed to
change states on one of the clock transition.
A typical clocked flip-flop consists of:
- clock input (CLK or CK or CP)
- two outputs usually termed as Q and Q where Q is also a complement of Q.
- one or more control inputs which have not have effect on Q until the flip-flop is clocked.
- 2 initialization input (to be discussed later) to momentarily change the state of Q.


Control
inputs
Clk
Q
Q
Init i/p

Control
inputs
Clk
Q
Q
Init i/p

PGT activated flip-flop NGT activated flip-flop

2.5.3 Making of Clocked S-C Flip-Flop
The NAND flip-flop in Section 2.5.1 does not have any enable/disable facilities. In order to have some
level of control when the inputs can controls the output Q, we add two more NAND gate at the input as
shown in the figure below.
SET
Q
Q
CLEAR
SET
E
CLEAR


*SET CLEAR
E/ D
Q
X X 0 No Change
0 0 1 No Change
0 1 1 0
1 0 1 1
1 1 1 Ambiguous

Chapter 2 DIGITAL ELECTRONICS
Page: 44 2011, ME, NUS
The input E acts like an enable/disable switch to control the inputs effect. Noting that when E is LOW,
both SET and CLEAR pins will be HIGH. From the truth table in Section 2.5.1, Q will remain
unchanged. On the other hand, when E is HIGH, then the state of pins SET and CLEAR will
depend on the value of pins SET and CLEAR. It behaves as if an inverter is appended to each of the
input SET and CLEAR . The Table above shows the behaviours of the modified flip-flop.
To acquire an edge-triggered flip-flop, we insert an edge detector before pin E as shown in the figure
below.

Clk
SET
Q
Q
CLEAR
SET
CLEAR
Edge
detector
Clk*

The figures below show the case for both PGT or NGT triggered edge detector.

CLK CLK
CLK*
CLK
CLK
CLK*

CLK CLK
CLK*
CLK
CLK
CLK*

Positive-going transition Negative-going transition

Positive Edge Triggered SC Flip-Flop
S
C
Q
Q




Asynchronous Inputs
Most clocked flip-flops also have one or more asynchronous inputs which operate independently of the
synchronous inputs and clock input.
These asynchronous inputs can be used to set the flip-flop to the HIGH state or clear the flip-flop to
the LOW state at any time regardless of the condition of the other inputs.
It is usually used to override the input to set or clear the flip-flop.
S C Clk Q
0 0 | Q
0

1 0 | 1
0 1 | 0
1 1 | Ambiguous

ME3241/ME3241E Microprocessor and Applications
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SC Flip-flop
Set
Clear
Q
Q
S
CLK
C

SET CLEAR Q
1 1 Clocked Mode
1 0 0
0 1 1
0 0 Not Allowed

2.5.4 Clocked J-K Flip-Flop
J
K
Q
Q

Positive edge going



J
K
Q
Q

Negative edge going


K
1
0
J
1
0
Clk
1
0
Q
1
0
a b c d e f

J K Clk Q
0 0 | Q0(no change)
1 0 | 1
0 1 | 0
1 1 |
Q
0
(toggles)
J K Clk Q
0 0 + Q
0
(no change)
1 0 + 1
0 1 + 0
1 1 +
Q
0
(toggles)
Chapter 2 DIGITAL ELECTRONICS
Page: 46 2011, ME, NUS
JK Flip-flop with Asynchronous Inputs
J
K
Q
Q
Preset
Clear


Example:
J
K
Q
Q
PRE
CLR
+5V


2.5.5 Clocked D Flip-Flop
D Q
Q


s

S
C
Q
Q
D
Clk
J
K
Q
Q
D
Clk

Equivalent D Flip-flop by SC Flip-Flop Equivalent D Flip-flop by JK Flip-Flop

Preset Clear
Q
1 1 Clocked mode
0 1 1
1 0 0
0 0 Not used
D Clk Q
0 | 0
1 | 1

ME3241/ME3241E Microprocessor and Applications
2011, ME, NUS Page: 47
2.5.6 D Latch (Transparent Latch)

D Q
Q EN

- The D Latch (74 373)
- A latch is a digital device that stores a 1 or a 0 on its output.
- The device functions as follows: (See the Truth Table above).
- if the enable input EN is low, the logic level present on the input will have no effect on the Q and Q
outputs.
- if the enable input is high, a high or a low on the D input will be passed to the Q output.
- when the enable input is made low again, the state on Q at that time will be latched there.


2.5.7 Timing Consideration for Flip-flop
- Setup and Hold Times
Synchronous
control input
Clock input
t
H
Hold time
t
s
Setup time

- Two timing requirements must be met if a clocked FF is to respond reliably to its control inputs when the
active CLK transition occurs.
- Setup time,
S
t , is the time interval immediately preceding the active transition of the CLK signal
during which the synchronous input has to be maintained at the proper level. (Usually specified in
S
t
(min)).
- Hold time,
H
t , is the time interval immediately following the active transition of the CLK signal
during which the synchronous input has to be maintained at the proper level. (Usually specified in
H
t (min)).
- Propagation Delay
- Whenever a signal is to change the state of a FFs output, there is a delay from the time
the signal is applied to the time when the output makes its change.
- Usually referred to as t
PLH
and t
PHL

- Maximum Clocking Frequency
- The highest frequency that may be applied to the CLK input of a FF.
- Usually referred to as f
MAX

- Clock Pulse HIGH and LOW Times
- The minimum time duration that the clock must remain LOW before it goes HIGH, t
W
(L)
- The minimum time duration that the clock must remain HIGH before it goes LOW, t
W
(H)
0
1
Clock
t
W
(H) t
W
(L)


EN D Q
0 X Q
0
(no change)
1 0 0
1 1 1
Chapter 2 DIGITAL ELECTRONICS
Page: 48 2011, ME, NUS
- Asynchronous Active Pulse Width
- The minimum time duration that a PRESET or CLEAR input has to be kept in its active
state in order to reliably set or clear the FF.
0
1
PRE
or
CLR
t
W
(L)

2.5.7.1 Some Flip-Flop Applications
1. Detecting an input Sequence
Suppose that we want to generate a high output only if A goes high and then B goes high sometime
later.
J
K
Q
Q
A
B
X

A
B
X

A
B
X

A goes HIGH before B A goes HIGH after B

2. Data Storage and Transfer

D A
A
D B
B
Transfer

K
Q
Q
K
K
Q
Q
K
Transfer
enable

Synchronous transfer Asynchronous transfer

D
Transfer
X
1
X
1
X
1
Y
1
Y
1
D Y
1
Y
1
D Y
1
Y
1

Parallel transfer
2.6 Counters and Registers
2.6.1 Registers
- A register is a device you use to store some information, in its simplest form, a flip-flop.


S
D Q
Clk Q
R
Write pulse
Storage
+5V
Input
Write pulse
Input
Storage Q

- However, one flip-flop can only store two possible values, i.e. a ONE or a ZERO.
- We usually group a few flip-flop to form one set of storage e.g.
- 1 nibble 4 bits
ME3241/ME3241E Microprocessor and Applications
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- 1 byte 8 bits
- The most commonly used group is byte (8 flip-flops).

Write
pulse
Storage
+5V
I
1
I
0
Input
S
D Q
Q
R
S
D Q
Q
R
S
D Q
Q
R
S
D Q
Q
R
S
D Q
Q
R
S
D Q
Q
R
S
D Q
Q
R
S
D Q
Q
R
I
3
I
2
I
5
I
4
I
7
I
6
Q
1
Q
0
Q
3
Q
2
Q
5
Q
4
Q
7
Q
6

2.6.1.1 Transferring of Registers content
- Parallel transfer of value in register A to Register B

Register B
Write Pulse
Register A
A
1
A
0
D A
3
A
3
A
2
D A
2
D A
1
D A
0
D B
3
D B
2
D B
1
D B
0
B
1
B
0
B
3
B
2


- Serial Transfer of value from Register A to Register B(Shift Register)
Register B
Register A
Write Pulse
D A
3
D A
2
D A
1
D A
0
D B
3
D B
2
D B
1
D B
0
B
1
B
0
B
3
B
2



- Asynchronous Shift Register



J
Q
Q
K
SET
CLR
Y
X
I3
J
Q
Q
K
SET
CLR
Y
X
I2
J
Q
Q
K
SET
CLR
X
I1
J
Q
Q
K
SET
CLR
Y
X
I0
Y
Stepping
Pulse
Parallel
Load
Serial
Input
Serial
Output
Chapter 2 DIGITAL ELECTRONICS
Page: 50 2011, ME, NUS
2.6.2 Counters
- We will consider asynchronous as well as synchronous counters.
- In asynchronous counters, circuit elements do not get the clock input simultaneously.
- In synchronous counters, circuit elements get the clock input simultaneously.

2.6.2.1 Asynchronous (Ripple) Counters

J
K
A
+5V
J
K
B
+5V
J
K
C
+5V
J
K
D
+5V

Clk
A
B
C
D

- FF outputs can only toggle.
- Clock connected to first (LSB) FF only. Succeeding FFs get their clock input from output of
previous FF.
- Each FF A, B, C, and D successively halves the clock input frequency.
- Counter counts in sequence from 0000 (0) 1111 (15)
- Counter has 16 distinct count states, and is called a mod-16 counter.
- In general, N-FFs connected up this way will have
2
N
states a mod-2
N
counter.

2.6.2.2 Counter with mod-X < 2
N

- Assume counter starts from 0.
- Find which FFs will be in HIGH state when count = X.
- Feed those FF outputs to a NAND gate.
- Connect NAND gate output to the asynchronous CLR input of all FFs.
- Example: A Mod-6 Counter
J
K
A
+5V
J
K
B
+5V
J
K
C
+5V
Clr Clr Clr
Clk
A
B
C
1 2 3 4 5 6 7 8 9 10 11 12
NAND

- More examples


J
K
A J
K
B J
K
C
Clr Clr Clr
J
K
D
Clr

J
K
A J
K
B J
K
C
Clr Clr Clr
J
K
D
Clr

Mod-14 Counter Mod-10 Counter

ME3241/ME3241E Microprocessor and Applications
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2.6.2.3 Ripple Counter that counts down.
- Connect complements of FF outputs to clock inputs of succeeding FFs.

J
K
A
+5V
J
K
B
+5V
J
K
C
+5V
J
K
D
+5V
A B C D


2.6.2.4 Problems in Ripple Counters.
Accumulation of Propagation Delay
- Ripple counters are easy to implement but have one major drawback:
- Cant operate beyond a limiting frequency. So, only used for low freq. applications.
- The limitation is due to the propagation delays of the FFs in the chain add up:
- Clock input to FF
1
: t
0
(clock transition time)
Clock input to FF
2
: t
0
+ t
pd

Clock input to FF
3
: t
0
+ 2 t
pd

..
Clock input to FF
n
: t
0
+ (n-1) t
pd

- This implies that the n
th
FF rather than changing state at t
0
it changes state at t
pd
.
- Hence t
clock
> n t
pd
or f
max
s
1
n t
pd

- The following waveform illustrate propagation delay of a Mod-8 Ripple Counter
A
1 2 3 4 5
Clk
B
C
1000ns
50ns
100ns
150ns

- Clock Period = 1 ms
- Propagation delay after NGT of the Clock Signal
t
pd
(Max) = 150ns << 1 ms --- OK

- Say, we increase the clock frequency to have Clock Period = 100 ns
A
1 2 3 4 5
Clk
B
C
100ns
50ns
100ns
150ns

- Note: There is no 100 in the counts!!!

Example:
A 4-bit ripple counter is constructed using the 74LS112 J-K flip-flop. From the spec., we have t
PLH

= 16 ns and t
PLH
= 24 ns. To calculate the maximum allowable clock frequency, we use the worst
case (i.e. t
pd
= 24ns)
f
max
s
1
n t
pd
=
1
4 x 24ns
= 10.4 MHz
Chapter 2 DIGITAL ELECTRONICS
Page: 52 2011, ME, NUS
Decoding Glitches
- This is another problem encountered with ripple counters if the states have to be decoded.
- Again due to propagation delays.
- Depending on application, may/may not be a relevant.
- Example

J
K
A J
K
B
A B
X
0
X
1
X
2
X
3
Clk

1
0
#1 #2 #3 #4
Clk
1
0
A
1
0
B
Temporay
00 state
Temporay
10 state
1
0
X
0
1
0
X
1
1
0
X
2
1
0
X
3

FF and decoding waveform for a mod-4 ripple Counter showing glitches at X0 and X2 outputs.

- These decoding glitches can be eliminated by a strobe signal.
X
0
A
B X
1
A
B X
2
A
B
X
3
A
B
Strobe
signal

1
0
#1 #2 #3 #4
Clk
1
0
Strobe
Decoder
disabled
t
D
Decoder enabled

- t
D
is chosen be greater than the total time it takes the counter to reach a stable count
(depends on FF delays and number of FFs).
- This method need not be used when the decoder drives a display
glitch is not visible.
- But must be used when decoder drives other circuitry.

2.6.2.5 IC Asynchronous Counters (74x293)
J
K
Q
1
1
C
D
J
K
Q
1
1
C
D
J
K
Q
1
1
C
D
J
K
Q
1
1
C
D
Q
1
Q
2
Q
3
(MSB)
Q
0
(LSB)
CP
0
CP
1
MR
1
MR
2

74293
Q
0
Q
1
Q
2
Q
3
MR
1
MR
2
CP
1
CP
0

- Consist of 4 JK flip-flops with output Q
0
, Q
1
, Q
2
and Q
3
(Q
0
is LSB and Q
3
is MSB)
- The clock inputs of Q
0
and Q
1
are externally accessible and labeled 0 CP and 1 CP ,
respectively.
- Each FF has an asynchronous CLEAR input, C
D
. These are connected together to the output
of a 2-input NAND gate with inputs MR
1
and MR
2

Need MR
1
= MR
2
= 1 to reset the counter to 0000.
- Q
1
, Q
2
and Q
3
are already connected as a 3-bit ripple counter. FF Q
0
is not connected to
anything internally. (Some flexibility here)


ME3241/ME3241E Microprocessor and Applications
2011, ME, NUS Page: 53
Example 1: Mod-16 Counter
74293
Q
0
Q
1
Q
2
Q
3
MR
1
MR
2
CP
1
CP
0

Example 2: Mod-10 Counter
74293
Q
0
Q
1
Q
2
Q
3
MR
1
MR
2
CP
1
CP
0


Example 3: Mod-50 Counter
74293
Q
0
Q
1
Q
2
Q
3
MR
1
MR
2
CP
1
CP
0
74293
Q
0
Q
1
Q
2
Q
3
MR
1
MR
2
CP
1
CP
0
Not
Used
f
in
/10
f
in
/50

2.6.2.6 Synchronous (Parallel Counters)
J
K
A J
K
B J
K
C J
K
D
Input

- The propagation delay problem encountered with ripple counters can be overcome by using
synchronous or parallel counters.
- The diagram above shows a MOD-16 parallel counter with "A" as the LSB and "D" as the MSB.
Noting that all clock inputs are triggered simultaneously.
- Technique used:
- When J=K=0, output does not change on the clock pulse
- When J=k=1, output toggles on the clock pulse.
- Notice that all FFs are triggered by the same clock.
- A toggles at every NGT (J,K=1).
- B toggles when A = 1.
- C toggles when AB = 1.
- D toggles when ABC = 1.
- The additional logic gates ensure that the FFs toggle at the right time.
- The total delay involved in this sync. counter is
t
pd
= t
pd
(FF) + t
pd
(AND)
- Hence counter operates at higher frequency than corresp. ripple counter.
Example:
If t
pd
(FF) = 50 ns. and t
pd
(AND) = 20 ns. What is the max operating frequency?
t
pd
(total) = 50 + 20 = 70 ns.
Hence,
t
clock
> 70 ns, i.e. f
max
<
1
70 ns
= 14.3 MHz (irrespective of no. of FFs).
On the other hand for a 4-bit ripple counter,
Chapter 2 DIGITAL ELECTRONICS
Page: 54 2011, ME, NUS
f
max
<
1
4 x 50 ns
= 5 MHz.

2.6.2.7 Synchronous Down and Up Counters
J
K
Q
Q
A
J
K
Q
Q
B
Count
Up/
Down
J
K
Q
Q
C
Input

C B A
7 1 1 1
6 1 1 0
5 1 0 1
4 1 0 0
3 0 1 1
2 0 1 0
1 0 0 1
0 0 0 0
- When Counting up
- A = 1 to toggle B
- A = B = 1 to toggle C
- When Counting down
- A = 0 to toggle B
- A = B = 0 to toggle C
- The Count-up and Count-down signal control the counting sequence.
- Count sequence is up if Count Up/ Down input = 1.
- Here, J(A) = K(A) = 1, J(B) = K(B) = A and J(C) = K(C) = A.B.
- Count sequence is down if Count Up/ Down input = 0.
- Here, J(A) = K(A) = 1, J(B) = K(B) = A and J(C) = K(C) = A . B .

2.6.2.8 Presettable Counters
- Many synchronous counters that are available as ICs are designed to be presettable
- Can be pre-set to any desired count asynchronously or synchronously.
- Sometime referred as loading the counter.
Clock
J
K
Q
A
Clr
Pre J
K
Q
B
Clr
Pre J
K
Q
C
Clr
Pre
P
2
P
1
P
0 PL


ME3241/ME3241E Microprocessor and Applications
2011, ME, NUS Page: 55
2.6.2.9 IC Presettable Counter (74x193)
P
1
P
2
P
3
P
0
PL
74193
Mod-16 up/down
counter
Q
0
Q
1
Q
2
Q
3
MR
+
-
TC
U
TC
D
CP
U
CP
D

- Pin Description
- CP
U
Count-up clock input (active rising edge)
- CP
D
Count-down clock input (active rising edge)
- MR Asynchronous master reset input (active HIGH)
- PL - Asynchronous parallel load input (active LOW)
- P
0
-P
3
Parallel data inputs
- Q
0
-Q
3
flip-flop outputs
- TC
U
Terminal count-up (carry) output (active LOW)
- TC
D
Terminal count-down (borrow) output (active LOW)

Example1: Up-counter
- Parallel data inputs = 1011
- Initial flip-flops output = 0000
1 0 1 1 PL
74193
+
-
TC
U
TC
D
CP
U
CP
D
P
0
P
1
P
2
P
3
PL
Q
0
Q
1
Q
2
Q
3
MR
1

1
0
CP
U
1
0
PL
1
0
MR
1
0
Q
0
1
0
Q
1
1
0
Q
2
1
0
Q
3
1
0
TC
U
t
0
t
1
t
2
t
3
t
4
t
5
t
6
t
7
t
8
t
9
t
10


MR
PL
CP
U
CP
D
Mode
H X X X Asyn. reset
L L X X Asyn. preset
L H H H No change
L H | H Count up
L H H | Count down

Chapter 2 DIGITAL ELECTRONICS
Page: 56 2011, ME, NUS
Example2: Down-counter
1 1 0 1 PL
74193
+
-
TC
U
TC
D
CP
U
CP
D
P
0
P
1
P
2
P
3
PL
Q
0
Q
1
Q
2
Q
3
MR
1

1
0
CP
D
1
0
PL
1
0
Q
0
1
0
Q
1
1
0
Q
2
1
0
Q
3
1
0
TC
D
t
0
t
1
t
2
t
3
t
4
t
5
t
6
t
7
t
8
t
9
t
10


2.6.2.10 Synchronous Counter Design
- A subset of Sequential Circuit Design
- Approach:
Given the state diagram of a counter realize it using common FFs and combinational logic.
Combinational
Logic
FFs
E
x
t
e
r
n
a
l
I
n
p
u
t
Clk

- All FFs are clocked at the same time.
- Must make sure the logic level at every FFs input pins stabilize to a correct level before each
clock pulse.
- Choices of flip-flops

Transition
JK Flip-flop D Flip-flop
J K D
00 0 X 0
01 1 X 1
10 X 1 0
11 X 0 1

- Design Steps
1. Determine the desired number of bits and choice of FF used.
2. Draw the state transition diagram showing all possible states.
3. Use the state transition diagram to set up a table that list all PRESENT states and their
NEXT states
4. Add the column to this table for each flip-flop input.
5. Design the logic circuits to generate the levels required at each flip-flop input.

ME3241/ME3241E Microprocessor and Applications
2011, ME, NUS Page: 57
- Example 1:
Design a 3-bit counter that counts from 000 to 111 and back to 000.
- Step 1: Since it is 3 bit counter, we need 3 flip-flops. Say, use D flip-flops.
- Step 2: State transition diagram.
000
010 110
100
101 011
001 111

- Step 3&4: Generate the truth table
Present State Next State Flip-Flops
Q2 Q1 Q0 Q2 Q1 Q0 D2 D1 D0
0 0 0 0 0 1 0 0 1
0 0 1 0 1 0 0 1 0
0 1 0 0 1 1 0 1 1
0 1 1 1 0 0 1 0 0
1 0 0 1 0 1 1 0 1
1 0 1 1 1 0 1 1 0
1 1 0 1 1 1 1 1 1
1 1 1 0 0 0 0 0 0


- Step 5: Logic Design flip-flops.
D0 = Q2 . Q1 . Q0 + Q2 .Q1. Q0 + Q2. Q1 . Q0 + Q2.Q1. Q0
= Q2 . Q0 + Q2. Q0 = Q0
D1 = Q2 . Q1 .Q0 + Q2 .Q1. Q0 + Q2. Q1 .Q0 + Q2.Q1. Q0
= Q2 .( Q1 .Q0 + Q1. Q0 ) + Q2.( Q1 .Q0 + Q1. Q0 )
= ( Q1 .Q0 + Q1. Q0 ) = Q1 Q0
D2 = Q2 .Q1.Q0 + Q2. Q1 .Q0 + Q2. Q1 . Q0 + Q2.Q1. Q0
= Q2 .Q1.Q0 + Q2. Q1 .(Q0 + Q0 ) + Q2.( Q1 + Q1). Q0
= Q2 .Q1.Q0 + Q2. Q1 + Q2. Q0

Combinational Logic
D Q
2
Q
2
D Q
1
Q
1
D Q
0
Q
0
Q
2
Q
1
Q
0
Clk



Homework: Repeat this with JK flip-flops.
Chapter 2 DIGITAL ELECTRONICS
Page: 58 2011, ME, NUS
Example 2:
Design a 3-bit counter that counts from 000001010011100000
- Step 1: Since it is 3 bit counter, we need 3 flip-flops. Say, use JK flip-flops.
- Step 2: State transition diagram.
000
010
100
011
001

Note: There undefined states like 101, 110 and 111
- Step 3&4: Generate the truth table
Present State Next State Flip-Flops
Q2 Q1 Q0 Q2 Q1 Q0 J2 K2 J1 K1 J0 K0
0 0 0 0 0 1 0 X 0 X 1 X
0 0 1 0 1 0 0 X 1 X X 1
0 1 0 0 1 1 0 X X 0 1 X
0 1 1 1 0 0 1 X X 1 X 1
1 0 0 0 0 0 X 1 0 X 0 X
1 0 1 X X X X X X X X X
1 1 0 X X X X X X X X X
1 1 1 X X X X X X X X X
- Step 5: Logic Design flip-flops.
For J0.
Present State Flip-Flops
Q2 Q1 Q0 J0
0 0 0 1
0 0 1 X
0 1 0 1
0 1 1 X
1 0 0 0
1 0 1 X
1 1 0 X
1 1 1 X
J0 = Q2
For K0, it can be seen from the table above that K0= 1.
Similarly, for J1, K1, J2 and K2, we have













J0 Q0 Q0
Q2 . Q1 1 X
Q2. Q1 0 X
Q2.Q1 X X
Q2 .Q1 1 X
J1 Q0 Q0
Q2 . Q1 0 1
Q2. Q1 0 X
Q2.Q1 X X
Q2 .Q1 X X
J1 = Q0
K1 Q0 Q0
Q2 . Q1 X X
Q2. Q1 X X
Q2.Q1 X X
Q2 .Q1 0 1
K1 = Q0
J2 Q0 Q0
Q2 . Q1 0 0
Q2. Q1 X X
Q2.Q1 X X
Q2 .Q1 0 1
J2 = Q1.Q0
K2 Q0 Q0
Q2 . Q1 X X
Q2. Q1 1 X
Q2.Q1 X X
Q2 .Q1 X X
K2 = 1
ME3241/ME3241E Microprocessor and Applications
2011, ME, NUS Page: 59
Therefore,
J0 = Q2 , K0 = 1
J1 = K1 = Q0
J2 = Q1.Q0, K2 =1
J Q
Q
2
K
J Q
Q
1
K
J Q
Q
0
K
Q
0
Q
1
Q
2
1
1
Clk


2.6.2.11 Synchronous vs. asynchronous circuit designs
- Sync. operations generally preferred to async. operations, since latter require great care to
address problems such as
- Races due to unequal path delays.
- Transients and glitches which can cause incorrect operation.
- Output changes that depend on order of async. input changes.
- Synchronous circuits bypass these problems by use of the clock which allows outputs to
change only at discrete time instants.
- This allows time for transients and glitches to settle down, races to be resolved etc.

2.6.2.12 Counter Applications: Digital Clock

Pulse
shaper
Mod-50
Counter
Mod-2 Mod-10 Mod-6 Mod-10 Mod-6 Mod-10
Decoder/
Display
Decoder/
Display
Decoder/
Display
Decoder/
Display
Decoder/
Display
Decoder/
Display
50 Hz
Main
50 pps 1 pps
"Seconds"
section
0-9
Units
0-9
Units
0-9
Units
0-5
Tens
0-5
Tens
0-1
Tens
"Minutes"
section
"Hours" section

- Pulse shaper can be constructed by a transformer and a schmitt trigger
- Mod-50 Counter can be constructed by a mod-10 counter cascading a mod-5 counter.
- Mod-10 and Mod-6 Counters can be constructed by either a BCD counter or any 16-bit
counter with reset capability.
- Mod-2 Counter can be constructed by just a JK flip-flop.
- Decoder/Display units can be constructed by a BCD to 7-segment display decoder (see
tutorial) and a 7-segment display LED.

2.6.2.13 Other Counters
Register Based Counters - Ring Counter
- A circulating arrangement where a single 1 moves from FF to FF.
- In most instances, only a single 1 circulates.
Chapter 2 DIGITAL ELECTRONICS
Page: 60 2011, ME, NUS
- Counter is initialized by presetting a 1 into one FF and clearing the rest.
- Mod-N counter needs N FFs (more hardware than other counters for same mod-#).
- N FFs mod-N counter.
- On the other hand, this counter does not need any decoding gates at all (saving).
- Example:
A Mod-4 ring counter consists of 4 flip-flops.
0001
0010
0100
1000
D Q
Q
d
D Q
Q
c
D Q
Q
b
D Q
Q
a

0
1
0
1
0
1
0
1
Clk
Q
d
Q
c
Q
b
Q
a

2.7 Encoders, Decoders
2.7.1 Decoders
2.7.1.1 3-8 Decoders
- A decoder is a circuit element that will decode an N-bit code.
- It activates an appropriate output line as a function of the applied N-bit input code.
- Example: a 3-8 decoder.

A2 A1 A0 O0 O1 O2 O3 O4 O5 O6 O7
0 0 0 1 0 0 0 0 0 0 0
0 0 1 0 1 0 0 0 0 0 0
0 1 0 0 0 1 0 0 0 0 0
0 1 1 0 0 0 1 0 0 0 0
1 0 0 0 0 0 0 1 0 0 0
1 0 1 0 0 0 0 0 1 0 0
1 1 0 0 0 0 0 0 0 1 0
1 1 1 0 0 0 0 0 0 0 1

A
0
A
1
A
2
O
0
O
1
O
2
O
3
O
4
O
5
O
6
O
7

- A decoder can have up to 2
N
output lines for N inputs.
- MSI decoders are available as 2-4, 3-8, 4-10 decoders, etc.
- Example: The 74138 decoder 3-8 decoder.

ME3241/ME3241E Microprocessor and Applications
2011, ME, NUS Page: 61
74138
1-of-8 decoder
A
0
A
1
A
2
O
0
1 2 3
E
O
1
O
2
O
3
O
4
O
5
O
6
O
7
E
1
E
3
E
2

1 2 3
E
1
E
3
E
2
A
2
A
0
A
1
O
0
O
1
O
2
O
3
O
4
O
5
O
6
O
7

- It has NAND gate output, i.e. active low.
- The decoder can be enabled/disabled by the input pins
1
E ,
2
E and
3
E .
- The chip is enable only when
1
E =
2
E =0 and
3
E = 1.
- The enable pins allow multiple chip to be used together for higher bit decoding.

- Example:
Use 4 74138 decoders to set up a 1-32 decoder.
74138
A
0
A
1
A
2
1 2 3
E
0 1 2 3 4 5 6 7
74138
A
0
A
1
A
2
1 2 3
E
0 1 2 3 4 5 6 7
74138
A
0
A
1
A
2
1 2 3
E
0 1 2 3 4 5 6 7
74138
A
0
A
1
A
2
1 2 3
E
0 1 2 3 4 5 6 7
A
0
A
1
A
2
A
3
A
4
O
0
- - - - - - -O
7
O
8
-- - - - - - O
15
O
16
-- - - - -- O
23
O
24
-- - - - -- O
31





E
1
E
2
E
3

Output
0 0 1 Respond to input code A
2
A
1
A
0

1 X X Diabled all HIGH
X 1 X Diabled all HIGH
X X 0 Diabled all HIGH
Chapter 2 DIGITAL ELECTRONICS
Page: 62 2011, ME, NUS
a
b
c
d
e
f
g
2.7.1.2 BCD-to-Decimal Decoder


- Used whenever an output or group of outputs is to be activated only on the occurrence of a
specific combination of input levels.
- Commercially available decoders are
- 7442 BCD-to-decimal decoder, or
- 7445 BCD-to-decimal decoder/driver (Open collector version)

- Example:
Design a circuit which consists of 5 LEDs arranged in a line such that these LED will lights up in
the following sequence.
L1 ON for 1 s and OFF for 1s,
L2 ON for 1 s and OFF for 1s,
L3 ON for 1 s and OFF for 1s,
L4 ON for 1 s and OFF for 1s, and
L5 ON for 1 s and OFF for 7s.
After that L1 start again and repeat
itself.
Solution:


2.7.1.3 BCD to 7 Segment decoder
- Converts a BCD number into signals required to display that number on a 7-
segment display.
- 7-segment displays are of 2 types:
- common anode - all LED anodes connected active low
- common cathode - all LED cathodes connected active High.
- Each segment is an LED which will light when a logic T signal is applied to it.

Commercial BCD to 7 Segment decoder - 7447
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15


7447
BCD
to
7 Seg
D
C
B
A
LT
a
RBI RBO
b
c
d
e
f
g
Active LOW
ME3241/ME3241E Microprocessor and Applications
2011, ME, NUS Page: 63
Func Input BI/
RBO
Output
LT RBI D C B A a b c d e f G
0 1 1 0 0 0 0 1 0 0 0 0 0 0 1
1 1 X 0 0 0 1 1 1 0 0 1 1 1 1
2 1 X 0 0 1 0 1 0 0 1 0 0 1 0
3 1 X 0 0 1 1 1 0 0 0 0 1 1 0
4 1 X 0 1 0 0 1 1 0 0 1 1 0 0
5 1 X 0 1 0 1 1 0 1 0 0 1 0 0
6 1 X 0 1 1 0 1 1 1 0 0 0 0 0
7 1 X 0 1 1 1 1 0 0 0 1 1 1 1
8 1 X 1 0 0 0 1 0 0 0 0 0 0 0
9 1 X 1 0 0 1 1 0 0 0 1 1 0 0
10 1 X 1 0 1 0 1 1 1 1 0 0 1 0
11 1 X 1 0 1 1 1 1 1 0 0 1 1 0
12 1 X 1 1 0 0 1 1 0 1 1 1 0 0
13 1 X 1 1 0 1 1 0 1 1 0 1 0 0
14 1 X 1 1 1 0 1 1 1 1 0 0 0 0
15 1 X 1 1 1 1 1 1 1 1 1 1 1 1
BI X X X X X X 0 1 1 1 1 1 1 1
RBI 1 0 0 0 0 0 0 1 1 1 1 1 1 1
LT 0 X X X X X 1 0 0 0 0 0 0 0

Commercial BCD to 7 Segment decoder - 7448
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

7448
BCD-
to-
7Seg
a
b
c
d
e
f
g
RBO RBI
A
B
C
D
LT

Active HIGH
Func Input BI/
RBO
Output
LT RBI D C B A a b c d e f G
0 1 1 0 0 0 0 1 1 1 1 1 1 1 0
1 1 X 0 0 0 1 1 0 1 1 0 0 0 0
2 1 X 0 0 1 0 1 1 1 0 1 1 0 1
3 1 X 0 0 1 1 1 1 1 1 1 0 0 1
4 1 X 0 1 0 0 1 0 1 1 0 0 1 1
5 1 X 0 1 0 1 1 1 0 1 1 0 1 1
6 1 X 0 1 1 0 1 0 0 1 1 1 1 1
7 1 X 0 1 1 1 1 1 1 1 0 0 0 0
8 1 X 1 0 0 0 1 1 1 1 1 1 1 1
9 1 X 1 0 0 1 1 1 1 1 0 0 1 1
10 1 X 1 0 1 0 1 0 0 0 1 1 0 1
11 1 X 1 0 1 1 1 0 0 1 1 0 0 1
12 1 X 1 1 0 0 1 0 1 0 0 0 1 1
13 1 X 1 1 0 1 1 1 0 0 1 0 1 1
14 1 X 1 1 1 0 1 0 0 0 1 1 1 1
15 1 X 1 1 1 1 1 0 0 0 0 0 0 0
BI X X X X X X 0 0 0 0 0 0 0 0
RBI 1 0 0 0 0 0 0 0 0 0 0 0 0 0
LT 0 X X X X X 1 1 1 1 1 1 1 1


Chapter 2 DIGITAL ELECTRONICS
Page: 64 2011, ME, NUS
- Uses of RBO and RBI

2.7.2 Encoders
- Perform the inverse of the decoding function.
- For N different inputs, an encoder is a circuit element that generates an M-bit binary code
(2
M
> N) that uniquely identifies the input.
- Example: An 8-3 encoder.
O
0
O
1
O
2
A
0
A
1
A
2
A
3
A
4
A
5
A
6
A
7

0
A
1
A
2
A
3
A
4
A
5
A
6
A
7
A O2 O1 O0
X 1 1 1 1 1 1 1 0 0 0
X 0 1 1 1 1 1 1 0 0 1
X 1 0 1 1 1 1 1 0 1 0
X 1 1 0 1 1 1 1 0 1 1
X 1 1 1 0 1 1 1 1 0 0
X 1 1 1 1 0 1 1 1 0 1
X 1 1 1 1 1 0 1 1 1 0
X 1 1 1 1 1 1 0 1 1 1
- Commercial Decimal to BCD Priority encoder

A
1
A
2
A
3
A
4
A
5
A
6
A
7
A
8
A
9
74147
Decimal
to-BCD
priority
encoder
O
1
O
2
O
3
O
0
Inverted
BCD
I
n
p
u
t
s


1
A
2
A
3
A
4
A
5
A
6
A
7
A
8
A
9
A O3 O2 O1 O0
1 1 1 1 1 1 1 1 1 1 1 1 1
X X X X X X X X 0 0 1 1 0
X X X X X X X 0 1 0 1 1 1
X X X X X X 0 1 1 1 0 0 0
X X X X X 0 1 1 1 1 0 0 1
X X X X 0 1 1 1 1 1 0 1 0
X X X 0 1 1 1 1 1 1 0 1 1
X X 0 1 1 1 1 1 1 1 1 0 0
X 0 1 1 1 1 1 1 1 1 1 0 1
0 1 1 1 1 1 1 1 1 1 1 1 0


ME3241/ME3241E Microprocessor and Applications
2011, ME, NUS Page: 65
2.8 Multiplexers & demultiplexers
2.8.1 Multiplexers
I
0
I
1
I
2
I
3
Output
Z
S
0
S
1

I
0
Z
I
1
I
2
I
3
S
0
S
1

- A multiplexer (MUX) is a combinational circuit element that selects data from one of many
inputs and directs it to a single output.
- Example: A 4-input multiplexer
S
1
S
0
Output
0 0 Z = I
0

0 1 Z = I
1

1 0 Z = I
2

1 1 Z = I
3


- Comercial 8-input multiplexer (74151)
- Multiplexer has an ENABLE which is active-low
- When E=0, the select inputs S
2
S
1
S
0
will select one data input (I0~I7) for passage to
output Z.
- When E=1, multiplexer is disabled.
- Both normal and inverted output are provided


E
S2 S1 S0
Z
Z
1 X X X 1 0
0 0 0 0
0
I I0
0 0 0 1
1
I I1
0 0 1 0
2
I I2
0 0 1 1
3
I I3
0 1 0 0
4
I I4
0 1 0 1
5
I I5
0 1 1 0
6
I I6
0 1 1 1
7
I I7
74151 MUX
I
7
I
6
I
5
I
4
I
3
I
2
I
1
I
0
S
0
E
Z Z
S
2
S
1
Chapter 2 DIGITAL ELECTRONICS
Page: 66 2011, ME, NUS
- Commercial Quad Two-input MUX (74157)

S Za Zb Zc Zd
1 X 0 0 0 0
0 0 I
0a
I
0b
I
0c
I
0d

0 1 I
1a
I
1b
I
1c
I
1d


S
E
I
1a
I
1b
I
1c
I
1d
I
0a
I
0b
I
0c
I
0d
Z
a
Z
b
Z
c
Z
d


2.8.2 Multiplexer Applications
- Logic Function Generation
Truth Table
C B A Z
0 0 0 0
0 0 1 1
0 1 0 1
0 1 1 0
1 0 0 0
1 0 1 0
1 1 0 0
1 1 1 1

- Operation Sequencing




74151 MUX
I
0
I
1
I
3
I
4
I
5
I
6
I
2
I
7
S
0
S
1
S
2
E
Z
1KO
74157
Quad 2 input MUX
I0d I0c I0b I0a I1d I1c I1b I1a
S
E
Z
d
Z
c
Z
b
Z
a
ME3241/ME3241E Microprocessor and Applications
2011, ME, NUS Page: 67
- Data Routing
7447
BCD to 7 Seg
Decoder/Driver
7-Segment
Display
Units
7447
BCD to 7 Seg
Decoder/Driver
7-Segment
Display
Tens
74157
MUX
E
S
I
1
I
0
Za Zb Zc Zd
74157
MUX
E
S
I
1
I
0
Za Zb Zc Zd
Select
BCD
Counter
BCD
Counter
BCD
Counter
BCD
Counter
Counter 1 Counter 2
Tens Tens Units Units
Clk #1 Clk #2
(Tens)
(Units)


2.8.3 Demultiplexers
- Demultiplexer takes a single input and distributes it over several outputs.
- The select input code determines to which output the DATA input will be transmitted.
O
0
DEMUX
O
1
O
2
O
3
Data
input
S
0
S
1

- 1-line-to-8-line Demultiplexer
Select Outputs
S2 S1 S0 O7 O6 O5 O4 O3 O2 O1 O0
0 0 0 0 0 0 0 0 0 0 D
0 0 1 0 0 0 0 0 0 D 0
0 1 0 0 0 0 0 0 D 0 0
0 1 1 0 0 0 0 D 0 0 0
1 0 0 0 0 0 D 0 0 0 0
1 0 1 0 0 D 0 0 0 0 0
1 1 0 0 D 0 0 0 0 0 0
1 1 1 D 0 0 0 0 0 0 0

S
0
S
1
S
2
Data
O
0
O
1
O
2
O
3
O
4
O
5
O
6
O
7

Chapter 2 DIGITAL ELECTRONICS
Page: 68 2011, ME, NUS
- 74138 decoder as a demultiplexer
- Use the enable input E
1
as the data input I.
74138
1-of-8 decoder
A
0
A
1
A
2
O
0
1 2 3
E
O
1
O
2
O
3
O
4
O
5
O
6
O
7
E
1
E
3
E
2

2.8.4 Demultiplexer Applications
- Security Monitoring System

330 O
+5 V
Mod-8
Counter
Q
2
Q
1
Q
0
door 7 door 6
door 0
+5 V
+5 V
+5 V
74LS151
MUX
S
2
S
1
S
0
E
I
0
I
6
I
1
I
2
I
3
I
4
I
5
I
7
Z
74LS138
DEMUX
O
0
O
1
O
2
O
3
O
4
O
5
O
6
O
7
A
2
A
1
A
0
1
2
3
Clock
+5 V





2011, ME, NUS Page: 69
Chapt er 3 Microprocessor Architecture
3.1 Making of a microprocessor
3.1.1 Registers, ROMs, Rams and Buses
3.1.1.1 Register
- A register is a device you use to store some information, in its simplest form, a flip-flop.
S
D Q
Clk Q
R
Write pulse
Storage
+5V
Input

Write pulse
Input
Storage Q

o However, one flip-flop can only store two possible values, i.e. a ONE or a ZERO.
o We usually group a few flip-flop to form one set of storage e.g.
o 1 nibble 4 bits
o 1 byte 8 bits
o 1 word 16 bits.
- The most commonly used group is byte (8 flip-flops).
Q
Q
SET
CLR
D
Q
Q
SET
CLR
D
Q
Q
SET
CLR
D
Q
Q
SET
CLR
D
Q
Q
SET
CLR
D
Q
Q
SET
CLR
D
Q
Q
SET
CLR
D
Q
Q
SET
CLR
D
I
7
I
6
I
5
I
4
I
3
I
2
I
1
I
0
O
7
O
6
O
5
O
4
O
3
O
2
O
1
O
0
Write
Pulse

- However, we sometime wish to share the input and output line together. This can be achieved by the use
of a D Latch as such.
Q
Q
D
L
R/W
CE
Data

CE R/ W
Data
1 X Not connected
0 0 Writing data to memory
0 1 Reading from memory
- Cascading four of these latches form a nibble of register.
Q
Q
D
L
R/W
CE
Q
Q
D
L
Q
Q
D
L
Q
Q
D
L
Q
0
Q
1
Q
2
Q
3

- To transfer data between Register A & B
Q
Q
D
L R/W
a
CE
a
Q
Q
D
L
Q
Q
D
L
Q
Q
D
L
A
0
A
1
A
2
A
3
Reg A
Q
Q
D
L
R/W
b
CE
b
Q
Q
D
L
Q
Q
D
L
Q
Q
D
L
B
0
B
1
B
2
B
3
Reg B

- Transferring between accumulator and two other registers
Chapter 3 Microprocessor Architecture
Page: 70 2011, ME, NUS
Acc
R/W
CE
D
3
. . D
0
Reg X
R/W
CE
D
3
. . D
0
Reg Y
R/W
CE
D
3
. . D
0
Read/
Write
X/Y

- Transferring many to one
2-to-4 Decoder
Acc
R/W
CE
D
3
. . D
0
Read/
Write
R/W
CE
D
3
. . D
0
R/W
CE
D
3
. . D
0
R/W
CE
D
3
. . D
0
R/W
CE
D
3
. . D
0
0
1
2
3
A
0
A
1


- A 4-Nibble RAM
R/W
CE
D
0
D
3
R/W
CE
D
0
D
3
R/W
CE
D
0
D
3
R/W
CE
D
0
D
3
Decoder
A
0
D
0
D
3
A
1
D
a
t
a
D
0
D
3
A
0
A
1
R/W
CE


3.1.1.2 RAM
- As illustrated in previous section, we have constructed a very small size 4-nibble RAM.
- Acronym for random access memory, a type of computer memory that can be accessed
randomly; that is, any byte of memory can be accessed without touching the preceding
bytes.
- Most common type of memory found in computers and other devices, such as printers.
- It usually consists of the following pins
- READ/ WRITE to control read/write status of the memory
- A
0
~A
n
to select a specific memory cell
- D
0
-D
7
to read/write the actual data
- CE to enable or disable the chip.

- Also now as volatile memory, meaning that they lose their contents when the power is
turned off.
- There are two basic types of RAM (based on different technology):
- dynamic RAM (DRAM)
4 K
RAM
A
0
A
11
D
0
D
7
C
E
R
/
W
NUS Logo Microprocessor Architecture
2011, ME, NUS Page: 71
- Needs to be refreshed.
- More commonly used
- Some variance of DRAMs are:
- EDO DRAM - a type of DRAM that is faster than conventional DRAM. Unlike
conventional DRAM which can only access one block of data at a time, EDO
RAM can start fetching the next block of memory at the same time that it sends
the previous block to the CPU.
- BEDO DRAM (Burst EDO DRAM) - a new type of EDO DRAM that can
process four memory addresses in one burst.
- SDRAM (Synchronous DRAM) - a new type of DRAM that can run at much
higher clock speeds than conventional memory. SDRAM actually synchronizes
itself with the CPU's bus and is capable of running at about twice as fast EDO
DRAM and BEDO DRAM. SDRAM is replacing EDO DRAM in many newer
computers
- RDRAM (Rambus DRAM) - a type of memory (DRAM) developed by Rambus,
Inc. Faster than SDRAM (600 MHz).
Being used in place of VRAM in some graphics accelerator boards.
Intel and Rambus are also working a new version of RDRAM, called nDRAM,
that will support data transfer speeds at up to 1,600 MHz.
- static RAM (SRAM)
- Static RAM does not need to be refreshed, which makes it faster;
- More expensive than dynamic RAM.

3.1.1.3 ROM
- Acronym for read-only memory
- Computer memory on which data has been prerecorded. Once data has been written onto a
ROM chip, it cannot be removed and can only be read.
- Unlike RAM, ROM retains its contents even when the computer is turned off. ROM is
referred to as being nonvolatile, whereas RAM is volatile.
- It usually consists of the following pins
- A
0
~A
n
to select a specific memory cell
- D
0
-D
7
to read the actual data
- CE to enable or disable the chip.
- PCs usually contain ROM that stores critical programs such as the program that boots the
computer. (e.g. BIOS in your IBM compatible PC)
- Also used extensively in calculators and peripheral devices such as laser printers, whose
fonts are often stored in ROMs.
- Variation of a ROM are
- PROM (programmable read-only memory).
- PROMs are manufactured as blank chips on which data can be written with a special
device called a PROM programmer.
- Can be written to only once
- EPROM (erasable programmable read-only memory)
- A special type of memory that retains its contents until it is exposed to ultraviolet
light.
- The ultraviolet light clears its contents, making it possible to reprogram the
memory.
- To write to and erase an EPROM, you need a special device called a PROM
programmer or PROM burner.
- EEPROM (electrically erasable programmable read-only memory)
- A special type of PROM that can be erased by exposing it to an electrical charge.
Like other types of PROM, EEPROM retains its contents even when the power is
turned off. Also, like other types of ROM, EEPROM is not as fast as RAM.




16 K
ROM
A
0
A
13
D
0
D
7
C
E
Chapter 3 Microprocessor Architecture
Page: 72 2011, ME, NUS
3.1.1.4 Concepts of bus
- Some Bus Example
4 nibble RAM
D
0
D
3
A
0
A
1 R/W CE
4 nibble RAM
D
0
D
3
A
0
A
1 R/W CE
4 nibble RAM
D
0
D
3
A
0
A
1 R/W CE
4 nibble RAM
D
0
D
3
A
0
A
1 R/W CE
MicroP
D
0
D
3
A
0
A
3 R/W CE
Decoder
Data Bus
Address Bus
Control Bus


3.1.2 Digital Arithmetic Circuits
- From previous chapter, we have constructed a full adder
A
B
S
C
n-1
C
n

FA
B
C
-1
C
S
A


- 4-Bit Adder
4 Bit Adder
FA
B
C
-1
C
S
A
FA
B
C
-1
C
S
A
FA
B
C
-1
C
S
A
FA
B
C
-1
C
S
A
A
3
A
2
A
1
A
0
B
3
B
2
B
1
B
0
S
3
S
2
S
1
S
0
C
0
C
4

- Addition with Registers
4 Bit Adder S
0
S
3
C
4
C
0
Reg A
Q
0
Q
3
Reg B
Q
0
Q
3
Temp
Q
0
Q
3
Clk
Tri-States






NUS Logo Microprocessor Architecture
2011, ME, NUS Page: 73
- Parallel Add/Subtract using 2s complement
4 Bit Adder S
0
S
3
C
4
C
0
Reg A
Q
0
Q
3
Reg B
Q
0
Q
3
Temp
Q
0
Q
3
Clk
Tri-States
Q
0
Q
1
Q
1
Q
2
Q
2
Q
3
Add/
Subtract

3.1.3 A Very Simple microprocessor
Microprocessor
Accumulaor Tmp Reg 1
Arithmetic Unit
Add/
Subtract
Tmp Reg 2
Internal Data Bus
Tri-state Buf
Data Bus
Instr Regs
Instr
Decoder
Address
Register
Address Bus
RAM ROM PIO
External I/O
Control Bus

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