21st International Conference on VLSI Design

A Novel Approach to Design BCD Adder and Carry Skip BCD Adder
Ashis Kumer Biswas, Md. Mahmudul Hasan, Moshaddek Hasan, Ahsan Raja Chowdhury and Hafiz Md. Hasan Babu
Department of Computer Science and Engineering, University of Dhaka, Dhaka-1000, Bangladesh. E-mails: ashis.csedu@gmail.com, nayeem81@gmail.com, moshaddekhasan@yahoo.com farhan717@yahoo.com, hafizbabu@hotmail.com

Abstract
Reversible logic has become one of the most promising research areas in the past few decades and has found its applications in several technologies; such as low power CMOS, nanocomputing and optical computing. This paper presents improved and efficient reversible logic implementations for Binary Coded Decimal (BCD) adder as well as Carry Skip BCD adder. It has been shown that the modified designs outperform the existing ones in terms of number of gates, number of garbage output and delay.

1. Introduction
The advancement in higher-level integration and fabrication process has emerged in better logic circuits and energy loss has also been dramatically reduced over the last decades. This trend of reduction of heat in computation also has its physical limit according to Landauer [1,2] who proved that in logic computation every bit of information loss generates kTln2 joules of heat energy, where k is Boltzmanns constant of 1.38 x 10-23 J/K, and T is the absolute temperature of the environment. At room temperature the dissipating heat is around 2.9 x 10-21 J. Energy loss by Landauer limit is important because it is likely that the growth of heat generation due to information loss will be noticeable in future. Bennett [3] showed that zero energy dissipation would be possible if the network consists of reversible gates only. Reversible logic has also found its applications in several disciplines such as quantum computing [4], nanotechnology [5], DNA technology [6] and optical computing [7]. Due to inherent characteristics of floating point numbers and limitations on storing formats, not all floating-point numbers can be represented with desired precision [8]. Faster hardware for decimal floatingpoint arithmetic is also imminent as it has its importance in financial, Internet based applications. So, faster circuits for Binary Coded Decimal (BCD) numbers have great impact, as it is likely to be

incorporated in more complex circuits like future mathematical processors. Reversible logic implementations for BCD adder using 4-bit parallel adder is presented in [9], where the reversible Full-adder implementation of [10] is used. In [11], both BCD adder and Carry Skip BCD adder are implemented in reversible mode. In this paper, improved design techniques of reversible logic implementation for BCD adder and Carry Skip BCD adder are presented. We have compared the proposed designs with the existing ones and found that modified designs are better than the existing ones in terms of number of gates, garbage output (output that is needed to maintain reversibility) and delay.

2. Basic Definitions and Literature Review

In this section, basic definitions and ideas related to reversible logic are presented. Definition 2.1. Reversible Gates are circuits in which number of outputs is equal to the number of inputs and there is a one to one correspondence between the vector of inputs and outputs [10]. Example 2.1. Let the input vector be Iv, output vector Ov and they are defined as follows, Iv = (Ii , Ii+1, Ii+2 Ik-1, Ik,) and Ov = (Oi , Oi+1, Oi+2 Ok-1, Ok). For each particular i, there exits the relationship Iv Ov. Definition 2.2. Unwanted or unused output of reversible gate (or circuit) is known as Garbage Output. Example 2.2. In Figure 2.1, P is a garbage output that propagates the primary input A.

Figure 2.1. Garbage output Definition 2.3. The delay of a logic circuit is the maximum number of gates in a path from any input

1063-9667/08 $25.00 2008 IEEE DOI 10.1109/VLSI.2008.37

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line to any output line. This definition is based on the following assumptions: i. Each gate performs computation in one unit time ii. All inputs to the circuit are available before the computation begins. A reversible circuit must incorporate reversible gates in it and the number of gates used and garbage output produced are always a good complexity measure for the circuit. Delay of a circuit should also be minimized.

3. Overview of the Existing Designs

The basic feature of the reversible BCD adder design in [9] is the use of combination of New gate [12] and Peres gate [13] as full-adder. The design techniques for both reversible BCD adder and Carry Skip BCD adder are presented in [11] and one of the basic characteristics of these designs is the use of TSG [11] gate as a full adder. For reversible BCD adder, one 4-bit parallel adder is used for binary addition of the numbers, a combinational circuit is used for detection of BCD overflow and another 4-bit parallel adder is used for error correction if overflow occurs. Apart from these basic components, in Carry Skip reversible BCD adder, carry skip logic is incorporated for faster carry generation, which is used in the overflow detection logic. The general ideas of these designs are as follows: In the first 4-bit parallel adder, initial sum is produced by the binary addition of the two BCD numbers. In the combinational part, BCD overflow is detected. In the strict reversible sense, fan-out is restricted. Therefore, copying circuit is used. In the correction part, a 4-bit parallel adder is used to add the error correction value, i.e. in binary 0110, whenever overflow occurs. Otherwise, output produced by the first 4-bit parallel adder becomes the final output. However, there are scopes to improve the designs in terms of number of gates, garbage outputs and delay. We have designed reversible BCD adder and carry skip reversible BCD adder, which overcome the limitations of the existing designs.

4. Proposed Reversible BCD Adders

In this section, improved designs for reversible BCD and Carry Skip Reversible BCD adder have been presented with detail algorithms and figures.

Definition 4.1.1. A full-adder is a device that takes as input two input bits and a carry-in bit and produces as output the sum of the bits and the carry-out. Theorem 4.1.1. A reversible full adder can be realized by at least one gate. Proof. The input and output vector, Iv and Ov for TSG [11] gate are Iv = (A,B,C,D) and Ov=( P = A , Q = A.C B , R = ( A.C B) D , S = (A.C B).D (AB C) respectively. If we put input bit, C = 0(constant) and other 3 inputs are for the 3 bits to be added; sum and carry are produced at output R and S respectively; and hence, a reversible full adder can be realized by at least one gate. Lemma 4.1.1. A reversible 4-bit parallel adder can be realized by at least 4 reversible gates. Proof. Theorem 4.1.1 proves that a reversible full adder can be realized by at least one gate. As a reversible 4-bit parallel adder consists of 4 reversible full adders, a reversible 4-bit parallel adder can be realized by at least 4 x 1 = 4 gates. Definition 4.1.2. A combinational circuit for BCD overflow detection is a circuit that checks whether the result of the binary addition of the two BCD numbers overflows. A BCD number overflow occurs if the resulting number is greater than 1001(decimal 9). Let A3A2A1A0 and B3B2B1B0 be the two BCD numbers to be added and the resulting number is represented by T3T2T1T0. Carry out is represented by C4. C4 is set when the resulting number is greater than 1111, i.e. decimal 15. Six invalid BCD numbers can be detected by the condition (T2+T1). T3. So, the expression for overflow detection bit, F is (T2+T1). T3 + C4. However, it is easy to note that (T2+T1). T3 and C4 cannot be set at the same time. Therefore, a revised expression for overflow detection bit is, F = (T2+T1). T3 C4. If F is set, an overflow has been occurred. In error correction logic, 0110 (decimal 6) is added to the partial sum, T3T2T1T0 and any carry out from this addition is ignored. Carry out from the addition of two BCD numbers A3A2A1A0 and B3B2B1B0 is already computed along with F. If F is not set, no error correction is needed. The partial sum, T3T2T1T0 itself becomes the final result.

4.2. Proposed Reversible BCD Adder

A reversible BCD adder consists of three components: a 4-bit parallel adder, BCD adder overflow detection logic and BCD adder overflow correction logic. We will present these parts with proper algorithms and appropriate figures of the algorithms in this section.

4.1. Basic Properties

Definitions and necessary terminologies related to Binary Coded Decimal (BCD) number and adder are presented here.

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In order to propose the 1-digit BCD adder, we have proposed three algorithms. Algorithm 4.2.1, termed as Overflow_Detection_Algorithm (ODA), is used to detect the overflow produced by adding two BCD digits. Overflow_Correction_Algorithm (OCA), or Algorithm 4.2.2, is used to correct the error generated by adding two BCD digits. Finally, Algorithm 4.2.3, which is termed as BCD_Adder_ Construction_Algorithm, is used to design the overall circuit. Algorithm 4.2.1. ODA (T) Input: T (C4, T3, T2, T1): a 4bit vector which we mentioned as the partial sum received from the binary adder discussed in Sub-section 4.1. Output: The vector R=(T F) would be the output from this algorithm, where F is the overflow detection bit (1 indicates overflow, 0 otherwise). The reversible logic design states that there must be no fan-out from any segment of the circuit. It is to be noted that, the T vector is required again for correction after overflow detection, but T was fed to this detection circuit. There are numerous ways of generating copies of T vector at any level, but we preferred this detection circuit to produce T vector as well. begin Overflow detection bit, F = (T2+T1). T3 C4. The expression shows that the resulting circuit may contain at least two blocks. The approach might be similar to the following Step 1: The first block will take T1 and T2 and output (T2+T1). Step 2: The second block will take the T3, C4 and output from first block (T2+T1 ) and compute the result F = (T2+T1). T3 C4. return R:= T F; end Example 4.2.1. Figure 4.2.1 shows a direct implementation of Algorithm 4.2.1 where T = (C4, T3, T2, T1).
T2 T1 1

Algorithm 4.2.2. OCA (R) Input: R = (T F): a 4 bit vector received from the overflow detection logic circuit. Output: Final corrected BCD sum S (Cout, S3, S2, S1, S0). As T vector that was fed to the detection logic does not include T0, it is free and intact to use as S0. It is not mandatory to wait for the final carry out, because if F is 1, we are sure that the final carry out Cout= 1, so we need not propagate further to compute this carry. begin Step 1: The first block will take T1 and F from the overflow detection logic circuit and generate S1 = T1 F and carry_out1 = T1.F. Step 2: The second block will take carry out of the first block, T2 from the overflow detection circuit and F (this F can be duplicated using numerous techniques, in our circuit first block generates F again) and generate S2 = T2 F carry_out1. It will also generate carry_out2 = (T2 F). carry_out1+ T2.F. Step 3: The third block will take carry out of the second block, T3 from the overflow detection circuit and generate S3 = T3 carry_out2. return S; end Example 4.2.2. Figure 4.2.2 shows implementation of Algorithm 4.2.2. a direct

FRG

FRG

T2 T1 1

Algorithm 4.2.3. BCD_ADDER_CONSTRUCTION _ ALGORITHM (A, B) Input: A = (A3, A2, A1, A0) and B= (B3, B2, B1, B0) are two 4-bit input BCD vectors. Output: Final corrected BCD sum S (Cout, S3, S2, S1, S0). begin T:= Binary Adder output(A, B); R:= ODA(T); S:= OCA(R); return S; end Example 4.2.3. Figure 4.2.3 shows a direct implementation of Algorithm 4.2.3. Table 1 shows the comparative analysis of the proposed reversible BCD adder with the designs presented in [9, 11] and it clearly shows that the proposed design outperforms both the existing designs in every metrics.

T3 C4

TG

T3 F = (T2 + T1) T3 C4

Figure 4.2.1. 1 digit BCD adders overflow detection logic

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Figure 4.2.2. Designing a 1 bit BCD adders correction logic circuit

Figure 4.2.3. Design of a 1-digit BCD adder Table 1. Comparison of different reversible BCD adders
Existing Circuit 1 [11] Existing Circuit 2 [9] Proposed Circuit

Gates 11* 23 10 Garbage 22* 22 10 Delay 10* 13 10 * The design in [11] contains multiple fan-outs, which are forbidden in strict reversible sense.

4.3 Proposed Carry Skip Reversible BCD Adder

A carry skip reversible BCD adder consists of the following components: a 4-bit parallel adder, Carry Skip logic, BCD adder overflow detection logic and

BCD adder overflow correction logic. Carry skip logic may generate the carry out, Cout instantaneously. We will present these components with proper algorithms and appropriate figures. The proposed design is found to be much better than the existing one [11] in terms of number of gates, number of garbage and delay. Carry skip logic circuit is the fundamental part to this design. We can propagate the carry in, Cin to the carry out, Cout of the block. Let, Ai and Bi be the inputs to i-th full-adder and either of them is set. Proper expression for this condition is: Pi = Ai Bi and Cin to the block will propagate to the carry output of the block if the entire Pis are set. In this way, we can generate Cout without waiting for it to be generated in ripple carry fashion. Let, the propagation signal for the block is denoted by P. Then, P = P3.P2.P1.P0. If P is set,

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Cin will be propagated to the Cout. However, in the other case, Cout will be generated in the ripple carry fashion. So, carry skip logic bit of the block is K = P.Cin + C4 where C4 is the carry generated in the ripple carry fashion. The overall overflow detection bit, F = (T1+T2). T3 K is generated in the same way with Reversible BCD adder presented earlier in this paper. Overflow correction logic incorporated is the same as the Reversible BCD adder. The following procedure (Algorithm 4.3.1) is used for the design of Carry Skip 1-digit BCD adder. This procedure is presented along with appropriate figure. Algorithm 4.3.1. CARRY_SKIP_BCD_ADDER_ ALGORITHM (A, B, Ci) Input: A (A3, A2, A1, A0) and B (B3, B2, B1, B0) are two input vectors and Cin is the carry in. Output: A BCD adder capable of performing the sum = A + B. The buffer vector S (Cout, S3, S2, S1, S0) will store the result. begin Step 1: Compute P (propagate bit). Initially P:= true for all i in {0, 1 3} do P := P AND (Ai Bi ). Step 2: Compute T:= {C4,T3,T2,T1,T0}, where Ti := Ai Bi Ci and Ci s are generated from each adder block. Step 3: Compute carry skip logic bit, K:= P.Cin + C4. Step 4: The overall overflow detection bit F:= (T1+T2)T3 K, which is true whenever a BCD overflow is detected. Step 5: Add binary 0110 to T if overflow detection bit F is true. Step 6: Compute S:= (Cout, S3, S2, S1, S0), the final sum of the addition process. return S; end Example 4.3.1. Figure 4.3.1 shows a direct implementation of Algorithm 4.3.1. The Fredkin gates in the middle of the Figure 4.3.1 generate the block propagation, P and carry skip logic bit, K. Fredkin gates and Toffoli gate on the left side performs the BCD overflow detection same as for reversible BCD adder. BCD overflow correction logic is also like the reversible BCD adder. Table 2 shows the comparative analysis of the improved Carry Skip Reversible BCD adder with the one presented in [11] and it clearly shows that the proposed design outperforms the existing one in every metrics. Circuit presented in [11] allows multiple fan-outs that are prohibited in strict reversible sense.

Table 2. Comparison of different carry skip reversible BCD adders

No. of gates No. of garbage Delay A B A B A B Existing Circuit [11] 15 21 27 27 10 12 Proposed Circuit (Without Fanout) 15 14 10

# A = With Fan out, B = Without Fan out * fan outs in reversible design are forbidden. But as it was found in literature [11], the numbers are shown here only.

5. Conclusions
In this paper, reversible logic syntheses were carried out for both BCD adder and carry skip BCD adder. The designs have been done for ease of reversible logic implementation and it has been found that the proposed designs are far better than the existing ones [9,11] in terms of number of gates needed, number of garbage outputs produced and delay. Improved Carry Skip BCD adder can perform much faster than the BCD adder. If multiple BCD blocks are used in the carry skip adder, i.e. m-digit BCD numbers, then carry skip BCD adder has the potential to perform the desired operation much faster. BCD adders can be an important part of some other larger and more complex reversible circuits. Fast and improved BCD adders may also find its use in future quantum computers [4].

6. References
[1] Keyes R, Landauer R. Minimal Energy Dissipation in Logic. IBM Journal of Research and Development 1970; 14: 153-7. [2] Landauer R. Irreversibility and heat generation in the computational processs. IBM Journal of Research Development 1961; 5: 183-91. [3] Bennett CH. Logical reversibility of computation. IBM Journal of Research and Development 1973; 17: 525-32. [4] Shende VV, Prasad AK, Markov IL, Hayes JP. Synthesis of reversible logic circuits. IEEE Transaction on CAD 2003; 22(6): 723-9. [5] Moore GE. Cramming more components onto integrated circuits. Journal of Electronics 1965; 38(8). [6] Frank M. Physical Limits of Computing. CIS 4930.1194X/6930.1078X, 2000. [7] Perkowski M. Reversible Computation for Beginners. Lecture Series 2000. Portland State University. http://www.ee.pdx.edu/~mperkows. [8] Hayes JP. Computer Architecture and Organization, 3rd ed. McGraw-Hill; 1998. [9] Babu HMH, Chowdhury AR. Design of a Compact Reversible Binary Coded Decimal Adder Circuit. Elsevier Journal of Systems Architecture 2006, 52 (5): 272-82.

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Figure 4.3.1. Design of a carry skip 1-digit BCD adder

[10] Babu HMH, Islam MR, Chowdhury AR, Chowdhury SMA. Synthesis of full-adder circuit using reversible logic. 17th International Conference on VLSI Design 2004; 757-60. [11] Thapliyal H, Kotiyal S, Srinivas MB. Novel BCD Adders and their Reversible Logic Implementation for IEEE 754r Format. 19th International Conference on VLSI Design 2006; 387-92. [12] Khan M. H. A and Perkowski M. Multi-output ESOP synthesis with cascades of new reversible families. 6th International Symposium on Representations and Methodology of Future Computing Technologies, March 2003, 144-153. [13] Peres A. Reversible Logic and Quantum Computers. Physical Review 1985; 3266-76.

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