HALF ADDER AND FULL ADDER Expt.

No:1a Date :

AIM: To implement half adder using Verilog HDL. APPARATUS REQUIRED:

PROCEDURE:

ModelSim or Xilinx) and verify the output waveform as obtained. in Spartan III using FPGA kit. HALF ADDER

Ex.no:1 HALF ADDER module hadder(a,b, s,c); input a,b; output s,c; assign c = a&b; assign s = a^b; endmodule Test bench program module adderr_v; // Inputs reg a; reg b; // Outputs wire s; wire c; // Instantiate the Unit Under Test (UUT) hadder uut ( .a(a), .b(b), .s(s), .c(c) ); initial begin // Initialize Inputs a = 0; b = 0; // Wait 100 ns for global reset to finish #100; // Add stimulus here end endmodule

Test bench waveform for Half adder:

Expt. No:1b Date :

AIM: To implement full adder using Verilog HDL. APPARATUS REQUIRED:

PROCEDURE:

ModelSim or Xilinx) and verify the output waveform as obtained.

Full adder

Full adder module fadd(a,b,c, s,carry); input a,b,c; output s,carry; assign s=a^b^c; assign carry=((a&b)|(b&c)|(c&a)); endmodule Test bench program module add_v; // Inputs reg a; reg b; reg c; // Outputs wire sum; wire carry; // Instantiate the Unit Under Test (UUT) full uut ( .a(a), .b(b), .c(c), .sum(sum), .carry(carry) ); initial begin // Initialize Inputs a = 0; b = 0; c = 0; // Wait 100 ns for global reset to finish #100; // Add stimulus here end endmodule

Test bench waveform for full adder:

HALF SUBTRACTOR AND FULL SUBTRACTOR Expt. No:2a Date :

AIM: To implement half subtractor using Verilog HDL. APPARATUS REQUIRED:

PROCEDURE:

tem.

ModelSim or Xilinx) and verify the output waveform as obtained.

Half subtractor

Half subtractor module sub(a, b, diff, brw); input a; input b; output diff; output brw; assign diff=a^b; assign brw=(~a&b);

endmodule Test bench program module half subt_v; // Inputs reg a; reg b; // Outputs wire diff; wire brw; // Instantiate the Unit Under Test (UUT) sub uut ( .a(a), .b(b), .diff(diff), .brw(brw) ); initial begin // Initialize Inputs a = 0; b = 0; // Wait 100 ns for global reset to finish #100; // Add stimulus here end endmodule

Test bench wave form for half subtractor:

Expt. No:2b Date :

AIM: To implement full subtractor using Verilog HDL. APPARATUS REQUIRED:

software.

PROCEDURE:

ModelSim or Xilinx) and verify the output waveform as obtained.

Full subtractor

Full subtractor module full(a, b, c, diff,brw); input a; input b; input c; output diff,brw; assign diff=a^b^c; assign brw=(~a&b&c); endmodule Test bench program module full sub_v; // Inputs reg a; reg b; reg c; // Outputs wire diff; wire brw; // Instantiate the Unit Under Test (UUT) full uut ( .a(a), .b(b), .c(c), .diff(diff), .brw(brw) ); initial begin // Initialize Inputs a = 0; b = 0; c = 0; // Wait 100 ns for global reset to finish #100; // Add stimulus here end endmodule

Test bench waveform for Full subtractor:

8 BIT ADDER
Expt. No:3 Date :

AIM: To implement 8 bit adder using Verilog HDL. APPARATUS REQUIRED:

PROCEDURE:

ModelSim or Xilinx) and verify the output waveform as obtained. in Spartan III using FPGA kit.

8 bit adder module adder(a, b, s, c); input [7:0] a; input [7:0] b; output [7:0] s; output c; assign {c,s}=a+b; endmodule

Test bench program module bitadder_v; // Inputs reg [7:0] a; reg [7:0] b; // Outputs wire [7:0] s; wire c; // Instantiate the Unit Under Test (UUT) ad uut ( .a(a), .b(b), .s(s), .c(c) ); initial begin // Initialize Inputs a = 0; b = 0; // Wait 100 ns for global reset to finish #100; // Add stimulus here end endmodule

Test bench waveform

ADDRESS DECODER
Expt. No:4 Date :

AIM: To implement 2 to 4 decoder using Verilog HDL. APPARATUS REQUIRED:

ModelSim software.

PROCEDURE:

ModelSim or Xilinx) and verify the output waveform as obtained.

2 4 decoder:

Address decoder module decoder(a, b,e,f,g,h); input a; input b; output e,f,g,h; wire c,d; assign c= ~a; assign d= ~b; assign e= c&d; assign f= c&b; assign g= a&d; assign h= a&b; endmodule Test bench program module addressdecoder_v; // Inputs reg a; reg b; // Outputs wire e; wire f; wire g; wire h; // Instantiate the Unit Under Test (UUT) decoder uut ( .a(a), .b(b), .e(e), .f(f), .g(g), .h(h) ); initial begin // Initialize Inputs a = 0; b = 0; // Wait 100 ns for global reset to finish #100; // Add stimulus here end endmodule

Test bench waveform

MULTIPLEXER
Expt. No:5 Date :

AIM: To implement 4: 1 multiplexer using Verilog HDL. APPARATUS REQUIRED:

Sim software.

PROCEDURE:

ModelSim or Xilinx) and verify the output waveform as obtained.

4:1 Multiplexer

4:1 multiplexer module mul(d0, d1, d2, d3, s0, s1, y); input d0; input d1; input d2; input d3; input s0; input s1; output y; wire w=(d0 & (~s0) & (~s1) ); wire x=(d1 & (~s0) & s1 ); wire t=(d2 & s0 & (~s1) ); wire z=(d3 & s0 & s1 ); assign y=(w|x|t|z); endmodule Test bench program module muxxxxx_v; // Inputs reg d0; reg d1; reg d2; reg d3; reg s0; reg s1; // Outputs wire y; // Instantiate the Unit Under Test (UUT) mul uut ( .d0(d0), .d1(d1), .d2(d2), .d3(d3), .s0(s0), .s1(s1), .y(y) ); initial begin // Initialize Inputs d0 = 0; d1 = 0; d2 = 0; d3 = 0; s0 = 0; s1 = 0; // Wait 100 ns for global reset to finish #100; // Add stimulus here end endmodule

Test bench waveform

4 BIT COUNTER
Expt. No:6 Date :

AIM: To implement 4 bit counter using Verilog HDL. APPARATUS REQUIRED:

Sim software.

PROCEDURE:

ModelSim or Xilinx) and verify the output waveform as obtained.

4 Bit Counter

4bit counter module bitcounter(clk,clear, q); input clk,clear; output [0:3] q; reg [0:3] q; always @ (posedge clear or negedge clk) begin if (clear) q<=4'd0; else q<=q+1; end endmodule

Test bench program module ripple_v; // Inputs reg clk; reg clear; // Outputs wire [0:3] q; // Instantiate the Unit Under Test (UUT) bitcounter uut ( .clk(clk), .clear(clear), .q(q) ); initial begin // Initialize Inputs clk = 0; clear = 0; // Wait 100 ns for global reset to finish #100; // Add stimulus here end endmodule

Test bench waveform for 4 bit counter

RING COUNTER
Expt. No:7 Date :

AIM: To implement 4 bit counter using Verilog HDL. APPARATUS REQUIRED:

Sim software.

PROCEDURE:

ModelSim or Xilinx) and verify the output waveform as obtained.

Ring counter

Ring counter module ringcount(enable , reset, clk, count); input enable ; input reset; input clk; output [7:0] count; reg[7:0] count; always@(posedge reset or posedge clk) if(reset ==1'b1)count<=8'b0000-0001; else if(enable==1'b1)count<={count[6:0],count[7]}; endmodule Test bench program module ringcounter_v; // Inputs reg enable; reg reset; reg clk; // Outputs wire [7:0] count; // Instantiate the Unit Under Test (UUT) ringcount uut ( .enable(enable), .reset(reset), .clk(clk), .count(count) ); initial begin // Initialize Inputs enable = 0; reset = 0; clk = 0; // Wait 100 ns for global reset to finish #100; // Add stimulus here end endmodule

Test bench waveform for ring counter

JOHNSON COUNTER
Expt. No:8 Date :

AIM: To implement Jhonson counter using Verilog HDL. APPARATUS REQUIRED:

Sim software.

PROCEDURE:

heck the syntax and simulate the above verilog code (using ModelSim or Xilinx) and verify the output waveform as obtained.

Johnson counter

Johnson counter module data(q, d, clk, rst); output q; input d; input clk; input rst; reg q; always @(posedge clk or posedge rst) if (rst) q <=1'b0; else q <=d; endmodule

module johnson(l,m,n,q,clk,rst); output l; output m; output n; output q; input clk; input rst; wire p; assign p=~q; data a(l,p,clk,rst); data b(m,l,clk ,rst); data c(n,m,clk,rst); data d(q,n,clk,rst); endmodule

Test bench program module jcounter_v; // Inputs reg clk; reg rst;

// Outputs wire l; wire m; wire n; wire q; // Instantiate the Unit Under Test (UUT) johnson uut ( .l(l), .m(m), .n(n), .q(q), .clk(clk), .rst(rst) ); initial begin // Initialize Inputs clk = 0; rst = 0;

// Wait 100 ns for global reset to finish #100;

// Add stimulus here

end

endmodule

Test bench waveform for Johnson counter

UP DOWN COUNTER Expt. No:10 Date :

AIM: To implement up down counter using Verilog HDL. APPARATUS REQUIRED:

PROCEDURE:

ModelSim or Xilinx) and verify the output waveform as obtained.

8-BIT UPDOWN COUNTER module up_down_counter(out,up_down,clk,data,reset); output [7:0] out; input [7:0] data; input up_down, clk, reset; reg [7:0] out; always @(posedge clk) if (reset) begin // active high reset out <= 8'b0 ;

end else if (up_down) begin out <= out + 1; end else begin out <= out - 1; end endmodule
TEST BENCH PROGRAM:

module counter1_v; // Inputs reg up_down; reg clk; reg [7:0] data; reg reset; // Outputs wire [7:0] out; // Instantiate the Unit Under Test (UUT) up_down_counter uut ( .out(out), .up_down(up_down), .clk(clk), .data(data), .reset(reset) ); initial begin // Initialize Inputs up_down = 0; clk = 0; data = 0; reset = 0; // Wait 100 ns for global reset to finish #100; // Add stimulus here end endmodule

Test bench waveform for up counter

Test bench waveform for down counter

ACCUMULATOR Expt. No:11

Date

AIM: To implement accumaltor using Verilog HDL. APPARATUS REQUIRED:

PROCEDURE:

ModelSim or Xilinx) and verify the output waveform as obtained. in Spartan III using FPGA kit. Accumulator program: module accum(clk, clr, d, q); input clk; input clr; input [3:0] d; output [3:0] q; reg [3:0]tmp; always @(posedge clk or posedge clr) begin if(clr) tmp <= 4'b000; else tmp <=tmp+d; end assign q=tmp; endmodule

Test bench program: module accumlatorr_v; // Inputs reg clk;

reg clr; reg [3:0] d; // Outputs wire [3:0] q; // Instantiate the Unit Under Test (UUT) accum uut ( .clk(clk), .clr(clr), .d(d), .q(q) ); initial begin // Initialize Inputs clk = 0; clr = 0; d = 0; // Wait 100 ns for global reset to finish #100; // Add stimulus here end endmodule LOGIC DIAGRAM

Test bench waveform: