An Overview of Digital Circuit Testing and Design for Testability

Santosh Biswas Dept. of EE , IIT Kharagpur Advanced VLSI Design Laboratory(Testing)

Fault Simulation
Problem and motivation Fault simulation algorithms
Serial Parallel Deductive Concurrent

Problem and Motivation

Fault simulation Problem: Given
A circuit A sequence of test vectors A fault model

Determine
Fault coverage - fraction (or percentage) of modeled faults detected by test vectors Set of undetected faults

Motivation
Determine test quality and in turn product quality Find undetected fault targets to improve tests

Fault simulator in a VLSI Design Process

Verified design netlist Fault simulator Remove Modeled fault list tested faults Fault Low coverage ? Adequate Stop Verification input stimuli Test vectors

Test Delete compactor vectors

Test generator

Add vectors

Fault Simulation Scenario

Circuit model: mixed-level
Mostly logic with some switch-level for highimpedance (Z) and bidirectional signals High-level models (memory, etc.) with pin faults

Signal states: logic

Two (0, 1) or three (0, 1, X) states for purely Boolean logic circuits

Timing:
Zero-delay for combinational and synchronous circuits Mostly unit-delay for circuits with feedback

Fault Simulation Scenario (continued)

Faults:
Mostly single stuck-at faults Sometimes stuck-open, transition, and path-delay faults; analog circuit fault simulators are not yet in common use Equivalence fault collapsing of single stuck-at faults Fault-dropping -- a fault once detected is dropped from consideration as more vectors are simulated; fault-dropping may be suppressed for diagnosis Fault sampling -- a random sample of faults is simulated when the circuit is large

Fault Simulation Algorithms

Serial Parallel Deductive Concurrent

Serial Algorithm
Algorithm: Simulate fault-free circuit and save responses. Repeat following steps for each fault in the fault list:
Modify netlist by injecting one fault Simulate modified netlist, vector by vector, comparing responses with saved responses If response differs, report fault detection and suspend simulation of remaining vectors

Advantages:
Easy to implement; needs only a true-value simulator, less memory Most faults, including analog faults, can be simulated

Serial Algorithm (Cont.)

Disadvantage: Much repeated computation; CPU time prohibitive for VLSI circuits Alternative: Simulate many faults together
Test vectors Fault-free circuit Circuit with fault f1 Comparator Circuit with fault f2 Comparator Circuit with fault fn fn detected? f2 detected? Comparator f1 detected?

Parallel Fault Simulation

Compiled-code method; best with two-states (0,1) Exploits inherent bit-parallelism of logic operations on computer words Storage: one word per line for two-state simulation Multi-pass simulation: Each pass simulates w1 new faults, where w is the machine word length Speed up over serial method ~ w-1

Parallel Fault Sim. Example

Bit 0: fault-free circuit Bit 1: circuit with c s-a-0 Bit 2: circuit with f s-a-1
1 1 1 1 1 1 1 1 0 1 0 1

a b

c s-a-0 detected
1 0 1

c s-a-0
0

e
0 0 s-a-1 0 0 1

Deductive Fault Simulation

One-pass simulation Each line k contains a list Lk of faults detectable on k Following true-value simulation of each vector, fault lists of all gate output lines are updated using set-theoretic rules, signal values, and gate input fault lists PO fault lists provide detection data

Deductive Fault Sim. Example

Notation: Lk is fault list for line k kn is s-a-n fault on line k a b
1 1 {b0} {a0} {b0 , c0} Le = La U = {a0 , Lc U {e0} b0 , c0 , e0} 1

c d

e f

{b0 , d0}

{b0 , d0 , f1}

Faults detected by the input vector

Lg = (Le Lf ) U {g0} = {a0 , c0 , e0 , g0}

Conc. Fault Sim. Example

0 1 1 1 1

a0

1 0

b0
0 1

c0
0

1 1

e0
0

a b

c d

1 1 0

e
0

1 0

g
0 1

0 0

a0
0 1 0

b0
1 1 1

0 0 1

c0

0 1 1

0 0 1

e0
0

0 1

b0

0 1

d0

1 1

f1

g0

f1

d0

Testability Measures
Controllability and observability SCOAP measures
Combinational circuit example Sequential circuit example

Purpose
Need approximate measure of:
Difficulty of setting internal circuit lines to 0 or 1 by setting primary circuit inputs Difficulty of observing internal circuit lines by observing primary outputs

Uses:
Analysis of difficulty of testing internal circuit parts redesign or add special test hardware Guidance for algorithms computing test patterns avoid using hard-to-control lines Estimation of fault coverage Estimation of test vector length

Origins Control theory Origins Rutman 1972 -- First definition of controllability Goldstein 1979 -- SCOAP
First definition of observability First elegant formulation First efficient algorithm to compute controllability and observability

Parker & McCluskey 1975

Definition of Probabilistic Controllability

Brglez 1984 -- COP

1st probabilistic measures

Seth, Pan & Agrawal 1985 PREDICT

1st exact probabilistic measures

Testability Analysis
Involves Circuit Topological analysis, but no test vectors and no search algorithm Static analysis Linear computational complexity Otherwise, is pointless might as well use automatic test-pattern generation and calculate: Exact fault coverage Exact test vectors

Types of Measures
SCOAP Sandia Controllability and Observability Analysis Program Combinational measures: CC0 Difficulty of setting circuit line to logic 0 CC1 Difficulty of setting circuit line to logic 1 CO Difficulty of observing a circuit line Sequential measures analogous: SC0 SC1 SO

Range of SCOAP Measures

Controllabilities 1 (easiest) to infinity (hardest) Observabilities 0 (easiest) to infinity (hardest) Combinational measures:
Roughly proportional to # circuit lines that must be set to control or observe given line

Sequential measures:
Roughly proportional to # times a flip-flop must be clocked to control or observe given line

Goldsteins SCOAP Measures Goldsteins SCOAP Measures

AND gate O/P 0 controllability: output_controllability = min (input_controllabilities) +1 AND gate O/P 1 controllability: output_controllability = (input_controllabilities) +1 XOR gate O/P controllability
output_controllability = min (controllabilities of each input set) + 1

Controllability Controllability Examples Examples

More Controllability More Controllability Examples Examples

Observability Examples Observability Examples

To observe a gate input: Observe output and make other input values non-controlling

More Observability More Observability Examples Examples

Error Due to Stems & Error Due to Stems & Reconverging Fanouts Reconverging Fanouts SCOAP measures wrongly assume that controlling or observing x, y, z are independent events
x y z

Sequential Example

Controllability Through Level 0

Circled numbers give level number. (CC0, CC1)

Controllability Through next Level

Final Combinational Controllability

Number in square box is level from primary outputs (POs). (CC0, CC1) CO

Combinational Observability for Level 1

Combinational Observabilities for Level 2

Final Combinational Observabilities

Sequential Measure Differences

Combinational Increment CC0, CC1, CO whenever you pass through a gate, either forwards or backwards Sequential Increment SC0, SC1, SO only when you pass through a flip-flop, either forwards or backwards, to Q, Q, D, C, SET, or RESET Both Must iterate on feedback loops until controllabilities stabilize

Assume a synchronous RESET line. CC1 (Q) = CC1 (D) + CC1 (C) + CC0 (C) + CC0 (RESET) SC1 (Q) = SC1 (D) + SC1 (C) + SC0 (C) + SC0 (RESET) + 1 CC0 (Q) = min [CC1 (RESET) + CC1 (C) + CC0 (C), CC0 (D) + CC1 (C) + CC0 (C)] SC0 (Q) is analogous CO (D) = CO (Q) + CC1 (C) + CC0 (C) + CC0 (RESET) SO (D) is analogous

D Flip-Flop Equations

Sequential Example Initialization

After 1 Iteration

After 2 Iterations

After 3 Iterations

Stable Sequential Measures

Final Sequential Observabilities

Combinational Automatic Test-Pattern Generation (ATPG) Basics

Origins of Stuck-Faults
Eldred (1959) First use of structural testing for the Honeywell Datamatic 1000 computer Galey, Norby, Roth (1961) First publication of stuck-at-0 and stuck-at-1 faults Seshu & Freeman (1962) Use of stuckfaults for parallel fault simulation Poage (1963) Theoretical analysis of stuck-at faults

Functional vs. Structural Functional vs. Structural ATPG ATPG

Carry Circuit

Functional vs. Structural Functional vs. Structural

Functional ATPG generate complete set of tests for circuit input-output combinations
129 inputs, 65 outputs: 2129 = 680,564,733,841,876,926,926,749,

214,863,536,422,912 patterns
Using 1 GHz ATE, would take 2.15 x 1022 years

Structural test:
No redundant adder hardware, 64 bit slices Each with 27 faults (using fault equivalence) At most 64 x 27 = 1728 faults (tests) Takes 0.000001728 s on 1 GHz ATE

Exhaustive Algorithm
For n-input circuit, generate all 2n input patterns Infeasible, unless circuit is partitioned into cones of logic, with 15 inputs
Perform exhaustive ATPG for each cone Misses faults that require specific activation patterns for multiple cones to be tested

Random-Pattern Generation Random-Pattern Generation

Flow chart for method Use to get tests for 6080% of faults, then switch to D-algorithm or other ATPG for rest

Circuit and Binary Circuit and Binary Decision Tree Decision Tree

Binary Decision Diagram Binary Decision Diagram

BDD Follow path from source to sink node product of literals along path gives Boolean value at sink Rightmost path: A B C = 1 Problem: Size varies greatly with variable order

Algorithm Completeness
Definition: Algorithm is complete if it ultimately can search entire binary decision tree, as needed, to generate a test Untestable fault no test for it even after entire tree searched Combinational circuits only untestable faults are redundant, showing the presence of unnecessary hardware

Algebras: Roths 5-Valued Algebras: Roths 5-Valued and Muths 9-Valued and Muths 9-Valued
Failing Good Symbol Meaning Machine Machine 0 D 1/0 1 1 D 0/1 0 Roths 0 0 0/0 0 Algebra 1 1 1/1 1 X X X/X X X G0 0/X 0 X G1 1/X 1 Muths 0 Additions F0 X/0 X 1 F1 X/1 X

Roths and Muths HigherRoths and Muths HigherOrder Algebras Order Algebras
Represent two machines, which are simulated simultaneously by a computer program:
Good circuit machine (1st value) Bad circuit machine (2nd value)

Better to represent both in the algebra:

Need only 1 pass of ATPG to solve both Good machine values that preclude bad machine values become obvious sooner & vice versa

Needed for complete ATPG:

Combinational: Multi-path sensitization, Roth Algebra Sequential: Muth Algebra -- good and bad machines may have different initial values due to fault

Path Sensitization Method Path Sensitization Method Circuit Example Circuit Example
1 Fault Sensitization 2 Fault Propagation 3 Line Justification

Path Sensitization Method Path Sensitization Method Circuit Example Circuit Example
Try path f h k L blocked at j, since there is no way to justify the 1 on i
1 1 D D 1 0 D D D

Path Sensitization Method Path Sensitization Method Circuit Example Circuit Example
Try simultaneous paths f h k L and g i j k L blocked at k because D-frontier (chain of D or D) disappears
1 1 1 D D D D 1 D

Path Sensitization Method Path Sensitization Method Circuit Example Circuit Example
Final try: path g i j k L test found!
0 1 1 1 0 D D D D D

Redundancy Removal Using ATPG

Redundancy identification Redundancy removal

Redundant Hardware and Redundant Hardware and Simplification Simplification

Redundant Fault q sa1 Redundant Fault q sa1

Multiple Fault Masking Multiple Fault Masking

f sa0 tested when fault q sa1 not there

Intentional Redundant Implicant BC

Eliminates hazards in circuit output

Major Combinational Automatic Test-Pattern Generation Algorithms

D-Algorithm (Roth) 1966

Branch-and-Bound Search
Efficiently searches binary search tree Branching At each tree level, selects which input variable to set to what value Bounding Avoids exploring large tree portions by artificially restricting search decision choices
Complete exploration is impractical Uses heuristics

Example Fault A sa0 Example Fault A sa0

Step 1 D-Drive Set A = 1

Step 2 -- Example Step 2 -- Example

Step 2 D-Drive Set f = 0

0 1 D D

Step 3 -- Example Step 3 -- Example

Step 3 D-Drive Set k = 1
1 0 1 D D D D

Step 4 -- Example Step 4 -- Example

Step 4 Consistency Set g = 1
1 0 1 D D 1 D D

Step 5 -- Example Step 5 -- Example

Step 5 Consistency f = 0 Already set
1 0 1 D D 1 D D

Step 6 -- Example Step 6 -- Example

Step 6 Consistency Set c = 0, Set e = 0
1 0 D 0 0 D D 1 D

Example Example
Step 7 Consistency Set B = 0
X 0 0 1 D 1 0 0 D

1 D D

Example Fault s sa1

Primitive D-cube of Failure
1 D

sa1

Example Step 2 s sa1

Propagation D-cube for v
1 D

sa1 0

Example Step 2 s sa1

Forward & Backward Implications
1 1 1 1 1 D 0

sa1 0

Example Step 3 s sa1

Propagation D-cube for Z test found!
1 1 1 1 1 D 0

sa1 0

D 1

Example Fault u sa1

Primitive D-cube of Failure
1

0 sa1 D

Example Step 2 u sa1

Propagation D-cube for v
1 0

0 sa1 D

Example Step 2 u sa1

Forward and backward implications
1 0 0 1 0 D sa1 D 1

Inconsistent

d = 0 and m = 1 cannot justify r = 1 (equivalence)

Backtrack Remove B = 0 assignment

Example Backtrack
Need alternate propagation D-cube for v
1

0 sa1 D

Example Step 3 u sa1

Propagation D-cube for v
1

0 sa1 D D

Example Step 4 u sa1

Propagation D-cube for Z
1

0 sa1 D D

D 1

Example Step 4 u sa1

Propagation D-cube for Z and implications
1 1 1 1 1 0 D 1 sa1 D D 0 0 0

Sequential Circuit ATPG Time-Frame Expansion

Problem of sequential circuit ATPG Time-frame expansion
Nine-valued logic ATPG implementation and drivability Complexity of ATPG

Sequential Circuits
A sequential circuit has memory in addition to combinational logic. Test for a fault in a sequential circuit is a sequence of vectors, which
Initializes the circuit to a known state Activates the fault, and Propagates the fault effect to a primary output

Methods of sequential circuit ATPG

Time-frame expansion methods Simulation-based methods

Example: A Serial Adder

An Bn 1 1 s-a-0 1 1 Cn X Combinational logic FF Sn X D D

X Cn+1 1

Time-Frame Expansion
An-1 Bn-1
1 1

Time-frame -1
s-a-0 1 D D X X

An Bn
1 1

Time-frame 0
s-a-0 1 D D D 1

Cn-1
X

Cn
1

Cn+1
1

Combinational logic

Sn-1
X

Combinational logic

Sn
D

FF

Concept of Time-Frames
If the test sequence for a single stuck-at fault contains n vectors,
Replicate combinational logic block n times Place fault in each block Generate a test for the multiple stuck-at fault using combinational ATPG with 9-valued logic Fault
Unknown or given Init. state Vector -n+1 Vector -1 Vector 0

Comb. block

Timeframe -n+1 PO -n+1

State variables

Timeframe -1 PO -1

Timeframe 0 PO 0

Next state

Example for Logic Systems

FF1

s-a-1

FF2

Five-Valued Logic (Roth) 0,1, D, D, X

A 0 s-a-1 D FF1 FF2 X X X D A 0 s-a-1 D X D FF1 FF2

Time-frame -1

B X

Time-frame 0

B X

Nine-Valued Logic (Muth)

0,1, 1/0, 0/1, 1/X, 0/X, X/0, X/1, X
A 0 s-a-1 0/1 FF1 FF2 X X 0/X 0/1 A X s-a-1 X/1 0/X X/1 FF1 FF2

Time-frame -1

B X

Time-frame 0

0/1

Implementation of ATPG
Select a PO for fault detection based on drivability analysis. Place a logic value, 1/0 or 0/1, depending on fault type and number of inversions. Justify the output value from PIs, considering all necessary paths and adding backward time-frames. If justification is impossible, then use drivability to select another PO and repeat justification. If the procedure fails for all reachable POs, then the fault is untestable. If 1/0 or 0/1 cannot be justified at any PO, but 1/X or 0/X can be justified, the the fault is potentially detectable.

Design for Testability (DFT): Full-Scan

Definition
Design for testability (DFT) refers to those design techniques that make test generation and test application cost-effective. DFT methods for digital circuits:
Ad-hoc methods Structured methods:
Scan Partial Scan Built-in self-test (BIST) Boundary scan

DFT method for mixed-signal circuits:

Analog test bus

Ad-Hoc DFT Methods

Good design practices learnt through experience are used as guidelines:
Avoid asynchronous (unclocked) feedback. Make flip-flops initializable. Avoid redundant gates. Avoid large fanin gates. Provide test control for difficult-to-control signals. Avoid gated clocks. Consider ATE requirements (tristates, etc.)

Design reviews conducted by experts or design auditing tools. Disadvantages of ad-hoc DFT methods:
Experts and tools not always available. Test generation is often manual with no guarantee of high fault coverage. Design iterations may be necessary.

Scan Design
Circuit is designed using pre-specified design rules. Test structure (hardware) is added to the verified design:
Add a test control (TC) primary input. Replace flip-flops by scan flip-flops (SFF) and connect to form one or more shift registers in the test mode. Make input/output of each scan shift register controllable/observable from PI/PO.

Use combinational ATPG to obtain tests for all testable faults in the combinational logic. Add shift register tests and convert ATPG tests into scan sequences for use in manufacturing test.

Scan Design Rules

Use only clocked D-type of flip-flops for all state variables. At least one PI pin must be available for test; more pins, if available, can be used. All clocks must be controlled from PIs. Clocks must not feed data inputs of flip-flops.

Correcting a Rule Violation

All clocks must be controlled from PIs.
Comb. logic D1 D2 CK FF Q Comb. logic

Comb. logic D1 D2 CK Q FF Comb. logic

Scan Flip-Flop (SFF)

D TC
Logic overhead

Master latch

Slave latch Q

SD CK

MUX

D flip-flop Master open Slave open

CK

t Scan mode, SD selected

TC

Normal mode, D selected

Adding Scan Structure

PI Combinational logic SFF SFF SFF PO SCANOUT

TC or TCK SCANIN

Not shown: CK or MCK/SCK feed all SFFs.

Testing Scan Register

Scan register must be tested prior to application of scan test sequences. Example: 2,000 scan flip-flops, 500 comb. vectors, total scan test length ~ 106 clocks. Multiple scan registers reduce test length.

Scan flip-flops can be distributed among any number of shift registers, each having a separate scanin and scanout pin. Test sequence length is determined by the longest scan shift register. Just one test control (TC) pin is essential. PI/SCANIN
Combinational logic SFF SFF TC CK SFF
M U X

Multiple Scan Registers

PO/ SCANOUT

Scan Overheads
IO pins: Area overhead: Performance overhead:
Multiplexer delay added in combinational path; approx. two gate-delays. Flip-flop output loading due to one additional fanout; approx. 5-6%.

Power

Automated Scan Design

Rule violations Scan design rule audits Behavior, RTL, and logic Design and verification

Gate-level netlist Scan hardware insertion Scan netlist Scan chain order Design and test data for manufacturing Chip layout: Scanchain optimization, timing verification

Combinational ATPG Combinational vectors Scan sequence and test program generation

Test program

Mask data

Boundary Scan Standard

IEEE 1149.1 JTAG

Motivation for Standard

Bed-of-nails printed circuit board tester gone We put components on both sides of PCB & replaced DIPs with flat packs to reduce inductance Nails would hit components Reduced spacing between PCB wires Nails would short the wires PCB Tester must be replaced with built-in test delivery system -- JTAG does that Need standard System Test Port and Bus Integrate components from different vendors Test bus identical for various components One chip has test hardware for other chips

System Test Logic

Instruction Register Loading with JTAG

Serial Board / MCM Scan

The Slides have been collected form the work of Vishwani D. Agrawal

Thanks !!!!