ARM7 ARCHITECTURE

A Brief overview.
Advanced RISC Machine (ARM) architectures were developed by Acorn Company. The series started with ARM1 and has till now reached ARM11. In this section, a brief introduction to ARM 7 architecture and its general features is presented. ARM 7 is intended for applications, which require power efficient processors, such as wireless telecommunications, data communication (protocol converter), portable instruments, portable computers and smart cards. Introduction The principle feature of the ARM 7 microcontroller is that it is a register oriented load-and-store architecture. Unlike other processors it can operate in a number of operating modes. While the ARM7 is a 32 bit microcontroller, it is also capable of running a 16-bit instruction set, known as THUMB i.e. earlier ARM instruction set. This helps it achieve a greater code density and enhanced power saving. To increase the performance of these instructions, the ARM 7 has a three-stage pipeline. Due to the inherent simplicity of the design and low gate count, ARM 7 is the industry leader in low-power processing on a watts per MIP basis. Finally, to assist the developer, the ARM core has a built-in JTAG debug port and on-chip embedded ICE that allows programs to be downloaded and fully debugged in-system. Thus using the JTAG port and embedded ice one can trace the execution of a program during debugging. While all of the register-to-register data processing instructions are single-cycle, other instructions such as data transfer instructions, are multi-cycle. In order to keep the ARM 7 both simple and cost-effective, the code and data regions are accessed via a single data bus. Thus while the ARM 7 is capable of single-cycle execution of all data processing instructions, data transfer instructions may take several cycles since they will require at least two bus cycles; one for the instruction code and another for the data. In order to improve performance, a three stage pipeline is used that allows up to three instructions to be processed simultaneously. The pipeline has three stages; FETCH, DECODE and EXECUTE. The hardware of each stage is designed to be independent so up to three instructions can be processed simultaneously. As we shall see later the ARM 7 designers had some clever ideas to solve this problem. Fig 1 shows the concept of a 3 stage pipelined execution.

Actions Fetch Instru. 1 Actions Instru. 2 Actions Instru. 3 Instructions 1 being executed at a time

Decode Fetch

Execute Decode Fetch

Execution complete Execute Decode 2 2 Waiting to Execute

Fig. 1 3-Stage Pipelined execution of Instructions in ARM7

The pipeline is most effective in speeding up sequential code. However a branch instruction will cause the pipeline to be flushed marring its performance due to jump at unexpected address.
ARM7 Programming Model (Register set) The programmers model of the ARM 7 consists of 15 user registers, as shown in Fig. 2, with R15 being used as the Program Counter (PC). Since the ARM 7 is a load-and-store architecture, a user program must load data from memory into the CPU registers, process this data and then store the result back into memory. Unlike other processors no memory to memory instructions are available.

As stated above R15 is the Program Counter. R13 and R14 also have special functions; R13 is used as the stack pointer, though this has only been defined as a programming convention. Unusually the ARM instruction set does not have PUSH and POP instructions so stack handling is done via a set of instructions that allow loading and storing of multiple registers in a single operation. Thus it is possible to PUSH or POP the entire register set onto the stack in a single instruction. R14 has special significance and is called the link register. When a call is made to a procedure, the return address is automatically placed into R14, rather than onto a stack, as might be expected. A return can then be implemented by moving the contents of R14 into R15, the PC. For nested subroutines, the contents of R14 (the link register) must be placed onto the stack. In addition to the 16 CPU registers, there is a current program status register (CPSR). This contains a set of condition code flags in the upper four bits that record the result of a previous instruction, as shown in Fig 4. In addition to the condition code flags, the CPSR contains a number of userconfigurable bits that can be used to change the processor mode, enter Thumb processing and enable/disable interrupts.

Fig 2 Register Model of ARM7 Instruction Decoder and Logic Control: The function of instruction decoder and logic control

is to fetch, decode instructions and generate control signals to other parts of processor and external circuits for execution of instructions. Address Register: To hold a 32-bit address for sending to address bus. Address Incrementer: It is used to increment an address by four and place it in address register. Register Bank: Register bank contains thirty one 32-bit registers and six status registers. Barrel Shifter: It is used for fast shift operation with large number of shifts with single instruction. ALU: 32-bit ALU is used for Arithmetic and Logic Operation. Write/Read Data Register: The processor stores the data in Write Data Register (DR) for write operation. When processor reads from memory or IO, it places the data in the Read Dataregister.
The schematic archtecture of the processor ARM7 is presented below in fig.

3.

Fig 3 Load And Store Architecture of ARM 7 It is quiet obvious that the large number of busses in the architecture enhance the parallelism in the architecture. The non-multiplexed addresses and data bus and separate read and write data bus will also enhance speed of execution. The separate busses A and B for the ALU operands eliminate the use of temporary registers. The separate ALU output bus and the A and B operand busses achieve overlap of writing of the results of the current operation into the register bank and fetching operands of the next operation from the register bank. The Booths multiplier and Barrel shifter circuits speed up the computationally expensive operations of multiplication and shifting by large number of bits. A separate address incrementer circuit increments the addresses by 4 as word size of the machine is 4 bytes. The instruction pipeline achieves overlap between the execution of the current instruction and fetching and/or decoding of the next instruction. The architecture houses total 31 registers in all the modes of operations excluding the respective program status registers. The Current status and flag register that uses only 12 bits out of 32 bits of the ARM7 register is presented below in fig.4.

Fig 4 Current Program Status Register and Flags

N (negative): N=1 means result of an operation is negative and N=0 means result of an operation is positive. Z (zero): Z=1 means result of an operation is zero and Z=0 result of an operation is not zero. C (carry): C=1 means result of an operation generated a carry, and C=0 means result of an operation did not produce a carry. V (overflow): V=1 means result of an operation generated an overflow and V=0 means result of an operation did not generate an overflow.

Control Bits
I (interrupt bit): When this bit set to one, it will disable the interrupt and this means the processor does not accept any software interrupt. F bit is used to disable and enable fast interrupt request mode (FIQ) mode. M4, M3, M2, M1 and M0 are mode status bits and they are equal to 10000 for user mode. T (State bit): T=1 Processor executing thumb instructions, T=0 processor executing ARM instructions
Exception And Interrupt Modes The ARM 7 architecture has a total of six different operating modes, as shown below. These modes are protected or exception modes which have associated interrupt sources and their own register sets. User: This mode is used to run the application code. Once in user mode the CPSR cannot be written to and modes can only be changed when an exception is generated. FIQ: (Fast Interrupt reQuest) This supports high speed interrupt handling. Generally it is used for a single critical interrupt source in a system IRQ: (Interrupt ReQuest) This supports all other interrupt sources in a system

Supervisor: A protected mode for running system level code to access hardware or run OS calls. The ARM 7 enters this mode after reset. Abort: If an instruction or data is fetched from an invalid memory region, an abort exception will be generated Undefined Instruction: If a FETCHED opcode is not an ARM instruction, an undefined instruction exception will be generated. The User registers R0-R7 are common to all operating modes. However FIQ mode has its own R7 R14 that replace the user registers when FIQ is entered. Similarly, each of the other modes have their own R13 and R14 so that each operating mode has its own unique Stack pointer and Link register. The CPSR is also common to all modes. However in each of the exception modes, an additional register - the saved program status register (SPSR), is added. When the processor changes the current value of the CPSR stored in the SPSR, this can be restored on exiting the exception mode. Fig 5 Full Register Set For ARM 7

Entry to the Exception modes is through the interrupt vector table. Exceptions in the ARM processor can be split into three distinct types. (i) Exceptions caused by executing an instruction, these include software interrupts, undefined instruction exceptions and memory abort exceptions

(ii) Exceptions caused as a side effect of an instruction such as a abort caused by trying to fetch data from an invalid memory region. (iii) Exceptions unrelated to instruction execution, this includes reset, FIQ and IRQ interrupts. In each case entry into the exception mode uses the same mechanism. On generation of the exception, the processor switches to the privileged mode, the current value of the PC+4 is saved into the Link register (R14) of the privileged mode and the current value of CPSR is saved into the privileged modes SPSR. The IRQ interrupts are also disabled and if the FIQ mode is entered, the FIQ interrupts are also disabled. Finally the Program Counter is forced to the exception vector address and processing of the exception can start. Usually the first action of the exception routine will be to push some or all of the user registers onto the stack. *Only two external interrupts are available. Data Types in ARM7: The ARM7 architecture supports 1 byte signed and unsigned, 2bytes signed and unsigned and 4bytes signed and unsigned register and immediate data. This supports little and big endian formats of data. Instruction set features of ARM7: *Most of the instructions have three operands: *A few with two operands or one operand or none. *The destination operand follows the mnemonic, the remaining are source operands. *The default operand sequence can be reversed using R as prefix to instructions. ADD R0,R1,R2 ; does not affect flag.

*Adding S to the mnemonic affects status flags. Fror eg ADDS *A few instructions only affect flags, results are not stored. TST(AND), TEQ(test if equal) *Conditional instructions and unconditional instructions- A condition prefix will execute the instruction only if the condition is satisfied. For Eg. EQ (most significant four bits of the opcode. Sixteen conditions are there. EQ suffixes the mnemonic in asm program. *All registers can be used as pointers [Rn]. Relative address can be added to a pointer content [Rn,#4]!, Autoincrement by 4 after the operation is allowed.pointer is modified. *PC relative mode is available.

*Data Processing Instructions (arithmetic, logical, shift and rotate applied to only second operand) *Multiply Instructions; multiply between registers *Single data Swap ; source Reg moves to destination Reg/mem

*Single data Transfer *Block Data Transfer is available *Branch conditional and unconditional
*PUSH and POP for complete register set is available.