ANNA UNIVERSITY, CHENNAI-25 PRACTICAL EXAMINATION

College

: 135: VELTECH

Programee Subject

: B.E ECE

Semester : 06 LAB Date of Exam : 16, 17.04.2012

: EC2357 VLSI Design

SET II QUESTION PAPER

1. (a) Write a verilog code for Accumulator and write the test bench for the same. (b). Draw a layout for logic circuit .Which do the addition operation and show the spice code the circuit. 2. (a) Write the verilog code Demultiplexing & show P&R , Post P&R simulation and download it to FPGA kit.

(b) Draw a layout for and gate and Show the spice code for the layout. 3. (a) Write a verilog code for the priority encoder,Write the test bench for the code and finally download it to FPGA kit. (b) Design a layout ,which performs the complement of multiplication operation and show the spice code for the layout. 4. (a) Write a verilog code for the flipflop .Which has the letter from the word Rain & Shadow .explain the concept of concurrent sequential execution and show P&R, Post P&R simulation. (b) Design a layout for the NOT gate and show the spice code for it. 5. (a) Write a verilog code for a Flip flop which has a letter from the word Jack & King and show the floor planning, boundary scan for the circuit . Finally implement it in spartan kit.

(b) Design a layout which performs compliment of Addition operation and show the spice code for it.

6. (a) Write a verilog code for Pseudo Random binary sequence generator.Explain the concept of concurrent & sequential execution and show the P&R, Post P&R simulation. (b) Design a oscillator circuit to control the voltage and show the spice code for it. 7. (a) write a verilog code for a flipflop which toggles for that explain the concept of concurrent & sequential execution. (b) Design a schematic circuit for n-bit voltage controlled oscillator. 8. (a) Write a verilog code for a flipflop which delays the signal .show out put in the Spartan kit. (b) Show the automatic layout generation for 10-bit voltage controlled oscillator. 9. (a) Write a verilog code Adder circuit which has two input pin and one carry pin .Explain the concept of concurrent &sequential execution and write the test bench codes. (b) Draw a schematic circuit for the circuit which performs the complement operation and extract the code from the circuit. 10. (a) Write a verilog code for 4-bit Multiplier and should be implemented in FPGA kit. (b) Design differential amplifier circuit to show gain, bandwidth & CMMR 11. (a) Write code for multiplexer using binary operator. Show the output in the FPGA kit. (b) Draw a layout for complement circuit and show the spice code for it. 12. (a) Write the verilog code Address decoder and show the floor plan. (b) Design a Differential Amplifier and Determine the gain,bandwidth and CMRR.

13. (a) Write a Verilog Code for Full Subractor using case statement. (b) Show Automatic Layout Generation for N-bit VCO . 14. (a) Write a Verilog Code for Full Adder by instantiating two Half adder and download it to a FPGA kit. (b) Draw the layout for multiplication gate and extract the p-spice code for the same. 15. (a)Write a verilog code for 4-bit multiplier with two inputs and write the test bench for the same. (b) Design a layout for NOT gate using tanner and show the simulation output. 16. (a)Write a code for 8-bit adder & Implement it in FPGA kit. (b) Draw a layout for NOT gate and Show the spice code for it. 17. (a) Write a code for multiplying two 4-bit values and write a test bench code for the same . Highlight the concept of concurrent of sequential execution. (b)Design a circuit to verify gain, bandwidth &Output impedance. 18. (a) Write a code for decoding the binary values and explain P&R , Post P&R simulation.Finaly implement it in FPGA kit. (b) Design a VLSI circuit to derive the gain, Bandwidth and CMMR. 19. (a) Write a code for multiplexing the binary values .Show the floor planning for the design and implement it in FPGA kit. (b) Design a 10-bit voltage controlled oscillator and show the corresponding output for it. 20. (a) Write the code for synchronous counter and implement it in FPGA kit. (b) Show the automatic layout generation for 10-bit voltage controlled oscillator.

Internal Examiner

External Examiner