Static Timing Analysis

What is Static Timing Analysis? Static Timing Analysis is a method for determining if a circuit meets timing constraints without having to simulate Much faster than timing-driven, gate-level simulation (dynamic simulation) Proper circuit functionality is not checked Vector generation NOT required Three Steps in Static Timing Analysis 1. Timing Paths: Circuit is broken down into sets of timing paths 2. Path delay calculation :Delay of each path is calculated 3. Path constraints: Path delays are checked to see if timing constraints have been met The purpose of a static timing analysis tool is to perform a static (with no test vectors and simulations) analysis of a circuit and report all the paths that violate some timing constraints. A static timing analysis tool (usually) ignores the functionality of the components and its results are independent of the input vector. Paths whose delay limits the maximum frequency at which the circuit may be operated are referred to as critical paths and are dealt with other tools.The timing constraints must not be violated. After the constraints are met, the static timing data of the initial configuration is the starting point for a great variety of optimizations, performed to enhance the circuits performance for many criterions such as frequency, power, area, signal integrity and others. ------------------------------------------------------------------------------------------------------------------------------SETUP AND HOLD 1.What is setup time? 2.What is Hold time? 3.What is minimum requirement of Clock period? 4.When does hold time violate & how to avoid it? 5.When does setup time violate & how to avoid it? ------------------------------------------------------------------------------------------------------------Setup: amount of time data must be stable at the data pin of FF before the clock capturing edge Hold: amount of time data must remain stable at the data pin of FF after the clock capturing edge In order to meet Setup and Hold time Data should come within the Setup-Hold Window shown.Whenever data arrives out of this window there will be setupand hold violation .

I n Cl k

D 1 Clk 1

D2 Clk 2

HOLD TIME 1.Without Skew Data Launched at D1 will be captured at D2 after a minimum time of (Tclk-q + Tcomo_min ). But this time should not be less than Th,or else there would be Hold Violation. Hold Time Launching Edge Clk1 Setup Time Capturing Edge

Clk2

Setup-Hold Window

Tclk-q + Tcomo_min < Th

--- Hold Violation Data arrived early before Setup-Hold Window

To avoid Hold time violation, Tclk-q + Tcomo_min > Th

------------------------------------------------------------------------------------------------------2.With Skew Skew: Difference in arrival times for different clock signals With Skew :- For Hold requirement To avoid Hold Violation, Treq > Tskew + Th but ---------Tclk_q + Tcomb_min > Tskew + Th

Launching Edge Clk1 Hold Time Setup Time

Clk2

Tskew Th

Setup-Hold Window DataReq

Treq= Tclk_q + T Comb_min SETUP TIME 1.Without Skew Simillarly for setup requirement, Data should come before T-Ts which is nothing but Treq =< (T-Ts) This delay is caused due to (Tclk-q + Tcomb_max) ----Treq = Tclk-q + Tcomb_max Tclk-q + Tcomb_max < T -Ts

Launching Edge Clk1 Hold Time

Capturing Edge

Setup Time

Clk2

Setup-Hold Window T Datareq Ts

Tclk_q + Tcomb_max Tclk_q + Tcomb_max < T Ts Hence T > Tclk_q + Tcomb_max +Ts

For this condition only ,timings meets. So The clock period should be greater than the delay shown on RHS. So ,Fmax=1/Tmin where Tmin > Tclk-q + Tcomo_max+Ts

Tclk-q + Tcomb_max >Treq ,Setup Violation Data arrives after Setup-Hold Window 2.With Skew :- For Setup requirement

To avoid Hold Violation

Launching Edge Clk1 Hold Time Setup Time

Clk2

Setup-Hold Window Tskew Data req Tskew +Tclk-q + Tcomo_max Ts

Tskew +Tclk-q + Tcomo_max < T-Ts Hence T > Tskew +Tclk-q + Tcomo_max +Ts