New Era University College of Engineering and Technology Computer Science Department

Computer Architecture Lecture

Project
Microprocessor Design and Simulation

Rating

Submitted by: Leandro M. Santos Rodel R. Aguinaldo Nieljun Acebes John Ethelbert Terrado Gerard Kristoffer C. Sabado Submitted to: Prof. Gaucho Agregado

Date of Submission: March 6, 2012

Table of Contents
Zero Operand Microprocessor (Cipher) One Operand Microprocessor (Primo) Notes on one operand instructions Two Operand Microprocessor (Ritornare) Three Operand Microprocessor (Ciel) Addressing Modes Main Memory Constructing an instruction in the main memory: Stack Memory Initialization of the processor components during simulation Source Codes ACC ALU AR CU IR MAR MBR MM PC Stack Cipher Primo Ritornare Ciel UML Class Diagrams 2 3 4 5 5 6 8 11 18 18 22 23 23 25 26 49 50 51 52 55 56 57 58 59 60 63

CS241 Computer Architecture LEC Tuesday 8:00am-10:00am

Cipher (Zero Operand Processor)

Diagram of Zero Operand Microprocessor

Assembly POP R1

Meaning R1 = Stack[top element]

PUSH R1

Stack[top element] = R1

ADR DIF MUL DIV INCR DECR

ACC = R1 + R2 ACC = R1 - R2 ACC = R1 * R2 ACC = R1 / R2 ACC = R1 + 1 ACC = R1 - 1

Description Takes the top most element of the stack and sends it to the register R1.Stack pointer is then decremented by 1. Note: R1 may be replaced by any register such as R2. Copies the data from the R1 and sends it on top of the stack. Stack pointer is then incremented by 1. Note: R1 may be replaced by any register such as R2 and ACC. Adds the value of R1 and R2 and sends it to Accumulator Subtracts the value of R1 to R2 and sends it to Accumulator Multiplies the value of R1 and R2 and sends it to Accumulator Divides the value of R1 to R2 and sends it to Accumulator Increments the value at register R1 and sends it to Accumulator Decrements the value at register R1 and sends it to Accumulator

CS241 Computer Architecture LEC Tuesday 8:00am-10:00am

Primo (One Operand Processor)

Diagram of One, Two and Three Operand Microprocessor

Assembly READ [2000] COPY R1

Meaning R1 = [2000] R1 = R2

WRITE [2000] ADR [4000] DIF [4000] MUL [4000]

[2000] = ACC ACC = R1 + R2 [4000] = ACC ACC = R1 + R2 [4000] = ACC ACC = R1 * R2 [4000] = ACC ACC = R1 / R2 [4000] = ACC ACC = R1 + 1 R1 = ACC ACC = R1 - 1 R1 =ACC

DIV [4000] INCR R1 DECR R1

Description Reads the data in address [2000] and copies it to register R1. Copies the value from R2 and send it to R1 Note: COPY command is used exclusively for R1 to R2 and R2 to R1 transferring of data. Reads the data in the Accumulator and sends it to address [2000]. Note: WRITE is exclusively used for sending data from ACC to Main Memory Adds the value of register R1 and R2 and sends it to address [4000]. Note: the parameter of ADR can be changed into a register such as R1 and R2 Subtracts the value of register R1 and R2 and sends it to address [4000]. Note: the parameter of DIF can be changed into a register such as R1 and R2 Multiplies the value of register R1 by R2 and sends it to address [4000]. Note: the parameter of MUL can be changed into a register such as R1 and R2 Divides the value of register R1 by R2 and sends it to address [4000]. Note: the parameter of DIV can be changed into a register such as R1 and R2 Increments the value of register R1 by 1. R1 can be changed in to R2 or an address from the main memory. Decrements the value of register R1 by 1. R1 can be changed in to R2 or an address from the main memory.

CS241 Computer Architecture LEC Tuesday 8:00am-10:00am

Notes on one operand instructions

The one, two and three operand microprocessor shares the same diagram. Take note that in one operand instructions, the Register or address next to ADR, DIF, MUL, DIV are specifying the storage of the final result of the computation of R1 and R2. Example: If I used DIV R2 command and the R1 and R2 has the following value: R1: 5 R2: 1, the value of R2 will be R2 = R1 / R2 R2:5. Take note that INCR command increments the value by 1 and it involves placing the value specified in the operand to increment it by 1. Example: INCR [40], the command increments the value of address [40] by one, so if address [40] has the value of 10.. R1 = [40] R1+=1 ACC = R1 [40] = ACC Final values: ACC: 11 R1: 11 [40]: 11 The same is true with DECR command R1: 10 R1: 11 ACC: 11 [40]: 11

CS241 Computer Architecture LEC Tuesday 8:00am-10:00am

Ritornare (Two Operand Processor)

Assembly READ [2000], [4000] Meaning [2000] = [4000] Description Reads the data in address [4000] and copies it to address [2000]. Note: the parameters of read could be change to accommodate register to register, memory to register data transfer. EX. READ [2000], R1 or READ R2, R1 Adds the value of address [4000] and [3000] then the result is stored at address [4000]. Note: the parameters can be changed into R1 or R2. Subtracts the value of address [4000] to [3000] then the result is stored at address [4000]. Note: the parameters can be changed into R1 or R2. Multiples the value of register R2 by [2000] then the result is stored at register R2. Note: the parameters can be changed into R1 or R2. Divides the value of address R1 by [2000] then the result is stored at register R1. Note: the parameters can be changed into R1 or R2.

ADR [4000], [3000]

[4000] = [4000] + [3000]

DIF [4000], [3000]

[4000] = [4000] - [3000]

MUL R2, [2000]

R2 = R2 * [2000]

DIV R1, [2000]

R1 = R1 / [2000]

Ciel (Three Operand Processor)

Assembly READ [4000], [1000], I Meaning [4000]: [20] [1000]: [50] [20] = [50] Description Reads the data in address [1000] and copies it to address [4000] using indirect memory addressing mode. Note: The last parameter can be changed to specify the type of addressing mode. D Direct if direct is set, its executed the same way as the two operand operation I Indirect as shown in the example, the address contained in the address of the operands will be used and the two operand operation will occur afterwards. O+[value] Offset when registers is used as operands the value is fetch using the operand as base address and the value provided as the offset address. Two operand operations follow afterwards. Adds the value of address [4000] and [3000], the result is stored in address [4000]. Note: The last parameter can be changed to specify the type of addressing mode.

ADR [4000], [3000], I

[4000]: [20] [1000]: [50] [20] = [20] + [50]

CS241 Computer Architecture LEC Tuesday 8:00am-10:00am

Addressing Modes:
Keep in mind that ADR, DIF, MUL, DIV shares the same series of operation but differs at mathematical operation. All of these commands are capable of memory addressing mode similar to the READ command. During different addressing modes, registers are not affected. Only memory addresses are altered during the execution of instruction. An error will occur if both operands are register and an addressing mode Offset or indirect is set. Several examples will be illustrated to show how the different addressing modes work. EX: ADR [40], [20], O+10 The command indicates that an offset of 10 addresses must be applied during the execution of command. By applying the offset the command will have this equivalent two operand command: ADR [50], [30] notice that both the operands address is increased by 10 as indicated by offset of 10. After the offset is applied, the same procedure as two operands executes. If the offset value was set to zero, the effect will be as if the instruction executed is a two operand direct addressing mode operation. Assuming address [40] contains the value 80 and address [20] contains the value 50. [40]: 80 [20]: 50 EX: ADR [40], [20], I This command indicates that Indirect addressing mode should be applied. Referring to the assumption above lets say the value of address [40] is read which gives us the value 80. However, since indirect addressing mode is indicated, we have to treat the value 80, which we read from address [40] as another address so we will have now the address [80] to replace the first operand which is [40]. The same will happen to address [20] since it is an address, it will be replaced by address [50] because it holds the value 50. The same procedure as the two operands operation will occur. Thus giving us the equivalent command of: ADR [80], [50] Thus we can say that a two operand command: ADR [80], [50] will do the same things as the three operand command ADR [40], [20], I.

CS241 Computer Architecture LEC Tuesday 8:00am-10:00am

Keep in mind that when using direct as addressing mode it will treat the command as two operands instruction. Using the previous statements, we can conclude that using the assumed values of address [40] and [20] above, the following commands are all equivalent instructions. ADR [80], [50] ADR [40], [20], I ADR [80], [50], D ADR [80], [50], O+0

CS241 Computer Architecture LEC Tuesday 8:00am-10:00am

Main Memory:
The main memory was given its own class during the program simulation of the microprocessors. The main memory served as the storage of instructions for Zero, One, Two and Three operand instructions. It is also used to store values processed by each instruction. Zero operand is an exception, Zero operand uses stack to store and retrieve value for computations. Here is an example illustration of a portion of the main memory: D/I 0 3 2 4 0 1 0 O/V 1 2 1 9 15 5 1 OT 2 1 1 0 0 1 0 OPR 3 5 6 0 0 1 0 OT 4 1 1 0 0 0 0 OPR 5 1 17 0 0 0 0 AM 6 1 0 0 0 0 0 AV 7 0 0 0 0 0 0

Address 0 1 2 3 4 5

index

Legend:
D/I Data or Instruction the value in this index determines if the contents of the address is a Zero, One, Two or Three operand instruction or it contains data. O/V Operation or Value the value in this index is treated differently depending on the value of D/I. If D/I is set to zero the number at this index is treated as a value. If the value of D/I is an instruction the value of this index is scanned and corresponding operation is executed. OT Operand Type - the value at this index determines if the operand is a register, accumulator or an address. OPR Operand the value at this index is treated differently based on the value of the preceding OT. Take note that OT at index [2] is the operand type for first operand and OPR at index [3] is for first operand as well. OT at index [4] and OPR at index [5] are for second operand. AM Addressing Mode the value determines what addressing mode is to be used. The value in this index is usually ignored except when the value of D/I is set to 3. AV Addressing Value the value in this index is used only by offset addressing mode. It determines how many address should be added to the base address.

CS241 Computer Architecture LEC Tuesday 8:00am-10:00am

List of flags for each index of a memory address

D/I Flags Meaning 0 value 1 one operand 2 two operand 3 three operand 4 zero operand O/V Flags Meaning Flags 0 READ 0 1 ADR 1 2 DIF 2 3 MUL 4 DIV 5 COPY 6 WRITE 7 INCR 8 DECR 9 POP 10 PUSH OT Meaning Register Address Accumulator OPR* AM Flags Meaning Flags Meaning 0 R1 0 Direct 1 R2 1 Indirect 2 Offset

*if the OT is set to register, these are the possible values for OPR. In most cases the value of AV (Addressing value) is ignored except when the AM (addressing mode) is set to offset.

CS241 Computer Architecture LEC Tuesday 8:00am-10:00am

The table below will give you the assembly commands (O/V) available for each type of microprocessor in tabular form.
COMMANDS READ ADR DIF MUL DIV WRITE COPY INCR DECR POP PUSH LEGEND Available Unavailable Number of Operands ZERO ONE TWO THREE

The next table will show which parts of a memory address are being read by each type of microprocessor:
Index in a memory cell No. of Operands ZERO ONE TWO THREE D/I O/V OT OPR OT OPR AM AV

LEGEND Being Read Ignored during decoding * As mentioned earlier, we read the value in AV only during the offset addressing mode which is used by three operand instructions.

CS241 Computer Architecture LEC Tuesday 8:00am-10:00am

10

Constructing an instruction in the main memory:

Below is a table with the default instructions with translation to assembly code, in the main memory. It will serve as a guide in placing your own instruction.
Address 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 CS241 Computer Architecture LEC Tuesday 8:00am-10:00am 1 1 1 1 1 1 1 1 1 1 1 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 3 3 3 0 5 0 1 2 1 4 7 8 6 3 0 0 2 0 1 1 1 1 2 2 2 2 3 3 3 3 4 4 4 4 0 0 0 Instruction 1 79 0 0 1 0 1 73 0 1 90 0 0 1 0 0 1 0 0 1 0 1 78 0 0 1 0 1 79 0 1 78 0 1 69 1 0 0 1 0 0 1 1 78 0 1 74 1 0 0 1 0 1 0 1 74 0 1 74 1 0 0 1 0 1 0 1 74 0 1 75 1 0 1 1 0 1 0 1 74 0 1 75 1 0 1 1 0 1 0 1 74 0 1 69 1 1 85 1 1 69 1 0 0 0 0 0 0 0 0 0 0 0 79 75 0 0 75 70 0 1 75 70 0 1 74 70 0 0 74 70 0 0 75 86 73 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 5 Assembly code READ [79] COPY R2 READ [73] ADR [90] DIF R2 ADR R2 DIV R2 INCR [78] DECR R2 WRITE [79] MUL [78] READ [69], [79] READ R1, [75] READ R2, R1 READ [78], R1 ADR [74], [75] ADR R1, [70] ADR R2, R1 ADR [74], R2 DIF [74], [75] DIF R1, [70] DIF R2, R1 DIF [74], R2 MUL [75], [74] MUL R2, [70] MUL R2, R1 MUL [74], R1 DIV [75], [74] DIV R2, [70] DIV R2, R1 DIV [74], R1 READ [69], [75], D READ [85], [86], I READ [69], [73], O+5 11

34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68

3 0 3 0 3 0 3 0 3 0 3 0 3 0 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 4 3 4 3 4 3 4 3 4 3 4 3 4 3 4 3 4 3 4 4 9 4 9 4 2 4 3 4 8 4 10 4 7 4 10

0 0 0 1 1 1 0 1 1 0 0 1 1 0 1 1 0 1 1 0 0 1 1 0 1 1 0 0 0 0 0 0 0 0 2

0 1 1 90 73 69 1 78 79 0 1 88 84 1 69 74 1 78 79 0 1 88 84 1 69 74 1 0 1 0 0 0 0 1 0

1 1 1 0 0 0 0 1 0 1 0 1 0 1 1 0 1 1 0 1 0 1 0 1 1 0 1 0 0 0 0 0 0 0 0

87 72 69 0 0 1 0 70 0 72 0 84 0 80 70 0 72 70 0 72 0 84 0 82 70 0 72 0 0 0 0 0 0 0 0

1 2 0 1 2 0 0 0 0 0 0 1 1 1 2 2 2 0 0 0 0 1 1 1 2 2 2 0 0 0 0 0 0 0 0

0 2 0 0 4 0 0 0 0 0 0 0 0 0 2 2 2 0 0 0 0 0 0 0 2 2 2 0 0 0 0 0 0 0 0

READ R1, [87], I READ R2, [72], O+2 READ R2, [69], D READ [90], R1, I READ [73], R1, O+4 READ [69], R2, D READ R2, R1, D MUL [78], [70], D MUL [79], R1, D MUL R1, [72], D MUL R2, R1, D MUL [88], [84], I MUL [84], R1, I MUL R2, [80], I MUL [69], [70], O+2 MUL [74], R1, O+2 MUL R2, [72], O+2 DIV [78], [70], D DIV [79], R1, D DIV R1, [72], D DIV R2, R1, D DIV [88], [84], I DIV [84], R1, I DIV R2, [82], I DIV [69], [70], O+2 DIV [74], R1, O+2 DIV R2, [72], O+2 POP R1 POP R2 DIF MUL DECR PUSH R1 INCR PUSH ACC

CS241 Computer Architecture LEC Tuesday 8:00am-10:00am

12

Zero operand instruction

Zero operand instructions are created in a tricky manner. Some commands use up to forth index in the memory cell but most uses only 2 indexes. Commands such as POP and PUSH read the values up to forth index. See the following examples: The shaded parts are the indexes that are being read by the decoder. 4 3 0 0 0 0 0 0
Sample zero operand MUL instruction

MUL Notice that in zero operand instruction, it only considers the first two values in the index. Since the MUL command of zero operand requires no parameter (operand) it is sufficient. 4 7 0 1 0 0 0 0
Sample zero operand INCR instruction

INCR In this zero operand instruction, it only considers the first two values in the index. The INCR command of zero operand requires no parameter (operand). It will always increment the value at register R1 regardless of the values that follows the first two indexes.

4 10 2 0 0 0 0 0
Sample zero operand PUSH instruction

PUSH ACC In PUSH zero operand instruction, it only considers the first three values in the index. Since the PUSH command of zero operand requires one parameter. In this case we used ACC. Another PUSH command requires up to 4 indexes of values, in this case the PUSH command will use the value from a register such as R1 and R2 look at another example instruction below. 4 10 0 0 0 0 0 0
Sample zero operand PUSH instruction

PUSH R1 It used for indexes to decode the instruction. Since the 3rd index will indicate that it will use register and the forth value will indicate what register is to be used by PUSH command.

CS241 Computer Architecture LEC Tuesday 8:00am-10:00am

13

4 9 0 1 0 0 0 0
Sample zero operand POP instruction

POP R2 In here POP command uses a register to POP a value from stack. It will require us to use three indexes. In this case, the form is a little odd compared to the other operands. It uses the first two indexes to determine the number of operands and the command to be performed. The fourth index checks which register to be used during POP. Notice how the decoder deliberately skipped the third index. It was made like this since the POP command will always have a register as its operand. See the command list above to review the rules in the commands.

One operand instruction:

In one operand instruction the values that are taken in to consideration are the shaded parts. 1 0 1 79 0 0 0 0
Sample one operand instruction

The first value indicates that it is a one operand instruction because of the value 1. The next value which is 0 indicates the operation which is READ. The next value which is 1 indicates that the first operand is an address from the memory. The value that follows it which is 79 indicates that location of the address mentioned in the previous value. Translating it to assembly code we get: READ [79] The rest of the values which consist of 0, 0, 0, 0 are all ignored since this is a one operand instruction. Any value placed in there doesnt affect the instruction.

CS241 Computer Architecture LEC Tuesday 8:00am-10:00am

14

Two Operand Instructions:

2 1 1 74 0 1 0 0
Sample two operand instruction

The value in the first cell which is 2 indicates it is two operand instructions. The next value 1 tells us that it is an ADR operation. The next value 1 indicates that the first operand is an address from the main memory. The value 74 tells us the address of the first operand. The next value which is 0 indicates that the second operand is a register. The next value 1 says it is register R2. The rest of the value which is 0 and 0 are ignored as seen in the previous tables.

Three Operand instructions:

D/I Address 0 0 3 O/V OT OPR OT OPR AM AV 1 2 3 4 5 6 7 2 1 5 1 1 1 0 index

Using a portion of memory shown above we will translate this into assembly code and describe its function. Using the flags above we get the equivalent Assembly code: DIF [5], [1], I Description: The instruction subtracts the value of address [5] to the value of address [1] using indirect addressing mode. The main memory is provided with default instructions for simulation, but it is possible to alter the memory contents to create your own assembly commands provided that the rules are followed. The illustration above demonstrates how an instruction and a value are indistinguishable in the memory. There is a flag (which is the value at index D/I) that determines the difference of an instruction and value. During memory write which is executed by the MBR, the MBR scans if the address contains either a value or an instruction. On the event that an address contains instruction, the memory write is aborted. For further details refer to the source code.

CS241 Computer Architecture LEC Tuesday 8:00am-10:00am

15

The default main memory has address starting from 00-90. But it is possible to extend the size by adding an array of values since the main memory is simulated by two dimensional array. The following address are reserved for each instruction for the sake convenience but can be altered if necessary: 00 - 10 contains One operand instructions 11- 30 contains Two operand instructions 31 60 contains Three operand instructions 61 - 68 contains Zero operand instructions. 69 79 contains values from numbers 0 10 80 90 contains addresses from 69 79 Take note that the values at 80 90 is actually used to referenced another memory address (as you can see they point to address which contains values) but these address can also be treated as actual values. As mentioned in the different addressing mode they can also be treated as values used for computations. This is the default contents of the main memory:
00| 01| 02| 03| 04| 05| 06| 07| 08| 09| 10| 11| 12| 13| 14| 15| 16| 17| 18| 19| 20| 21| 22| 23| 24| 25| 26| 27| 28| 29| 30| 31| 32| [1] [1] [1] [1] [1] [1] [1] [1] [1] [1] [1] [2] [2] [2] [2] [2] [2] [2] [2] [2] [2] [2] [2] [2] [2] [2] [2] [2] [2] [2] [2] [3] [3] [0] [5] [0] [1] [2] [1] [4] [7] [8] [6] [3] [0] [0] [0] [0] [1] [1] [1] [1] [2] [2] [2] [2] [3] [3] [3] [3] [4] [4] [4] [4] [0] [0] [1] [0] [1] [1] [0] [0] [0] [1] [0] [1] [1] [1] [0] [0] [1] [1] [0] [0] [1] [1] [0] [0] [1] [1] [0] [0] [1] [1] [0] [0] [1] [1] [1] [79] [1] [73] [90] [1] [1] [1] [78] [1] [79] [78] [69] [0] [1] [78] [74] [0] [1] [74] [74] [0] [1] [74] [75] [1] [1] [74] [75] [1] [1] [74] [69] [85] [0] [0] [0] [0] [0] [0] [0] [0] [0] [0] [0] [1] [1] [0] [0] [1] [1] [0] [0] [1] [1] [0] [0] [1] [1] [0] [0] [1] [1] [0] [0] [1] [1] [0] [0] [0] [0] [0] [0] [0] [0] [0] [0] [0] [79] [75] [0] [0] [75] [70] [0] [1] [75] [70] [0] [1] [74] [70] [0] [0] [74] [70] [0] [0] [75] [86] [0] [0] [0] [0] [0] [0] [0] [0] [0] [0] [0] [0] [0] [0] [0] [0] [0] [0] [0] [0] [0] [0] [0] [0] [0] [0] [0] [0] [0] [0] [0] [0] [1] [0] [0] [0] [0] [0] [0] [0] [0] [0] [0] [0] [0] [0] [0] [0] [0] [0] [0] [0] [0] [0] [0] [0] [0] [0] [0] [0] [0] [0] [0] [0] [0] [0]

CS241 Computer Architecture LEC Tuesday 8:00am-10:00am

16

33| 34| 35| 36| 37| 38| 39| 40| 41| 42| 43| 44| 45| 46| 47| 48| 49| 50| 51| 52| 53| 54| 55| 56| 57| 58| 59| 60| 61| 62| 63| 64| 65| 66| 67| 68| 69| 70| 71| 72| 73| 74| 75| 76| 77| 78| 79| 80| 81| 82| 83| 84| 85| 86| 87| 88| 89| 90|

[3] [3] [3] [3] [3] [3] [3] [3] [3] [3] [3] [3] [3] [3] [3] [3] [3] [3] [3] [3] [3] [3] [3] [3] [3] [3] [3] [3] [4] [4] [4] [4] [4] [4] [4] [4] [0] [0] [0] [0] [0] [0] [0] [0] [0] [0] [0] [0] [0] [0] [0] [0] [0] [0] [0] [0] [0] [0]

[0] [0] [0] [0] [0] [0] [0] [0] [3] [3] [3] [3] [3] [3] [3] [3] [3] [3] [4] [4] [4] [4] [4] [4] [4] [4] [4] [4] [9] [9] [2] [3] [8] [10] [7] [10] [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [69] [70] [71] [72] [73] [74] [75] [76] [77] [78] [79]

[1] [0] [0] [0] [1] [1] [1] [0] [1] [1] [0] [0] [1] [1] [0] [1] [1] [0] [1] [1] [0] [0] [1] [1] [0] [1] [1] [0] [0] [0] [0] [0] [0] [0] [0] [2] [0] [0] [0] [0] [0] [0] [0] [0] [0] [0] [0] [0] [0] [0] [0] [0] [0] [0] [0] [0] [0] [0]

[69] [0] [1] [1] [90] [73] [69] [1] [78] [79] [0] [1] [88] [84] [1] [69] [74] [1] [78] [79] [0] [1] [88] [84] [1] [69] [74] [1] [0] [1] [0] [0] [0] [0] [1] [0] [0] [0] [0] [0] [0] [0] [0] [0] [0] [0] [0] [0] [0] [0] [0] [0] [0] [0] [0] [0] [0] [0]

[1] [1] [1] [1] [0] [0] [0] [0] [1] [0] [1] [0] [1] [0] [1] [1] [0] [1] [1] [0] [1] [0] [1] [0] [1] [1] [0] [1] [0] [0] [0] [0] [0] [0] [0] [0] [0] [0] [0] [0] [0] [0] [0] [0] [0] [0] [0] [0] [0] [0] [0] [0] [0] [0] [0] [0] [0] [0]

[73] [87] [72] [69] [0] [0] [1] [0] [70] [0] [72] [0] [84] [0] [80] [70] [0] [72] [70] [0] [72] [0] [84] [0] [82] [70] [0] [72] [0] [0] [0] [0] [0] [0] [0] [0] [0] [0] [0] [0] [0] [0] [0] [0] [0] [0] [0] [0] [0] [0] [0] [0] [0] [0] [0] [0] [0] [0]

[2] [1] [2] [0] [1] [2] [0] [0] [0] [0] [0] [0] [1] [1] [1] [2] [2] [2] [0] [0] [0] [0] [1] [1] [1] [2] [2] [2] [0] [0] [0] [0] [0] [0] [0] [0] [0] [0] [0] [0] [0] [0] [0] [0] [0] [0] [0] [0] [0] [0] [0] [0] [0] [0] [0] [0] [0] [0]

[5] [0] [2] [0] [0] [4] [0] [0] [0] [0] [0] [0] [0] [0] [0] [2] [2] [2] [0] [0] [0] [0] [0] [0] [0] [2] [2] [2] [0] [0] [0] [0] [0] [0] [0] [0] [0] [0] [0] [0] [0] [0] [0] [0] [0] [0] [0] [0] [0] [0] [0] [0] [0] [0] [0] [0] [0] [0]

CS241 Computer Architecture LEC Tuesday 8:00am-10:00am

17

Stack Memory:
Stack memory is a special type of memory used by zero operand instruction. Unlike the main memory which is implemented using two dimensional arrays the stack memory was implemented using linked list. Stack memory is dynamically expanding which means its size can change in contrast to the array which cannot. POP and PUSH commands alters the size of the stack memory.

These are the default values of stack memory:

13| 12| 11| 10| 09| 08| 07| 06| 05| 04| 03| 02| 01| 00| 24 9 15 10 9 8 7 6 5 4 3 2 1 0

0 at stack address [0] being the first value inserted and 24 at stack address [13] being the last value inserted.

Initialization of the processor components during simulation:

During the simulation, components of the microprocessors are defined in a class. Each class requires an object to be created in order to use its functions. However, some classes require another object of a class as parameters during construction which are defined in the constructor.

Here are the list of classes and what they do:

ACC represents the Accumulator. It serves as the storage of temporary result in ALU ALU represents the Algorithmic Logic Unit. It handles all the mathematical computations during the simulation. AR (ALU register) represents a register being used by ALU as operands during mathematical computations. CU represents the Control Unit. It sends signals to different components of the microprocessor in order to perform the instruction correctly. Data transfers between processor components and processing of

CS241 Computer Architecture LEC Tuesday 8:00am-10:00am

18

ALU are handled by this class. A decoder is included in this class which translates the instruction being executed. IR represents the instruction register. It holds the address of the current instruction being executed from the main memory. MAR represents the Memory Address Register. It holds the address of an instruction or data that needs to be fetched from the main memory. MBR represents the Memory Buffer Register. It holds data coming from the main memory and sends distributes it to the other components of the microprocessor MM or Main memory represents the storage of data and instruction. Stack represents a stack which is used in stack operations. Take a look at the constructors of these classes:
ALU(AR r1, AR r2, ACC acc) CU(PC pc, IR ir, MAR mar, ALU alu, MBR mbr, ACC acc, Stack stack) MBR(MM mem)

Notice that these classes take other components of the processor as its parameters. It was designed that way to ensure that all the necessary components of processor are created before creating another component whose task requires the presence of other component.

Let us take ALU as an example: ALU for mathematical operations requires 2 operands in the form of registers and an ACC which is a special register to store results of computations of ALU.

Illustration of ALUs constructor

Notice that the ALU is like a piece of the puzzle, with two ends fitting to an ACC object and two AR objects. Imagine if we created an object from ALU without creating an ACC and a method was called to add R1 and R2 where will the resultant value go? An error would occur if thats the case.

CS241 Computer Architecture LEC Tuesday 8:00am-10:00am

19

Another example is the MBR. If we created MBR without the presence of MM, the MBR wont be able to know where to fetch the instruction being pointed out by MAR.

Illustration of MBRs constructor

Similar to an ALU object, MBR requires yet another object which in this case is MM object before an MBR object is created.

Now for the CU object the graphical representation of the constructor should look like this.

Illustration of CUs constructor

CS241 Computer Architecture LEC Tuesday 8:00am-10:00am

20

Notice that the constructor of the ALU and MBR gives the CU the connection it needs to interact with MM, ACC and two AR. The very reason the constructors of MBR and ALU require the other components of the process is because they are an integral part of the larger design, which in this case is the CU. As mentioned earlier the CU provides connections between components of microprocessor, so the IR, PC, MAR, MBR, Stack and ALU can also interact with one another because of CU. It is also worth mentioning that the CU has another constructor which looks like this.
CU(PC pc, IR ir, MAR mar, ALU alu, MBR mbr, ACC acc)

Notice that the constructor is missing the Stack. This is actually a constructor which can operate one, two and three Operand instructions. The constructor shown above (which includes Stack in its parameters) is capable of handling zero, one, two and three operands.

CS241 Computer Architecture LEC Tuesday 8:00am-10:00am

21