EE115C

Digital Electronic Circuits

Lecture 2:
MOS Behavior
EE115C 2
Metal Oxide Semiconductor Field Effect Transistor
Cross Sectional View
n+ n+ p+
p substrate
Source
Drain
Body Gate
Poly Si
SiO
2
SiO
2

Artists Rendition
EE115C 3
n+ n+ p+
p substrate
Source
Drain
Body Gate
NMOS
S
G
D
Analog Representation
S
G
D
Digital Representation
nMOS Cross-Section and Symbols
EE115C 4
p+ p+ n+
n substrate
Source
Drain
Body
Gate
PMOS
S
G
D
Analog Representation
D
G
S
Digital Representation
pMOS Cross-Section and Symbols
EE115C 5
Which is Source, which is Drain ?
1.0 V 1.0 V 0.0 V 1.0 V 1.0 V 0.0 V
Current flow
Carrier (electron) flow
Source Source Drain Drain
EE115C 6
Long Channel Vs Short Channel
Long channel transistors
older technologies, long Ls
Short channel transistors
new, deep submicron technologies, short Ls
operation more complicated
many 2
nd
order effects become pronounced

n n p+
p substrate
Source
Drain
Body Gate
NMOS
L
EE115C 7
nMOSFET Basic Operation
Long Channel Devices
Consider V
s
=V
d
and V
g
is increased
Electron are stripped away from atoms in the source and drain region as well
as deep in the substrate and attracted to the channel. Simultaneously, holes
are pushed away from the surface and into the substrate
A conducting channel of electrons is formed
n+ p+
p substrate
Source Drain
Body
Gate
V
s

V
g
V
d

n+
Carrier (electron) flow
Current flow
Volts
Threshold Voltage, V
T
Channel a.k.a.
Inversion Layer
V
T
EE115C 8
n
+
n
+
p -substrate
D
S
G
B
x L

I
D
Linear (Triode) Operation
Channel is formed
The application of a potential between the source and the drain
causes current to flow
The shape of the channel region changes
it becomes more tapered

( )
2
'
2
DS
DS n ox GS T DS
n
k
W V
I C V V V
L

l
l
=
l
l
EE115C 9
Pinch-off Saturation
For V
DS
= V
GS
V
T
, no mobile charge at Drain
The channel is said to be pinched off
I
DS
does not increase anymore
Pinch Off
n+ n+
S
G
V
GS
D
V
DS
> V
GS
- V
T
V
GS
- V
T
+
-

( )
2
'
1
2
DS n ox GS T
n
k
W
I C V V
L
=
EE115C 10
Channel Length Modulation
The Pinch-off point moves as a function of V
DS
I
DS
changes as a function of V
DS


V
DS

-V
A
= -1/
I
D

V
DSAT
V
Drop

V
DSAT
=V
GS
-V
T

V
Drop
= V
DS
-V
DSAT

L

( ) ( )
2
'
1 1
1 where
2
DS n ox GS T DS
n
k
W
I C V V V
L L
=
EE115C 11
Body Effect (1)
( )
0
2 2 where ln
A
T T SB F F F T
i
N
V V V
n
= =
Threshold Voltage
2
F
is approximately 0.6V for p-type substrates
is the body factor
V
T0
is approximately 0.45V for our process
So far, assumed that V
B
= V
S
If V
SB
> 0
More e

required to fill in the holes of the depletion region

In other words, V
T
is higher
So, Body also controls I
DS
called Back Gate
EE115C 12
Body Effect (2)
-2.5 -2 -1.5 -1 -0.5 0
0.4
0.45
0.5
0.55
0.6
0.65
0.7
0.75
0.8
0.85
0.9
V
BS
(V)
V
T

(
V
)
V
T0
reverse body bias

EE115C 13
Long Channel MOS Modes of Operation
Cutoff:
V
GS
< V
T
Resistive:
V
GS
> V
DS
+ V
T
Saturation:
V
T
< V
GS
< V
DS
+ V
T

( )
(

=
2
2
DS
DS T GS n D
V
V V V
L
W
k I

( )
2
2
T GS
n
D
V V
L
W k
I =

0 =
D
I
EE115C 14
Quadratic
Relationship
0 0.5 1 1.5 2 2.5
0
1
2
3
4
5
6
x 10
-4
V
GS
= 2.5 V
V
GS
= 2.0 V
V
GS
= 1.5 V
V
GS
= 1.0 V
Resistive Saturation
V
DS
= V
GS
- V
T

V
DS
(V)
I
D

(
A
)

Long Channel MOS Modes of Operation
EE115C 15
Long Channel MOS: Model for Manual Analysis
S

D

G

I
D
( )
2
'
2
DS
D n GS T DS
V
W
I k V V V
L
l
l
=
l
l
l
( ) ( )
'
2
1
2
n
D GS T DS
k
W
I V V V
L
=
( )
F SB F T T
V V V 2 2
0
+ + =
V
DS
> V
GS
V
T

V
DS
< V
GS
V
T
with

EE115C 16
Velocity Saturation

Threshold Variations

Sub-threshold Conduction

Short Channel Effects
EE115C 17
Velocity Saturation
(V/m)

c
= 1.5

n



(

m

/
s
)


sat
= 10
5
Constant mobility
(slope = )
Constant velocity
Carrier velocity saturates due to carrier scattering effects
EE115C 18
Velocity Saturation : I
D
Vs V
DS
I
D
Long-channel device
Short-channel device
V
DS
V
DSAT
V
GS
- V
T
V
GS
= V
DD
EE115C 19
Velocity Saturation: I
D
versus V
GS

0 0.5 1 1.5 2 2.5
0
1
2
4
5
6
x 10
-4
Long Channel
Short Channel
quadratic
linear
quadratic
V
GS
(V)
I
D

(
A
)

3
EE115C 20
Modeling Velocity Saturation
c
n

+

=
1
Velocity saturation model #1
sat
=
for
c
for
c
n
=
Velocity saturation model #2
sat n c
= =
for
c
for
c
Leads to
complicated
MOS equations

Simpler MOS
equations

sat
DSAT c
n
L
V L

=
If V
DS
> V
DSAT
, carrier velocity saturates at v
sat
EE115C 21
How to Determine the Region of Operation
If V
DS
< V
DSAT
Carriers are moving slower than
sat
i.e. not velocity saturated
V
DS
< V
GS
V
T
Linear
V
DS
> V
GS
V
T
Pinch-off Saturation
i.e. no more free carriers at Drain

If V
DS
> V
DSAT
Carriers are velocity saturated
V
DSAT
> V
GS
V
T
Pinch-off Saturation
Note: Pinch off occurs before velocity saturation, so call it pinch off saturation
V
DSAT
< V
GS
V
T
Velocity Saturation
EE115C 22
Regions of Operation
Linear
Relationship
-4
0 0.5 1 1.5 2 2.5
0
0.5
1
1.5
2
2.5
x 10
Velocity
Saturation
V
DS
(V)
I
D

(
A
)

V
DS
= V
GT
V
DSAT
= V
GT
Pinch-off Saturation
Linear
V
DS
= V
DSAT
Define V
GT
= V
GS
V
T
V
DSAT
= L
c
EE115C 23
B

D

G

I
D
S

( )
DS GT D
V
V
V V
L
W
k I +
|
|
.
|

\
|
= 1
2
'
2
min
min
for V
GT
0: I
D
= 0
with V
min
= min (V
GT
, V
DS
, V
DSAT
)

for V
GT
0:

define V
GT
= V
GS
V
T
A Unified Model for Manual Analysis
Sat Lin V-sat
EE115C 24
Manual Analysis Model versus SPICE
0 0.5 1 1.5 2 2.5
0
0.5
1
1.5
2
2.5
x 10
-4
V
DS
(V)
I
D

(
A
)

Velocity
Saturated
Linear
Saturated
V
DSAT
=V
GT
V
DS
=V
DSAT
V
DS
=V
GT
EE115C 25
NMOS Transistor I-V Characteristics:
Long Channel vs. Short Channel (Real Data)
90nm device, constant W/L ratio
Short Channel: W/L = 480nm/100nm
Long Channel: W/L = 2.4m/0.5m
V
GS
=1V
V
GS
=0.8V
V
GS
=0.6V
V
GS
=0.4V
L=500nm
L=100nm
gpdk090
EE115C 26
Sub-Threshold Conduction: I
D
versus V
GS

0 0.5 1 1.5 2 2.5
0
1
2
4
5
6
x 10
-4
Long Channel
Short Channel
quadratic
linear
quadratic
V
GS
(V)
I
D

(
A
)

3
EE115C 27
Sub-Threshold Conduction
Typical values for S:
60 100 mV/decade
The Slope Factor
ox
D
nkT
qV
D
C
C
n e I I
GS
+ =1 , ~
0
S is V
GS
for I
D2
/I
D1
=10
0 0.5 1 1.5 2 2.5
10
-12
10
-10
10
-8
10
-6
10
-4
10
-2
V
T

Linear
Exponential
Quadratic
V
GS
(V)
I
D

(
A
)

EE115C 28
V
DS
from 0 to 0.5V
|
|
.
|

\
|
=

kT
qV
nkT
qV
D
DS GS
e e I I 1
0
Sub-Threshold I
D
vs. V
GS
I
D
V
GS
EE115C 29
Sub-Threshold I
D
vs. V
DS

( )
DS
kT
qV
nkT
qV
D
V e e I I
DS GS
+
|
|
.
|

\
|
=

1 1
0
V
GS
from 0 to 0.3V
I
D
V
DS
EE115C 30
V
T
L
Long-channel threshold
Threshold as a function of
channel length (for low V
DS
)
V
DS

V
T
Threshold Variations
Low V
DS
threshold
Drain induced barrier lowering
(DIBL) (for low L)
EE115C 31
A PMOS Transistor
-2.5 -2 -1.5 -1 -0.5 0
-1
-0.8
-0.6
-0.4
-0.2
0
x 10
-4
Assume all variables negative!
V
GS
= -1.0V
V
GS
= -1.5V
V
GS
= -2.0V
V
GS
= -2.5V
V
DS
(V)
I
D

(
A
)