Documente Academic
Documente Profesional
Documente Cultură
1824
The University of Manchester
Coprocessors
t Outline: r the ARM coprocessor interface r oating-point support r MOVE coprocessor r CP15, CP14
Coprocessors v4 1
MANCHEstER
1824
The University of Manchester
Coprocessors
t Outline: the ARM coprocessor interface r oating-point support r MOVE coprocessor r CP15, CP14
Coprocessors v4 2
MANCHEstER
1824
The University of Manchester
Coprocessors
through coprocessors
r coprocessors have:
private registers and data types their own interpretation of instructions
r Example coprocessors:
hardware oating point - the VFP10 on-chip cache and MMU control application specic (e.g. MOVE)
Coprocessors v4 3
MANCHEstER
1824
The University of Manchester
Coprocessor instructions
Coprocessors v4 4
MANCHEstER
1824
The University of Manchester
Coprocessor instructions
t Coprocessor data processing instructions 31 28 27 24 23 20 19 16 15 12 11 8 7 5 4 3 0 cond 1 1 1 0 Cop1 CRn CRd CP# Cop2 0 CRm
CDP{<cond>} Pcp, Cop1, CRd, CRn, CRm, Cop2
t CP# species the coprocessor number: r it performs the operation specied by Cop1 and Cop2 on data in CRn and CRm, putting the result in CRd r other interpretations are possible!
Coprocessors v4 5
MANCHEstER
1824
The University of Manchester
Coprocessor instructions
LDC{<cond>}{L} Pcp, CRd, <addressing mode> STC{<cond>}{L} Pcp, CRd, <addressing mode>
2005 PEVEIT Unit ARM System Design Coprocessors v4 6
MANCHEstER
1824
The University of Manchester
Coprocessor instructions
t Coprocessor register transfer instructions 31 28 27 24 23 21 20 19 16 15 12 11 8 7 5 4 3 0 cond 1 1 1 0 Cop2 L CRn Rd CP# Cop2 1 CRm
load from coprocessor/store to coprocessor
MRC{<cond>} Pcp, Cop1, Rd, CRn, CRm{, Cop2} MRC{<cond>} Pcp, Cop1, Rd, CRn, CRm{, Cop2}
Coprocessors v4 7
MANCHEstER
1824
The University of Manchester
Coprocessor instructions
r move a 64-bit value between the coprocessor and ARM r e.g. FMDRR Dm, Rd, Rn
Floating point 64-bit move Rd := lower half of Dm Rn := upper half of Dm
Coprocessors v4 8
MANCHEstER
1824
The University of Manchester
Coprocessor instructions
t Later ARMs (from v5) also have: r CDP2 r LDC2/STC2 r MCR2/MCR2 r MCRR2/MRCC2 t These are the same as above except: r they use the former NV (1111) condition r they are always, unconditionally, executed
Coprocessors v4 9
MANCHEstER
1824
The University of Manchester
Coprocessor mnemonics
e.g.
MCR
Coprocessors v4 10
MANCHEstER
1824
The University of Manchester
Coprocessor interface
They:
r watch the instruction trafc on the bus r copy instructions into a pipeline
which mimics ARMs instruction pipeline
Coprocessors v4 11
MANCHEstER
1824
The University of Manchester
Coprocessor interface
t Issues: r not all instructions entering the ARM pipeline are executed
those following a branch are not
Coprocessors v4 12
MANCHEstER
1824
The University of Manchester
Coprocessor interface
coprocessor instruction ARM has identied a coprocessor instruction and wishes to execute it
Coprocessors v4 13
MANCHEstER
1824
The University of Manchester
Coprocessor interface
t Interface timing r shows coprocessor busy, then available mclk ~CPI CPA CPB sample copro. busy
~CPI 1 0 0 0 CPA 1 0 0 CPB 1 0 Meaning Not a (taken) coprocessor operation. No coprocessor recognises this operation Coprocessor may accept instruction in future Coprocessor committed to operation
copro. commit
Action Do nothing Illegal instruction trap Stall pipeline Coprocessor operation
Coprocessors v4 14
MANCHEstER
1824
The University of Manchester
Coprocessors
t Outline: r the ARM coprocessor interface oating-point support r MOVE coprocessor r CP15, CP14
Coprocessors v4 15
MANCHEstER
1824
The University of Manchester
r value = (-1)S x 1.fraction x 2(exponent-127) t double precision: 31 30 S 31 fraction (least signicant part) 20 19 exponent fraction (most signicant part) 0 0
Coprocessors v4 16
MANCHEstER
1824
The University of Manchester
t Floating-point instructions r map into the coprocessor instruction space r will use coprocessor if present r otherwise trap into software emulator t Floating-point library r will not use coprocessor even if present r faster than software emulator r can be called from Thumb code
Thumb has no coprocessor instructions
2005 PEVEIT Unit ARM System Design Coprocessors v4 17
MANCHEstER
1824
The University of Manchester
Coprocessors v4 18
MANCHEstER
1824
The University of Manchester
t VFP10 is coprocessor number 10 r also CP11 if double precision implemented t IEEE 754 subset r supports single (32-) and (possibly) double (64-) bit fp formats r most functions in hardware
does not support remainder binary decimal round-to-integer
Coprocessors v4 19
MANCHEstER
1824
The University of Manchester
VFP architecture
S0 S2 S4 S6 S8 S10 S12 S14 S16 S18 S20 S22 S24 FPSID FPSCR FPEXC S26 S28 S30 S1 S3 S5 S7 S9 S11 S13 S15 S17 S19 S21 S23 S25 S27 S29 S31 D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D variants
r Each S register can hold: a single precision oat or a 32-bit integer r Can process short vectors as well as scalars
up to 8 single precision up to 4 double precision
Coprocessors v4 20
MANCHEstER
1824
The University of Manchester
r Floating point system ID register (FPSID) 31 24 23 22 21 20 19 16 15 8 7 4 3 0 implementor SW format SNG architecture part number variant revision r Floating point status and control register (FPSCR) 31 30 29 28 27 25 24 23 22 21 20 19 18 16 15 13 12 11 10 9 8 7 5 4 3 2 1 0 N Z C V 0 0 0 FZ RMODE STRIDE 0 len 0 0 0 IXE UFEOFE DZE IOE 0 0 0 IXC UFCOFC DZC IOC
ags, rounding, vector length, exception control
Coprocessors v4 21
MANCHEstER
1824
The University of Manchester
t Load and store from/to memory r includes some multiple register moves t Transfers from/to ARM registers t Copy/negate/absolute value
Add/subtract/multiply/divide/square root
r single values or short vectors t Comparisons t Floating point/integer conversion
Coprocessors v4 22
MANCHEstER
1824
The University of Manchester
31 28 27 24 23 20 19 16 15 12 11 8 7 4 3 0 cond 1 1 1 0 0 D 1 1 Sn Sd 1 0 1 0 N 0 M 0 Sm r {D, N, M} are LSBs of register speciers t Floating point Divide, Double precision
FDIVD{<cond>} <Dd>, <Dn>, <Dm>
31 28 27 24 23 20 19 16 15 12 11 8 7 4 3 0 cond 1 1 1 0 1 0 0 0 Dn Dd 1 0 1 1 0 0 0 0 Dm
2005 PEVEIT Unit ARM System Design Coprocessors v4 23
MANCHEstER
1824
The University of Manchester
31 28 27 24 23 22 21 20 19 16 15 12 11 8 7 cond 1 1 0 1 U D 0 1 Rn Sd 1 0 1 0
0 offset
31 28 27 25 24 23 22 21 20 19 16 15 12 11 8 7 cond 1 1 0 P U 0 W 0 Rn Dd 1 0 1 1
0 offset
Coprocessors v4 24
MANCHEstER
1824
The University of Manchester
31 28 27 24 23 20 19 16 15 12 11 8 7 6 5 4 3 0 cond 1 1 1 0 0 0 0 0 Sn Rd 1 0 1 0 N 0 0 1 0 0 0 0
MANCHEstER
1824
The University of Manchester
Coprocessors
t Outline: r the ARM coprocessor interface r oating-point support MOVE coprocessor r CP15, CP14
Coprocessors v4 26
MANCHEstER
1824
The University of Manchester
MOVE
coprocessor
t A video encoding acceleration coprocessor r to accelerate Motion Estimation (e.g. MPEG) r implements an 8 x 8 byte block buffer r major function is SAD (Sum of Absolute Differences)
compare 8 x 8 pixel blocks
Coprocessors v4 27
MANCHEstER
1824
The University of Manchester
Coprocessors
t Outline: r the ARM coprocessor interface r oating-point support r MOVE coprocessor CP15, CP14
Coprocessors v4 28
MANCHEstER
1824
The University of Manchester
CP15, CP14
functions
r outside the memory space t CP15 is the system control coprocessor r cache, MMU, paging, etc. control and status r more details in Memory Hierarchy Support section t CP14 is the debug coprocessor r breakpoint, watchpoint, etc. control and status r more details in System Development section
2005 PEVEIT Unit ARM System Design Coprocessors v4 29
MANCHEstER
1824
The University of Manchester
t Look further into ARM system software issues r Use a semaphore to perform atomic I/O
Coprocessors v4 30