MOS Devices

Device Physics:
To design of an Integrated Circuit, one of two extreme approaches can be
taken:
- begin with quantum mechanics and understand solid-state physics, semi-
conductor device physics, device modeling and finally the design of circuits.
-treat each semiconductor device as a black box whose behavior is described
in terms of its terminal voltages and currents and design circuits with little in terms of its terminal voltages and currents and design circuits with little
attention to the internal operation of the device.
What is MOS device?
-An MOS (Metal Oxide Semiconductor) structure is created by super imposing
several layers of conducting and insulating materials to form a sandwich like
structure.
MOS structures are manufactured using a series of chemical processing
steps.
-Oxidation of the silicon
-The diffusion of impurities into the silicon to give it certain conduction
characteristics.
-Deposition and etching of aluminium or other metals to provide
interconnection in the same way that a printed wiring board is constructed.
CMOS technology provides two types of transistor-
- n-type transistor (NMOS)
- p-type transistor (PMOS)
Transistor operation based on electric field so the devices are also called
Metal Oxide Semiconductor Field Effect Transistor (MOSFET).
MOS- Structure
n
+
n
+
S G
D
p-substrate
Polysilicon
SiO
2
NMOS
G
D
S
G
D
S
NMOS
NMOS- Symbol
p
+
p
+
S G
D
n-substrate
PMOS
PMOS-symbol
G
G
S
S
D
D
NMOS transistor is built with a p-type body and has regions of n-type
semiconductor adjacent to the gate called source and drain. Similarly,
A PMOS transistor is built with a n-type body and has regions of p-type
semiconductor adjacent to the gate called source and drain
- Each transistor consists of a stack of the conducting gate.
MOS- Structurecontd
- An insulating layer of SiO
2
.
- A silicon wafer also called the substrate.
Two types of Transistor :
Enhancement Mode Transistor
Depletion Mode Transistor
n
+
n
+
S G
D
p-substrate
Polysilicon
SiO
2
NMOS- Enhancement Mode
Enhancement Mode Transistor
-Polysilicon gate is deposited on a layer of insulation over the region between source
and drain.
-Basic enhancement mode device in which the channel is not established and the
device is in non-conducting condition, V
D
=V
S
=V
gs
=0.
-A suitable positive voltage with respect to the source is applied to the gate, then the
electric field established between the gate and the substrate gives rise to a charge
inversion region in the substrate under the gate insulation.
-A conducting path or channel is formed between source and drain.
Depletion Mode Transistor
n
+
n
+
S G
D
p-substrate
Polysilicon
SiO
2
Implant
NMOS- Depletion Mode
- A suitable impurities in the region between source and drain during manufacture
and prior to depositing the insulation and gate. Under this circumstance, source and
drain are connected by a conducting channel.
-The channel may be established under the condition V
gs
=0.
-Now the channel may be closed by applying a suitable negative voltage to the gate.
MOS Transistor Theory
MOS transistor is a majority-carrier device in which the current in a conducting
channel between the source and drain is controlled by a voltage applied to the gate.
In an NMOS transistor, the majority carriers are electrons.
In a PMOS transistor the majority carriers are holes.
The behavior of MOS transistor-
Firstly, Consider an isolated MOS structure with a gate and body but no source or Firstly, Consider an isolated MOS structure with a gate and body but no source or
drain.
Top layer of the structure is a good
conductor, metal/poly-silicon.
Middle layer of the structure is a very thin
insulating film of SiO
2
called gate oxide.
The bottom layer is the p-type doped body.
Gate- metal/polysilicon
SiO
2
p-substrate
Accumulation Mode
Gate- metal/polysilicon
p-substrate
SiO
2

+
-
V
g
<0
-A negative voltage is applied to the gate, so there is negative charge on the gate.
-The mobile positively charged holes are attracted to the region beneath the gate,
This is called the Accumulation mode.

Depletion Mode

+
-

0<V
g
<V
t
Depletion Region
-A low positive voltage is applied to the gate, resulting in some positive charge on
the gate.
-The holes in the substrate are repelled from the region directly beneath the gate.
Thus resulting in a depletion region forming below the gate.

+
-

Inversion Mode
V
g
>V
t
Inversion Region
Depletion Region

-When a higher positive voltage exceeding a critical threshold voltage V

t
is applied,
attracting more positive charge to the gate.
-The holes are repelled further and a small number of free electrons in the body are
attracted to the region beneath the gate.
-This conductive layer of electrons in the p-type body is called the inversion layer.
V
gs
=0

n+ n+
+
-
+
-

S
G
D
V
gd
Cut-off: No Channel
MOS Operation
Cut-off mode

Cut-off: No Channel
I
ds
=0
-The gate to source voltage V
gs
is less than the threshold voltage.
- No channel is formed between source and drain, so almost zero current flow
from drain to source.
-This mode of operation is called cutoff region.
Linear:
V
gs
>V
t

n+ n+
+
-
+
-

S
G
D
V
gd
=V
gs
V
ds
=0
Linear mode
Linear:
Channel Formed
I
ds
increase with V
ds
V
gs
>V
t +
-
+
-
S
G
D
V
gd
>V
gs
>V
t

n+ n+

0 <V
ds
<V
gs
- V
t
I
ds
-The gate voltage is greater than the threshold voltage
-An inversion region of electrons called the channel connects the source
and drain, creating a conductive path.
-The number of carriers and conductivity increases with the gate voltage.
-The potential difference between drain and source is V
ds
=V
gs
-V
gd
.
Linear mode of Operation
ds gs gd
-If V
ds
=0 i.e. V
gs
=V
gd
, there is no electric field tending to push current from
drain to source.
-When a small positive potential V
ds
is applied to the drain, current Ids flows
through the channel from drain to source.
-This mode of operation in termed linear, resistive or non-saturated region;
the current is increases with both the drain and gate voltage.
V
gs
>V
t +
-
+
-
S
G
D
V
gd
<V
t

n+ n+

V
ds
>V
gs
- V
t
I
ds
Saturation mode
-If V
ds
becomes sufficiently large that V
gd
<V
t
, the channel is no longer inverted near
the drain and becomes pinched off.
-However the conduction is still brought about by the drift of electrons under the
influence of the positive drain voltage.
-As electrons reach the end of the channel, they are injected into the depletion region
near the drain and accelerated toward the drain. Above this drain voltage the current
I
ds
is controlled only by the gate voltage, this mode is called saturation mode.
Threshold Voltage
The input potential V
gs
at which the surface just becomes inverted is
called the threshold voltage V
t
.
What affects the Threshold Voltage?
Substrate doping Substrate doping
Oxides thickness
Source-to-substrate voltage bias
Gate material
Surface charge density
Metal Oxide (Si) Semiconductor (MOS) structure
Gate
voltage
p-Si substrate
v
G
The surface charge in the semiconductor ( Q
S
) is controlled
by means of the gate voltage ( v
G
)
Metal (n
+
poly-Si gate)
Gate oxide SiO
2
Thickness = t
ox
Dielectric
p-Si substrate
Dielectric
constant =
ox
= electric potential across the semiconductor
) (v V v
G s ox G
+ =
) (v
G s
V
ox
= electric potential across the oxide
t
ox
pSi
v
G
Gate
voltage
The surface charge in the semiconductor ( Q
S
) is controlled
by means of the gate voltage ( v
G
);
No perturbation far from the interface (equilibrium) !!
capacitance/cm
2
of the oxide: C
ox
=
ox
/ t
ox
( ) ( )
G s
ox
s
G s
ox
m
G s ox G
v
C
Q
v
C
Q
) (v V v + = + = + =
Q
m
: charge/cm
2
in metal = -Q
s
: charge/cm
2
in semiconductor.
Charge in the metal Q
M
= Q
S
charge in the semiconductor
Ideal MOS capacitor
No current can flow:
0 = + =
dx
dn
qD
dx
d
n q J
n n n

n n
q
kT
D =
with
dx
dn
q
kT
q
dx
dn
qD
dx
d
n q
n n n

= =
n
dn
q
kT
d =
dx q
q
dx
qD
dx
n q
n n n
= =
n q
d =
Integrating:

=
0
0
n
n
s s
n
dn
q
kT
d

\
|
=
kT
q
n n
s
s

exp
0
and similarly for holes: |

\
|
=
kT
q
p p
s
s

exp
0
Different charge carrier concentrations at the surface can be
obtained by varying the surface potential ...
Accumulation: v
G
< 0
Hole accumulation at the
Si/SiO
2
interface
pSi substrate
v
G
Q
M
<0
Q
S
>0
O pSi M
0 <
s

V
G
O pSi M
(x)
s

0
x
pSi substrate
Q
S
>0

>
|

\
|

=
<
|

\
|
=
0 0
0 0
exp
exp
p
kT
q
p p
n
kT
q
n n
s
s
s
s
Q
s
Q
m
x
Charge neutrality
(x)
|Q
m
| =Q
s
[ ] ) (V
G s
O pSi M
Depletion: 0 < v
G
< V
Tn

Depletion of holes at the
Si/SiO
2
interface
O pSi M
F s
2 0 < <
Q
M
(positive)
pSi substrate
v
G
( ) ( ) ( ) ( ) ( )
V
G
O pSi M
(x)
s

0
x
Q
b
=-qN
A
w
Q
m
x
(x)
w
depletion
O pSi M
It can be shown that:
s
A
s

qN

w
2
=
Depletion: Q
S
(negative N
A

)
pSi substrate
( )
s A s s b s
qN Q Q 2 = =
Poisson equation for fully depleted SCR

=
= =
d
d
s
A
s
x x
dx
d
x x
qN
dx
d
; 0
0 ;
2
2
2
2

0 ) ( = =

dx
d

Boundary conditions:
Two integrations:

=
=
d
d d
s
A
x x x
x x x x
qN
x
; 0 ) (
0 ; ) (
2
) (
2

2
2
d
s
A
s
x
qN
=

s
A
s
d
qN
x
2
=
At the interface:
s
x = = ; 0
s A s d A b
qN x qN Q 2 = =
Strong inversion: v
G
> V
Tn

An electron layer (inversion channel) is formed at the Si/SiO
2
interface
Q
M
(positive)
Inversion channel
pSi substrate
v
G
( ) ( ) ( ) ( ) ( )
F s
2
( )
Tn G ox i
V v C Q =
Q
b
=-qN
A
w
m
Q
m
x
(x)
w
m
depletion
Q
i
i F b sc
Q ) ( Q Q + = 2
Semiconductor charge/cm
2
:
For v
G
> V
Tn
the electron
surface concentration is
not negligible any more.
t
ox
pSi
V
G
( )
G s
ox
b
G
V
C
Q
V + = From:
The strong inversion threshold voltage of the ideal MOS
capacitor can be derived:
( )
( )
F
ox ox
F A s
F
ox
F b
Tn
/t
qN
C
Q
V

2
2 2
2
2
+ = +

=
It depends on the oxide thickness t
ox
and on the substrate
doping concentration N
A
MOSFET Input Characteristics
The input characteristics relates drain current response to the input gate-source
driving voltage.
Since the gate terminal is electrically isolated from the remaining terminals, the
gate current is essentially zero, so that the gate current is not part of the
characteristics.
Figure 3-9 shows measured input characteristics for an nMOS and pMOS transistor
with a small 0.1V potential across their drain to source terminals.
NMOS
PMOS
The transistors are in their non-saturated bias states.
As V
GS
increases for the nMOS transistor in Figure, the threshold voltage is
reached where drain current elevates.
For V
GS
between 0 V and 0.7 V, I
D
is nearly zero indicating that the
equivalent resistance between the drain and source terminals is extremely
high.
Once V
GS
reaches 0.7 V, the current increases rapidly with V
GS
indicating
that the equivalent resistance at the draindecreases with increasing gate-
source voltage.
Therefore, the threshold voltage of the nMOS transistor is about V
tn
0.7 V.
When a transistor turns on the current moves through a load.
NMOS transistor Output Characteristics
MOS transistor output characteristics plot I
D
versus V
DS
for several values of
V
GS.
Two conduction states are distinguished when the device is ON: the saturated
state and the non-saturated state. The saturated curve is the flat portion and
defines the saturation region.
When the transistor is OFF (V
GS
< V
tn
), then I
D
is zero for any VDS value.
For V
GS
> V
DS
+ V
tn
, the transistor is in the non-saturation region and the
curve is a half parabola.
For V
GS
< V
DS
+ V
tn
, the NMOS device is conducting and I
D
is independent of
V
DS
.
The boundary of the saturation/non-saturation bias states is a point seen for
each curve in Figure as the intersection of the straight line of the saturated each curve in Figure as the intersection of the straight line of the saturated
region with the quadratic curve of the nonsaturated region.
This intersection point occurs at the channel pinchoff voltage called V
DSAT
.
V
DSAT
is defined as the minimum drain-source voltage that is required to keep
the transistor in saturation for a given V
GS
.
In the non-saturated state, the drain current initially increases almost linearly
from the origin before bending in a parabolic response. Thus the name ohmic or
linear for the non-saturated region.
CMOS Current (I
DS
) Equation
Consider an NMOS device,
We know,
when V
GS
<V
T
the transistor is off, regardless of the drain voltage.
The device conducts when V
GS
>V
T
, and if a constant V
GS
is applied then the
resulting I
DS
versus V
DS
curve can be split into two regions.
- at resistive region when V
DS
<V
GS
-V
T
; V
GS
>V
T DS GS T GS T
- Saturation region when V
DS
V
GS
-V
T
; V
GS
>V
T
For resistive region:
The voltage across the insulator at the source is VGS and at the drain is VGD.
Although the voltage across the insulator is not constant, a voltage excess of
VT exists at all points across the oxide, causing
The saturated and non-saturated states intersect at V
DSAT
where either equation
describes the current and voltage relations. We can solve for this important bias
condition where the saturated and nonsaturated states intersect (V
DSAT
).
The midpoint at zero slope defines the useful upper region of Equation for
resistive region and also defines the boundary between the saturated and
non-saturated bias states.
We can define the boundary bias condition by differentiating the equation
with respect to V
DS
, setting the expression to zero, and then solving for the
conditions.
Terms cancel giving the important bias condition at the transition between
saturation and nonsaturation states as
V
GS
=V
DS
+V
T
V
DS
=V
GS
-V
T
The equation can be extended to define the NMOS saturated bias
For saturation bias condition
V
DS
>V
GS
-V
T
or, V
GS
<V
DS
+V
TC
V <V -V or, V >V +V
For non-saturation bias condition
V
DS
<V
GS
-V
T
or, V
GS
>V
DS
+V
TC
Examples..
PMOS Transistor Output Characteristics
PMOS transistor analysis is similar to the NMOS transistor with a major exception;
-Care must be taken with the polarities of the drain current and node voltage
-PMOS transistor majority carrier is the hole that emanates from the source into the
channel