Application Note Guide to Using the DDX-4100 to Implement a 5.

1 Channel Audio System

Introduction
DDX all-digital amplifiers are an excellent choice for 5.1 surround systems. The high-efficiency and power to size ratio of DDX amplifiers provide the ability to integrate power amplification inside a low-profile DVD player, A/V Receiver, or powered speaker system. When used in conjunction with a surround sound decoder IC, DDX provides a complete high quality digital surround system.
2 The purpose of this application note is to describe the DDX-4100 I C register settings necessary to implement a 5.1 channel reference design. Schematics and register settings are provided for the following two design examples.

Design 1: A 5.1 channel design with the DDX-4100s each having a unique device address (Refer to DDX4100 errata at; http://www.apogeeddx.com/ER_DDX_4100.pdf.). Design 2: A 5.1 channel design sharing the same device address (Two I2 C SCLs are needed for this configuration). This configuration enables additional subwoofer channel gain by using the DDX-4100 bass/treble boost settings. The application note also includes, in the Appendices, system configuration information to meet product power output requirements, use of the bass/treble functions of the DDX-4100 and suggestions for the proper implementation of the subwoofer channel.

129 Morgan Drive, Norwood MA 02062 1 voice: (781) 551-9450 fax: (781) 440-9528 email: sales@apogeeddx.com
Copyright Apogee Technology, Inc 2002 (All Rights Reserved)

PRELIMINARY

Rev 1.0 January 2002 Doc# 01020001-01

Design Example 1
Design a DDX 5.1 channel amplifier circuit with 5 x 35W + 1x70W, 6 channel I2 S input, MCU control of I C, and local regulation of logic power supplies. A 5.1 system with I2 S inputs are assumed as well as the LFE and CENTER channels are connected to the Main Controllers Right Surround channel and Left Surround respectively. The LS and RS channels are connected to the Aux Controllers LS/RS channels.
2

The Main/Aux Select is done in this example by using device select addressing. By grounding the SA pin on the Main controller its device address is 0x0011110. The Aux controllers address is 0x0011111 since its SA pin is pulled high. In this demonstration only one SCL clock is needed from the micro-controller and the device address selects which device the micro-controller is interfacing too (an example with two SCLs is shown in design example two). When using a single SCL clock and two processors SA must be tied to VDD and SDI1 to GND on the second processor, refer to DDX-4100 errata at; http://www.apogeeddx.com/ER_DDX_4100.pdf.

BLOCK DIAGRAM for DESIGN EXAMPLE 1

5.1 Channel Decoder

I2S

DDX4100
Controller Main

DDX-2060 Power Driver DDX-2060 Power Driver DDX-2060 Power Driver

LP Filter

2X35W, 8 , L&R

LP Filter

35W, 8 Center

LP Filter

70W, 4 SUB

I2C MicroController

DDX4100
Controller Auxiliary

DDX-2060 Power Driver

LP Filter

2X35W, 8 Surround

I C COMMANDS The first I2 C register settings are used to reset the main and auxiliary ICs. The digital gain is also set to the maximum level for surround sound playback (digital gain of 9dB or a factor of 3) with compression enabled.

PRELIMINARY

System Reset, Set System Gain

Main/Aux Address 3Ch 3Ch 3Eh 3Eh 3Ch 3Eh 3Ch 3Eh R/ W W W W W W W W W REG 00h 01h 00h 01h 5Bh 5Bh 26h 26h DATA 00h E4h 00h E4h 6Dh 6Dh 00h 00h COMMENTS Soft Reset, Main Controller Soft Reset, Main Controller Soft Reset, Auxiliary Controller Soft Reset, Auxiliary Controller Clear DDX Reset, Set DDX Gain=3X, Proprietary (1dB/step)vol. mode, Main Clear DDX Reset, Set DDX Gain=3X, Proprietary (1dB/step)vol. mode, Aux Clear EAPD, Main Clear EAPD, Aux

*Unmute and Set Desired Channel Volume

Main/Aux R/ REG DATA COMMENTS Address W 3Ch W 03h Set Volume on Right Channel to Desired Setting 3Ch W 02h Set Volume on Left to Desired Setting and Unmute Left and Right Channels 3Ch W 38h Set Volume to Desired Setting and Unmute C (LS) Channel 3Ch W 36h Set Volume to Desired Setting and Unmute SUB (LFE) Channel 3Eh W 37h Set Volume to Desired Setting and Unmute Left Surround Channel 3Eh W 38h Set Volume to Desired Setting and Unmute Right Surround Channel * When using the sample rate converter (SRC), it is mandatory to apply a valid input signal to the DDX-4100 prior to unmuting, refer to DDX-4100 errata at; http://www.apogeeddx.com/ER_DDX_4100.pdf .

LFE Redirection via Bass Management Feature In order for the LFE channel to have a separate filter from the Center channel bass redirection can be used to redirect the LFE channel. By Default, the bass redirection factors are set to 0xC0000h. The desired scaling factors for the LFE channel redirection should be entered into the DDX-4100 device. In this example the LFE channel is completely redirected while the remaining channels are muted (refer to the I2 C commands in the following table). The biquad filters should be written when the devices are muted, i.e., prior to the Unmute commands above.
Main/Aux Address 3Ch 3Ch 3Ch 3Ch 3Ch 3Ch 3Ch 3Ch 3Ch 3Ch 3Ch 3Ch 3Ch 3Ch 3Ch 3Ch 3Ch 3Ch 3Ch 3Ch 3Ch 3Ch 3Ch 3Ch 3Ch R/ W W W W W W W W W W W W W W W W W W W W W W W W W W REG 73h 78h 79h 7Ah 7Bh 78h 79h 7Ah 7Bh 78h 79h 7Ah 7Bh 78h 79h 7Ah 7Bh 78h 79h 7Ah 7Bh 78h 79h 7Ah 7Bh DATA 01h 00h 00h 7Fh 00h 00h 00h 80h 00h 00h 00h 81h 00h 00h 00h 82h 08h 00h 00h 83h 00h 00h 00h 84h 00h COMMENTS Enable Bass-Management in Main Controller Write L SCALE bit [15..8] for L Channel redirection factor on Main Controller (MUTE) Write L SCALE bit [7..0] for L Channel redirection factor on Main Controller (MUTE) Write L SCALE address for L Channel redirection factor on Main Controller (MUTE) Write L SCALE bit [19..16] for L Channel redirection factor on Main Controller (MUTE) Write R SCALE bit [15..8] for R Channel redirection factor on Main Controller (MUTE) Write R SCALE bit [7..0] for R Channel redirection factor on Main Controller (MUTE) Write R SCALE address for R Channel redirection factor on Main Controller (MUTE) Write R SCALE bit [19..16] for R Channel redirection factor on Main Controller (MUTE) Write C (LS) SCALE bit [15..8] for C Chan redirection factor on Main Controller(MUTE) Write C (LS) SCALE bit [7..0] for C Chan redirection factor on Main Controller (MUTE) Write C (LS) SCALE address for C Chan redirection factor on Main Controller (MUTE) Write C(LS) SCALE bit[19..16] for C Chan redirection factor on MainController (MUTE) Write LFE (RS) SCALE bit [15..8]for SUB Chan redirection factor on Main Controller Write LFE (RS) SCALE bit [7..0] for SUB Chan redirection factor on Main Controller Write LFE (RS) SCALE address for SUB Chan redirection factor on Main Controller Write LFE (RS) SCALE bit [19..16] for SUB Chan redirection factor on Main Controller Write C SCALE bit [15..8] for C Chan redirection factor on Main Controller (MUTE) Write C SCALE bit [7..0] for C Chan redirection factor on Main Controller (MUTE) Write C SCALE address for C Chan redirection factor on Main Controller (MUTE) Write C SCALE bit [19..16] for C Chan redirection factor on Main Controller (MUTE) Write LFE SCALE bit [15..8]for LFE Chan redirection factor on Main Controller (MUTE) Write LFE SCALE bit [7..0] for LFE Chan redirection factor on Main Controller (MUTE) Write LFE SCALE address for LFE Chan redirection factor on Main Controller (MUTE) Write LFE SCALE bit [19..16] for LFE Ch redirection factor on Main Controller (MUTE)

PRELIMINARY

BIQUAD Coefficients (Optional)

2 As an additional example of I C setting, biquad filters are used to perform speaker equalization and crossover functions. The biquad filters should be written when the devices are muted, i.e., prior to the Unmute commands above.

The biquad coefficients were obtained using Apogees Filter generation software and were generated in order to equalize a +2dB bump at 1kHz with Q = 1.414 on the L/R/LS/RS/C channels. On the LFE channel a 2nd order Butterworth Low-pass filter with a cutoff of 225Hz was used.

L/R/LS/RS/C Coefficients: B2: 0x73633h (B0)-1: 0 xFE8DF h A2: 0x71F1Fh A1/2: 0x88107h B1/2: 0x88107h SUB Coefficients: B2: 0x0006Fh (B0)-1: 0x80070h A2: 0x7AC6Fh A1/2: 0x82AA7Fh B1/2: 0x0006Fh Following are the steps necessary to write coefficients via I2 C Write 8 middle data bits at I2 C address 78h Write 8 lower data bits at I2 C address 79h Write 8 bit address at I2 C address 7Ah coeff INDEX +40h Write 4 upper data bits and R/W bit at I2 C address

Main/Aux Address 3Ch 3Ch 3Ch 3Ch 3Ch 3Ch 3Ch 3Ch 3Ch 3Ch 3Ch 3Ch 3Ch 3Ch 3Ch 3Ch 3Ch 3Ch 3Ch 3Ch 3Ch

R/ W W W W W W W W W W W W W W W W W W W W W W

REG 78h 79h 7Ah 7Bh 78h 79h 7Ah 7Bh 78h 79h 7Ah 7Bh 78h 79h 7Ah 7Bh 78h 79h 7Ah 7Bh 78h

DATA 36h 33h 40h 07h E8h DFh 41h 0Fh 1Fh 1Fh 42h 07h 81h 07h 43h 08h 81h 07h 44h 08h 36h

COMMENTS Write [B2 Biqaud 0] Coeff bit [15..8] for LR Channel on Main Controller Write [B2 Biquad 0] Coeff bit [7..0] for LR Channel on Main Controller Write [B2 Biquad 0] Coeff address for LR Channel on Main Controller Write [B2 Biquad 0] Coeff bit [19..16] for LR Channel on Main Controller Write [((B0) 1) Biquad 0] Coeff bit [15..8] for LR Channel on Main Controller Write [((B0) 1) Biquad 0] Coeff bit [7..0] for LR Channel on Main Controller Write [((B0) 1) Biquad 0] Coeff address for LR Channel on Main Controller Write [((B0) 1) Biquad 0] Coeff bit [19..16] for LR Channel on Main Controller Write [A2 Biqaud 0] Coeff bit [15..8] for LR Channel on Main Controller Write [A2 Biquad 0] Coeff bit [7..0] for LR Channel on Main Controller Write [A2 Biquad 0] Coeff address for LR Channel on Main Controller Write [A2 Biquad 0] Coeff bit [19..16] for LR Channel on Main Controller Write [(A1/2) Biquad 0] Coeff bit [15..8] for LR Channel on Main Controller Write [(A1/2) Biquad 0] Coeff bit [7..0] for LR Channel on Main Controller Write [(A1/2) 1) Biquad 0] Coeff address for LR Channel on Main Controller Write [(A1/2) 1) Biquad 0] Coeff bit [19..16] for LR Channel on Main Controller Write [(B1/2) Biquad 0] Coeff bit [15..8] for LR Channel on Main Controller Write [(B1/2) Biquad 0] Coeff bit [7..0] for LR Channel on Main Controller Write [(B1/2) 1) Biquad 0] Coeff address for LR Channel on Main Controller Write [(B1/2) 1) Biquad 0] Coeff bit [19..16] for LR Channel on Main Controller Write [B2 Biqaud 0] Coeff bit [15..8] for C (LSRS) Channel on Main Controller

PRELIMINARY

3Ch 3Ch 3Ch 3Ch 3Ch 3Ch 3Ch 3Ch 3Ch 3Ch 3Ch 3Ch 3Ch 3Ch 3Ch 3Ch 3Ch 3Ch 3Ch 3Ch 3Ch 3Ch 3Ch 3Ch 3Ch 3Ch 3Ch 3Ch 3Ch 3Ch 3Ch 3Ch 3Ch 3Ch 3Ch 3Ch 3Ch 3Ch 3Ch 3Eh 3Eh 3Eh 3Eh 3Eh 3Eh 3Eh 3Eh 3Eh 3Eh 3Eh 3Eh 3Eh 3Eh 3Eh 3Eh 3Eh 3Eh 3Eh 3Eh

W W W W W W W W W W W W W W W W W W W W W W W W W W W W W W W W W W W W W W W W W W W W W W W W W W W W W W W W W W W

79h 7Ah 7Bh 78h 79h 7Ah 7Bh 78h 79h 7Ah 7Bh 78h 79h 7Ah 7Bh 78h 79h 7Ah 7Bh 78h 79h 7Ah 7Bh 78h 79h 7Ah 7Bh 78h 79h 7Ah 7Bh 78h 79h 7Ah 7Bh 78h 79h 7Ah 7Bh 78h 79h 7Ah 7Bh 78h 79h 7Ah 7Bh 78h 79h 7Ah 7Bh 78h 79h 7Ah 7Bh 78h 79h 7Ah 7Bh

33h 45h 07h E8h DFh 46h 0Fh 1Fh 1Fh 47h 07h 81h 07h 48h 08h 81h 07h 49h 08h 00h 6Fh 68h 00h 00h 70h 69h 08h ACh 6Fh 6Ah 07h 2Ah A7h 6Bh 08h 00h 6Fh 6Ch 00h 36h 33h 54h 07h E8h DFh 55h 0Fh 1Fh 1Fh 56h 07h 81h 07h 57h 08h 81h 07h 58h 08h

Write [B2 Biquad 0] Coeff bit [7..0] for C (LSRS) Channel on Main Controller Write [B2 Biquad 0] Coeff address for C (LSRS) Channel on Main Controller Write [B2 Biquad 0] Coeff bit [19..16] for C (LSRS) Channel on Main Controller Write [((B0) 1) Biquad 0] Coeff bit [15..8] for C (LSRS) Channel on Main Controller Write [((B0) 1) Biquad 0] Coeff bit [7..0] for C (LSRS) Channel on Main Controller Write [((B0) 1) Biquad 0] Coeff address for C (LSRS) Channel on Main Controller Write [((B0) 1) Biquad 0] Coeff bit [19..16] for C (LSRS) Channel on Main Controller Write [A2 Biqaud 0] Coeff bit [15..8] for C (LSRS) Channel on Main Controller Write [A2 Biquad 0] Coeff bit [7..0] for C (LSRS) Channel on Main Controller Write [A2 Biquad 0] Coeff address for C (LSRS) Channel on Main Controller Write [A2 Biquad 0] Coeff bit [19..16] for C (LSRS) Channel on Main Controller Write [(A1/2) Biquad 0] Coeff bit [15..8] for C (LSRS) Channel on Main Controller Write [(A1/2) Biquad 0] Coeff bit [7..0] for C (LSRS) Channel on Main Controller Write [(A1/2) 1) Biquad 0] Coeff address for C (LSRS) Channel on Main Controller Write [(A1/2) 1) Biquad 0] Coeff bit [19..16] for C (LSRS) Channel on Main Controller Write [(B1/2) Biquad 0] Coeff bit [15..8] for C (LSRS) Channel on Main Controller Write [(B1/2) Biquad 0] Coeff bit [7..0] for C (LSRS) Channel on Main Controller Write [(B1/2) 1) Biquad 0] Coeff address for C (LSRS) Channel on Main Controller Write [(B1/2) 1) Biquad 0] Coeff bit [19..16] for C (LSRS) Channel on Main Controller Write [B2 Biqaud 0] Coeff bit [15..8] for SUB Channel on Main Controller Write [B2 Biquad 0] Coeff bit [7..0] for SUB Channel on Main Controller Write [B2 Biquad 0] Coeff address for SUB Channel on Main Controller Write [B2 Biquad 0] Coeff bit [19..16] SUB Channel on Main Controller Write [((B0) 1) Biquad 0] Coeff bit [15..8] for SUB Channel on Main Controller Write [((B0) 1) Biquad 0] Coeff bit [7..0] for SUB Channel on Main Controller Write [((B0) 1) Biquad 0] Coeff address for SUB Channel on Main Controller Write [((B0) 1) Biquad 0] Coeff bit [19..16] SUB Channel on Main Controller Write [A2 Biqaud 0] Coeff bit [15..8] for SUB Channel on Main Controller Write [A2 Biquad 0] Coeff bit [7..0] for SUB Channel on Main Controller Write [A2 Biquad 0] Coeff address for SUB Channel on Main Controller Write [A2 Biquad 0] Coeff bit [19..16] SUB Channel on Main Controller Write [(A1/2) Biquad 0] Coeff bit [15..8] for SUB Channel on Main Controller Write [(A1/2) Biquad 0] Coeff bit [7..0] for SUB Channel on Main Controller Write [(A1/2) 1) Biquad 0] Coeff address for SUB Channel on Main Controller Write [(A1/2) 1) Biquad 0] Coeff bit [19..16] SUB Channel on Main Controller Write [(B1/2) Biquad 0] Coeff bit [15..8] for SUB Channel on Main Controller Write [(B1/2) Biquad 0] Coeff bit [7..0] for SUB Channel on Main Controller Write [(B1/2) 1) Biquad 0] Coeff address for SUB Channel on Main Controller Write [(B1/2) 1) Biquad 0] Coeff bit [19..16] SUB Channel on Main Controller Write [B2 Biqaud 0] Coeff bit [15..8] for LSRS Channel on AUX Controller Write [B2 Biquad 0] Coeff bit [7..0] for LSRS Channel on AUX Controller Write [B2 Biquad 0] Coeff address for LSRS Channel on AUX Controller Write [B2 Biquad 0] Coeff bit [19..16] for LSRS Channel on AUX Controller Write [((B0) 1) Biquad 0] Coeff bit [15..8] for LSRS Channel on AUX Controller Write [((B0) 1) Biquad 0] Coeff bit [7..0] for LSRS Channel on AUX Controller Write [((B0) 1) Biquad 0] Coeff address for LSRS Channel on AUX Controller Write [((B0) 1) Biquad 0] Coeff bit [19..16] for LSRS Channel on AUX Controller Write [A2 Biqaud 0] Coeff bit [15..8] for LSRS Channel on AUX Controller Write [A2 Biquad 0] Coeff bit [7..0] for LSRS Channel on AUX Controller Write [A2 Biquad 0] Coeff address for LSRS Channel on AUX Controller Write [A2 Biquad 0] Coeff bit [19..16] for LSRS Channel on AUX Controller Write [(A1/2) Biquad 0] Coeff bit [15..8] for LSRS Channel on AUX Controller Write [(A1/2) Biquad 0] Coeff bit [7..0] for LSRS Channel on AUX Controller Write [(A1/2) 1) Biquad 0] Coeff address for LSRS Channel on AUX Controller Write [(A1/2) 1) Biquad 0] Coeff bit [19..16] for LSRS Channel on AUX Controller Write [(B1/2) Biquad 0] Coeff bit [15..8] for LSRS Channel on AUX Controller Write [(B1/2) Biquad 0] Coeff bit [7..0] for LSRS Channel on AUX Controller Write [(B1/2) 1) Biquad 0] Coeff address for LSRS Channel on AUX Controller Write [(B1/2) 1) Biquad 0] Coeff bit [19..16] for LSRS Channel on AUX Controller

PRELIMINARY

3.3V

VB+

REGULATED POWER SUPPLY

SDATA1 SDATA2 SDATA3 LRCK SCK

SDI1 SDI3 LRCK SCK SDA SCL PWDN RESET XTO

3.3V

VB+

LEFTA LEFTB RIGHTA RIGHTB CENTERA CENTERB LFEA LFEB EAPD1

LEFTA LEFTB RIGHTA RIGHTB

LEFT+ LEFT-

SPKR1

8 OHM

EAPD1 TWARN1

RIGHT+ RIGHT-

SPKR2

8 OHM

5.1 CHANNEL DECODER

L,R,C,SUB PROCESSING

L,R OUTPUTS

CENTERA CENTERB

VB+

CENTER+ EAPD1 TWARN2 CENTER-

SPKR3

8 OHM

C OUTPUTS

SDA SCL

LFEA LFEB

VB+

LFE+ TWARN EAPD1 PWDN TWARN3 SYSTEM MICROCONTROLLER SUB OUTPUTS LFE-

SPKR4

4 OHM

3.3V

VB+

SDI2 LRCK SCK SDA SCL POWER-ON-RESET PWDN RESET XTO

SLEFTA SLEFTB SRIGHTA SRIGHTB

SLEFTA SLEFTB SRIGHTA SRIGHTB

LSUR+ LSUR-

SPKR5

8 OHM

EAPD2

EAPD2 TWARN4

RSUR+ RSUR-

SPKR6

8 OHM

LS,RS PROCESSING

LS,RS OUTPUTS

SHEET 1: SYSTEM LEVEL DIAGRAM FOR DESIGN EXAMPLE 1

PRELIMINARY

C1 +3.3V + 22uF 6.3V C2 100nF

PWDN

EAPD1 CENTER_A

+3.3V

SDI1 SDI3 LRCK SCK RESET SDA SCL

C4 100nF

TEST_MODE VDD_2 XTI XTO GND_2 VCC RXP RXN VSS LFE_B LFE_A

1 2 3 4 5 6 7 8 9 10 11

PWDN CKOUT VDD_5 GND_5 SCKO SDO_3 SDO_2 SDO_1 LRCKO EAPD SLEFT_A

SDI1 = L, R SDI2 = LS, RS SDI3 = C, SUB

44 43 42 41 40 39 38 37 36 35 34

U1

SDI_1/SDATA_OUT SDI_2/SDATA_IN LRCKI/SYNC BCKI/BIT_CLK VDD_1 GND_1 RESET AC97_MODE SDA SCL SA

SLEFT_B VDD_4 GND_4 LEFT_A LEFT_B RIGHT_A RIGHT_B VDD_3 GND_3 SRIGHT_A SRIGHT_B

33 32 31 30 29 28 27 26 25 24 23

CENTER_B +3.3V LEFTA LEFTB RIGHTA RIGHTB +3.3V C5 100nF C3 100nF

12 13 14 15 16 17 18 19 20 21 22

DDX4100A

LFE_A LFE_B L1 R1 +3.3V +3.3V 100nH 1 MEG Y1 XTO 24.576 MHz C9 18pF C10 18pF C6 100nF + C79 C7 C8 100nF 22uF 100nF 6.3V

SHEET 2: MAIN DDX-4100 PROCESSOR FOR DESIGN EXAMPLE 1

C11 +3.3V + 22uF 6.3V C12 100nF

EAPD2 PWDN SLEFT_A SLEFT_B 44 43 42 41 40 39 38 37 36 35 34

+3.3V

SDI2 LRCK SCK RESET SDA SCL +3.3V

C14 100nF

TEST_MODE VDD_2 XTI XTO GND_2 VCC RXP RXN VSS LFE_B LFE_A

1 2 3 4 5 6 7 8 9 10 11

PWDN CKOUT VDD_5 GND_5 SCKO SDO_3 SDO_2 SDO_1 LRCKO EAPD SLEFT_A

SDI1 = L, R SDI2 = LS, RS SDI3 = C, SUB

U2

SDI_1/SDATA_OUT SDI_2/SDATA_IN LRCKI/SYNC BCKI/BIT_CLK VDD_1 GND_1 RESET AC97_MODE SDA SCL SA

SLEFT_B VDD_4 GND_4 LEFT_A LEFT_B RIGHT_A RIGHT_B VDD_3 GND_3 SRIGHT_A SRIGHT_B

33 32 31 30 29 28 27 26 25 24 23

+3.3V C13 100nF +3.3V C15 100nF

12 13 14 15 16 17 18 19 20 21 22

DDX4100A SRIGHTA SRIGHTB

XTO +3.3V

L2 +3.3V 100nH C16 100nF + C80 C17 C18 100nF 22uF 100nF 6.3V

SHEET 3: AUXILIARY DDX-4100 PROCESSOR FOR DESIGN EXAMPLE 1

PRELIMINARY

L3 LEFT+ U3 19 20 C22 100nF +3.3V 100nF X7R C24 21 22 23 24 R5 25 10k EAPD1 26 27 28 C29 100nF LEFTA LEFTB RIGHTA TWARN1 RIGHTB R6 10k C32 34 35 100nF X7R +3.3V C36 100nF X7R 36 29 30 31 32 33 GNDREF GNDR1 VREG1 VREG1 VL CONFIG PWRDN TRI-STATE FAULT TWARN INLA INLB INRA INRB VREG2 VREG2 VSIG VSIG NC OUTPL OUTPL VCC1P PGND1P PGND1N VCC1N OUTNL OUTNL OUTPR OUTPR VCC2P PGND2P PGND2N VCC2N OUTNR OUTNR GNDS 18 17 16 15 14 C27 13 12 11 L4 10 9 L5 8 7 6 5 C30 4 3 2 1 C35 330pF X7R L6 C38 100nF X7R R9 6.2 1/4W C37 100nF X7R 1uF X7R R7 20 1/4W 28V C95 100nF X7R R8 6.2 1/4W C34 100nF X7R J2 RIGHT 1 2 22uH C31 100nF X7R 22uH C94 1uF X7R 100nF X7R C28 100nF X7R 28V C21 + 1000u 35V F C25 330pF X7R 22uH R2 20 1/4W C19 100nF X7R

R3 6.2 1/4W

C20 100nF X7R

C23 470nF FILM

J1 LEFT 1 2

R4 6.2 1/4W

C26 100nF X7R

8 OHM

LEFTRIGHT+

8 OHM
C34 470nF FILM

DDX2060

RIGHT-

22uH

SHEET 4: LEFT AND RIGHT OUTPUTS

SLEFT+ U4 19 20 C42 100nF 100nF X7R +3.3V R13 25 10k EAPD1 26 27 28 C49 100nF SLEFTA SLEFTB SRIGHTA TWARN2 SRIGHTB R14 10k C52 29 30 31 32 33 34 35 100nF X7R +3.3V C56 100nF X7R 36 23 24 C44 21 22 GNDREF GNDR1 VREG1 VREG1 VL CONFIG PWRDN TRI-STATE FAULT TWARN INLA INLB INRA INRB VREG2 VREG2 VSIG VSIG NC OUTPL OUTPL VCC1P PGND1P PGND1N VCC1N OUTNL OUTNL OUTPR OUTPR VCC2P PGND2P PGND2N VCC2N OUTNR OUTNR GNDS 18 17 28V 16 15 14 C47 13 12 11 10 9 8 7 6 C50 5 4 3 2 1 C55 330pF X7R L10 22uH C58 100nF X7R R17 6.2 1/4W C57 100nF X7R 1uF X7R R15 20 1/4W 28V C98 100nF X7R R16 6.2 1/4W C53 100nF X7R J4 RSUR 1 2 L9 22uH C51 100nF X7R C97 1uF X7R 100nF X7R C45 330pF X7R L8 22uH R12 6.2 1/4W C46 100nF X7R C41 + 1000u 35V F R10 20 1/4W R11 6.2 1/4W C40 100nF X7R L7 22uH C39 100nF X7R

C43 470nF FILM

J3 LSUR 1 2

8 OHM

C48 100nF X7R

SLEFTSRIGHT+

8 OHM
C54 470nF FILM SRIGHT-

DDX2060

SHEET 5: LEFT AND RIGHT SURROUND OUTPUTS

PRELIMINARY

L11 CENTER+ U5 19 20 C63 C65 21 22 100nF X7R 23 24 R21 25 10k EAPD2 26 27 28 C71 100nF CENTERA CENTERB 29 30 31 TWARN3 32 33 R22 10k C75 35 100nF X7R +3.3V 100nF X7R 36 C74 34 18 17 28V 16 15 14 C68 13 12 11 10 9 8 7 C72 6 5 C73 4 3 2 1 1uF X7R 100nF X7R 28V 22uH C69 100nF X7R 1uF X7R L12 C70 100nF X7R C59 + 1000uF C66 35V 330pF X7R R20 6.2 1/4W C67 100nF X7R 22uH NC OUTPL OUTPL VCC1P PGND1P PGND1N VCC1N OUTNL OUTNL OUTPR OUTPR VCC2P PGND2P PGND2N VCC2N OUTNR OUTNR GNDS R18 20 1/4W C60 100nF X7R J5 CENTER C64 470nF FILM 1 2

GNDREF GNDR1 VREG1 VREG1 VL CONFIG PWRDN TRI -STATE FAULT TWARN INLA INLB INRA INRB VREG2 VREG2 VSIG VSIG

R19 6.2 1/4W

C62 100nF X7R

100nF +3.3V

8 OHM

CENTER -

DDX2060

SHEET 6: CENTER OUTPUT

L13 LFE+ U6 10uH 19 20 C77 100nF +3.3V R23 C85 10k 100nF EAPD2 26 27 TWARN4 LFEA R27 10k LFEB 28 29 30 31 32 +3.3V C91 C92 100nF X7R 33 34 35 100nF X7R 36 C79 100nF X7R 21 22 23 24 25 GNDREF GNDR1 VREG1 VREG1 VL CONFIG PWRDN TRI -STATE FAULT TWARN INLA INLB INRA INRB VREG2 VREG2 VSIG VSIG NC OUTPL OUTPL VCC1P PGND1P PGND1N VCC1N OUTNL OUTNL OUTPR OUTPR VCC2P PGND2P PGND2N VCC2N OUTNR OUTNR GNDS 18 17 16 15 14 C81 13 12 11 10 9 C86 8 7 C88 6 5 C89 4 3 L14 2 1 10uH LFE 1uF X7R 100nF X7R C90 220nF X7R 28V 680pF X7R R26 3.0 1/4W C87 220nF X7R R24 10 1/2W R25 3.0 1/4W C83 220nF X7R C84 1uF FILM J6 SUBWOOFE R 1 2 100nF X7R 28V C76 + 35V C82 1000u F 1uF X7R

C80 220nF X7R

4 OHM

DDX2060

SHEET 7: SUBWOOFER OUTPUT

PRELIMINARY

Design Example 2
Design a DDX 5.1 channel amplifier circuit with 5 x 35W + 1x70W, 6 channel I2 S input, MCU control of I C, and local regulation of logic power supplies. A 5.1 system with I2 S inputs are assumed as well as the LFE and CENTER channels are connected to the Aux Controllers Right channel and Left Surround respectively. Below is the Block Diagram and Schematics for the 5.1 system design described above in design example 2.
2

The Main/Aux Select is done in this example by the micro-controller having two SCL clocks. When using two DDX-4100s in a single system the user must ground SA pin 11 on both ICs, causing both ICs to have the same I2 C address = 0x0011110, and use two separate I2 C clock pins from the system micro-controller, one for each IC, to address the two processors independently. When communicating with the first processor, the SCL signal connected to the second must remain static and vice versa, refer to DDX-4100 errata at; http://www.apogeeddx.com/ER_DDX_4100.pdf. This setup using one SCL could also be accomplished with a demultiplexer. The micro-controller would provide the Main/Aux Select signal, which would steer the SCL to the correct 4100 as well as the SCL signal, which would be the input into the demux. An example with one SCL is shown in design example one above.

BLOCK DIAGRAM for DESIGN EXAMPLE 2

DDX-2060 Power Driver
LP Filter

5.1 Channel Decoder

I2S

DDX4100
Controller Main

2X35W, 8 , L&R

DDX-2060 Power Driver

LP Filter

2X35W, 8 Surround

DDX4100
I2C MicroController Controller Auxiliary

DDX-2060 Power Driver DDX-2060 Power Driver

LP Filter

35W, 8 Center

LP Filter

70W, 4 SUB

I C COMMANDS The first I2 C register settings are used to reset the main and auxiliary ICs. The digital gain is also set to the maximum level for surround sound playback (Digital gain of 9dB or a factor of 3) with compression enabled.

10

PRELIMINARY

System Reset, Set System Gain

Main/Aux SELECT 0 0 1 1 0 1 0 1 R/ W W W W W W W W W REG 00h 01h 00h 01h 5Bh 5Bh 26h 26h DATA 00h E4h 00h E4h 6Dh 6Dh 00h 00h COMMENTS Soft Reset, Main Controller Soft Reset, Main Controller Soft Reset, Auxiliary Controller Soft Reset, Auxiliary Controller Clear DDX Reset, Set DDX Gain=3X, Proprietary (1dB/step)vol. mode, Main Clear DDX Reset, Set DDX Gain=3X, Proprietary (1dB/step)vol. mode, Aux Clear EAPD, Main Clear EAPD, Aux

*Unmute and Set Desired Channel Volume

Main/Aux R/ REG DATA COMMENTS SELECT W 0 W 03h Set Volume to Desired Setting on Right Channel 0 W 02h Set Volume to Desired Setting on Left and Unmute Left and Right Channels 0 W 38h Set Volume to Desired Setting and Unmute Left Surround Channel 0 W 39h Set Volume to Desired Setting and Unmute Right Surround Channel 1 W 08h Set Bass/Treble Boost/Cut to Desired Setting (See Appendix D) 1 W 03h Set Volume on LFE Channel(U2 Right) to Desired Setting 1 W 02h 3Fh Unmute LFE Channel(U2 Right) 1 W 38h Set Volume to Desired Setting and Unmute Center Channel(U2 Left Surround) * When using the sample rate converter (SRC), it is mandatory to apply a valid input signal to the DDX-4100 prior to unmuting, refer to DDX-4100 errata at; http://www.apogeeddx.com/ER_DDX_4100.pdf .

BIQUAD Coefficients (Optional)

2 As an additional example of I C setting, biquad filters are used to perform speaker equalization and crossover functions. The biquad filters should be written when the devices are muted, i.e., prior to the Unmute commands above.

The biquad coefficients were obtained using Apogees Filter generation software and were generated in order to equalize a +4dB bump at 2kHz with Q = 1.414 on the L/R/LS/RS/C channels and on the LFE channel a 2nd order Butterworth Low-pass filter with a cutoff of 150Hz was used. L/R/LS/RS/C Coefficients: B2: 0x658E0h (B0)-1: 0xFA043h A2: 0x5F923h A1/2: 0x94061h B1/2: 0x94061h LFE Coefficients: B2: 0x00032h (B0)-1: 0x80032h A2: 0x7C7EAh A1/2: 0x81C6Fh B1/2: 0x00032h Following are the steps necessary to write coefficients via I2 C Write 8 middle data bits at I2 C address 78h Write 8 lower data bits at I2 C address 79h Write 8 bit address at I2 C address 7Ah coeff INDEX +40h Write 4 upper data bits and R/W bit at I2 C address

11

PRELIMINARY

Main/Aux SELECT 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

R/ W W W W W W W W W W W W W W W W W W W W W W W W W W W W W W W W W W W W W W W W W W W W W W W W W W W W W W W W W W

REG 78h 79h 7Ah 7Bh 78h 79h 7Ah 7Bh 78h 79h 7Ah 7Bh 78h 79h 7Ah 7Bh 78h 79h 7Ah 7Bh 78h 79h 7Ah 7Bh 78h 79h 7Ah 7Bh 78h 79h 7Ah 7Bh 78h 79h 7Ah 7Bh 78h 79h 7Ah 7Bh 78h 79h 7Ah 7Bh 78h 79h 7Ah 7Bh 78h 79h 7Ah 7Bh 78h 79h 7Ah 7Bh 78h

DATA 58h E0h 40h 06h A0h 43h 41h 0Fh F9h 23h 42h 05h 40h 61h 43h 09h 40h 61h 44h 09h 58h E0h 54h 06h A0h 43h 55h 0Fh F9h 23h 56h 05h 40h 61h 57h 09h 40h 61h 58h 09h 00h 32h 40h 00h 00h 32h 41h 08h C7h EAh 42h 07h 1Ch 6Fh 43h 08h 00h

COMMENTS Write [B2 Biqaud 0] Coeff bit [15..8] for LR Channel on Main Controller Write [B2 Biquad 0] Coeff bit [7..0] for LR Channel on Main Controller Write [B2 Biquad 0] Coeff address for LR Channel on Main Controller Write [B2 Biquad 0] Coeff bit [19..16] LR Channel on Main Controller Write [((B0) 1) Biquad 0] Coeff bit [15..8] for LR Channel on Main Controller Write [((B0) 1) Biquad 0] Coeff bit [7..0] for LR Channel on Main Controller Write [((B0) 1) Biquad 0] Coeff address for LR Channel on Main Controller Write [((B0) 1) Biquad 0] Coeff bit [19..16] LR Channel on Main Controller Write [A2 Biqaud 0] Coeff bit [15..8] for LR Channel on Main Controller Write [A2 Biquad 0] Coeff bit [7..0] for LR Channel on Main Controller Write [A2 Biquad 0] Coeff address for LR Channel on Main Controller Write [A2 Biquad 0] Coeff bit [19..16] LR Channel on Main Controller Write [(A1/2) Biquad 0] Coeff bit [15..8] for LR Channel on Main Controller Write [(A1/2) Biquad 0] Coeff bit [7..0] for LR Channel on Main Controller Write [(A1/2) 1) Biquad 0] Coeff address for LR Channel on Main Controller Write [(A1/2) 1) Biquad 0] Coeff bit [19..16] LR Channel on Main Controller Write [(B1/2) Biquad 0] Coeff bit [15..8] for LR Channel on Main Controller Write [(B1/2) Biquad 0] Coeff bit [7..0] for LR Channel on Main Controller Write [(B1/2) 1) Biquad 0] Coeff address for LR Channel on Main Controller Write [(B1/2) 1) Biquad 0] Coeff bit [19..16] LR Channel on Main Controller Write [B2 Biqaud 0] Coeff bit [15..8] for LSRS Channel on Main Controller Write [B2 Biquad 0] Coeff bit [7..0] for LSRS Channel on Main Controller Write [B2 Biquad 0] Coeff address for LSRS Channel on Main Controller Write [B2 Biquad 0] Coeff bit [19..16] LSRS Channel on Main Controller Write [((B0) 1) Biquad 0] Coeff bit [15..8] for LSRS Channel on Main Controller Write [((B0) 1) Biquad 0] Coeff bit [7..0] for LSRS Channel on Main Controller Write [((B0) 1) Biquad 0] Coeff address for LSRS Channel on Main Controller Write [((B0) 1) Biquad 0] Coeff bit [19..16] LSRS Channel on Main Controller Write [A2 Biqaud 0] Coeff bit [15..8] for LSRS Channel on Main Controller Write [A2 Biquad 0] Coeff bit [7..0] for LSRS Channel on Main Controller Write [A2 Biquad 0] Coeff address for LSRS Channel on Main Controller Write [A2 Biquad 0] Coeff bit [19..16] LSRS Channel on Main Controller Write [(A1/2) Biquad 0] Coeff bit [15..8] for LSRS Channel on Main Controller Write [(A1/2) Biquad 0] Coeff bit [7..0] for LSRS Channel on Main Controller Write [(A1/2) 1) Biquad 0] Coeff address for LSRS Channel on Main Controller Write [(A1/2) 1) Biquad 0] Coeff bit [19..16] LSRS Channel on Main Controller Write [(B1/2) Biquad 0] Coeff bit [15..8] for LSRS Channel on Main Controller Write [(B1/2) Biquad 0] Coeff bit [7..0] for LSRS Channel on Main Controller Write [(B1/2) 1) Biquad 0] Coeff address for LSRS Channel on Main Controller Write [(B1/2) 1) Biquad 0] Coeff bit [19..16] LSRS Channel on Main Controller Write [B2 Biqaud 0] Coeff bit [15..8] for SUB (LR) Channel on AUX Controller Write [B2 Biquad 0] Coeff bit [7..0] for SUB (LR) Channel on AUX Controller Write [B2 Biquad 0] Coeff address for SUB (LR) Channel on AUX Controller Write [B2 Biquad 0] Coeff bit [19..16] SUB (LR) Channel on AUX Controller Write [((B0) 1) Biquad 0] Coeff bit [15..8] for SUB (LR) Channel on AUX Controller Write [((B0) 1) Biquad 0] Coeff bit [7..0] for SUB (LR) Channel on AUX Controller Write [((B0) 1) Biquad 0] Coeff address for SUB (LR) Channel on AUX Controller Write [((B0) 1) Biquad 0] Coeff bit [19..16] SUB (LR) Channel on AUX Controller Write [A2 Biqaud 0] Coeff bit [15..8] for SUB (LR) Channel on AUX Controller Write [A2 Biquad 0] Coeff bit [7..0] for SUB (LR) Channel on AUX Controller Write [A2 Biquad 0] Coeff address for SUB (LR) Channel on AUX Controller Write [A2 Biquad 0] Coeff bit [19..16] SUB (LR) Channel on AUX Controller Write [(A1/2) Biquad 0] Coeff bit [15..8] for SUB (LR) Channel on AUX Controller Write [(A1/2) Biquad 0] Coeff bit [7..0] for SUB (LR) Channel on AUX Controller Write [(A1/2) 1) Biquad 0] Coeff address for SUB (LR) Channel on AUX Controller Write [(A1/2) 1) Biquad 0] Coeff bit [19..16] SUB (LR) Channel on AUX Controller Write [(B1/2) Biquad 0] Coeff bit [15..8] for SUB (LR) Channel on AUX Controller

12

PRELIMINARY

1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

W W W W W W W W W W W W W W W W W W W W W W W

79h 7Ah 7Bh 78h 79h 7Ah 7Bh 78h 79h 7Ah 7Bh 78h 79h 7Ah 7Bh 78h 79h 7Ah 7Bh 78h 79h 7Ah 7Bh

32h 44h 00h 58h E0h 54h 06h A0h 43h 55h 0Fh F9h 23h 56h 05h 40h 61h 57h 09h 40h 61h 58h 09h

Write [(B1/2) Biquad 0] Coeff bit [7..0] for SUB (LR) Channel on AUX Controller Write [(B1/2) 1) Biquad 0] Coeff address for SUB (LR) Channel on AUX Controller Write [(B1/2) 1) Biquad 0] Coeff bit [19..16] SUB (LR) Channel on AUX Controller Write [B2 Biqaud 0] Coeff bit [15..8] for C (LSRS) Channel on AUX Controller Write [B2 Biquad 0] Coeff bit [7..0] for C (LSRS) Channel on AUX Controller Write [B2 Biquad 0] Coeff address for C (LSRS) Channel on AUX Controller Write [B2 Biquad 0] Coeff bit [19..16] C (LSRS) Channel on AUX Controller Write [((B0) 1) Biquad 0] Coeff bit [15..8] for C (LSRS) Channel on AUX Controller Write [((B0) 1) Biquad 0] Coeff bit [7..0] for C (LSRS) Channel on AUX Controller Write [((B0) 1) Biquad 0] Coeff address for C (LSRS) Channel on AUX Controller Write [((B0) 1) Biquad 0] Coeff bit [19..16] C (LSRS) Channel on AUX Controller Write [A2 Biqaud 0] Coeff bit [15..8] for C (LSRS) Channel on AUX Controller Write [A2 Biquad 0] Coeff bit [7..0] for C (LSRS) Channel on AUX Controller Write [A2 Biquad 0] Coeff address for C (LSRS) Channel on AUX Controller Write [A2 Biquad 0] Coeff bit [19..16] C (LSRS) Channel on AUX Controller Write [(A1/2) Biquad 0] Coeff bit [15..8] for C (LSRS) Channel on AUX Controller Write [(A1/2) Biquad 0] Coeff bit [7..0] for C (LSRS) Channel on AUX Controller Write [(A1/2) 1) Biquad 0] Coeff address for C (LSRS) Channel on AUX Controller Write [(A1/2) 1) Biquad 0] Coeff bit [19..16] C (LSRS) Channel on AUX Controller Write [(B1/2) Biquad 0] Coeff bit [15..8] for C (LSRS) Channel on AUX Controller Write [(B1/2) Biquad 0] Coeff bit [7..0] for C (LSRS) Channel on AUX Controller Write [(B1/2) 1) Biquad 0] Coeff address for C (LSRS) Channel on AUX Controller Write [(B1/2) 1) Biquad 0] Coeff bit [19..16] C (LSRS) Channel on AUX Controller

13

PRELIMINARY

3.3V

VB+

VB+ REGULATED POWER SUPPLY LEFTA LEFTB RIGHTA RIGHTB LEFT+ SPKR1

SDATA1 contains Left and Right channels. SDATA2 contains Left and Right Surround channels. SDATA3 contains Center and LFE channels.

LEFT -

8 OHM

3.3V SDATA1 SDATA2 SDATA3 LRCK SCK SDI1 SDI2 LRCK SCK SDA SCL1 PWDN RESET XTO LEFTA LEFTB RIGHTA RIGHTB SLEFTA SLEFTB SRIGHTA SRIGHTB EAPD1

EAPD1 TWARN1

RIGHT+

SPKR2

RIGHT -

8 OHM

L,R OUTPUTS

VB+ SLEFTA SLEFTB SRIGHTA SRIGHTB SLEFT+ SPKR3

SLEFT-

8 OHM

5.1 CHANNEL DE CODER

L,R,LS,RS PROCESSING SPKR4

EAPD1 TWARN2

SRIGHT+

SRIGHT-

8 OHM

SDA SCL1 SCL2

LS,RS OUTPUTS

VB+ CENTER+ TWARN1 TWARN2 TWARN3 TWARN4 PWDN SPKR6

CENTER TWARN3

8 OHM

CENTERA CENTERB SYSTEM MICROCONTROLLER

EAPD2 CENTERA 3.3V CENTERB SDI2 SDI3 LRCK SCK SDA SCL2 PWDN RESET EAPD2 XTI EAPD2 CENTER OUTPUT

SPKR6 VB+ LFEA LFEB LFEA LFEB LFE+ LFE 4OHM

POWER -ON- RESET

CTR, LFE PROCESSING

TWARN4

SUBWOOFER OUTPUT

SHEET 1: SYSTEM LEVEL DIAGRAM FOR DESIGN EXAMPLE 2

14

PRELIMINARY

C1 +3.3V + 22uF 6.3V C2 100nF

PWDN

EAPD1

44 43 42 41 40 39 38 37 36 35 34

U1 SDI1= L, R SDI2 = LS, RS SDI3 = C, SUB SDI1 SDI2 LRCK SCK RESET SDA SCL_1 1 2 3 4 5 6 7 8 9 10 11 PWDN CKOUT VDD_5 GND_5 SCKO SDO_3 SDO_2 SDO_1 LRCKO EAPD SLEFT_A

+3.3V

C4 100nF

TEST_MODE VDD_2 XTI XTO GND_2 VCC RXP RXN VSS LFE_B LFE_A

SDI_1/SDATA_OUT SDI_2/SDATA_IN LRCKI/SYNC BCKI/BIT_CLK VDD_1 GND_1 RESET AC97_MODE SDA SCL SA

SLEFT_B VDD_4 GND_4 LEFT_A LEFT_B RIGHT_A RIGHT_B VDD_3 GND_3 SRIGHT_A SRIGHT_B

33 32 31 30 29 28 27 26 25 24 23

SLEFT_A SLEFT_B +3.3V LEFTA LEFTB RIGHTA RIGHTB +3.3V C5 C3 100nF

100nF

12 13 14 15 16 17 18 19 20 21 22

DDX4100

SRIGHT_A SRIGHT_B

L1 R1 +3.3V +3.3V 100nH 1 MEG Y1 XTO 24.576MHz C9 18pF C10 18pF C6 100nF C7 100nF C8 100nF

SHEET 2: MAIN DDX-4100 PROCESSOR FOR DESIGN EXAMPLE 2

+3.3V

C11 C12

22uF 6.3V 100nF

EAPD2 PWDN CENTER_A CENTER_B 44 43 42 41 40 39 38 37 36 35 34

+3.3V

SDI3 LRCK SCK

C14 100nF

RESET SDA SCL2

TEST_MODE VDD_2 XTI XTO GND_2 VCC RXP RXN VSS LFE_B LFE_A

1 2 3 4 5 6 7 8 9 10 11

PWDN CKOUT VDD_5 GND_5 SCKO SDO_3 SDO_2 SDO_1 LRCKO EAPD SLEFT_A

SDI1= L, R SDI2 = LS, RS SDI3 = C, SUB

U2

SDI_1/SDATA_OUT SDI_2/SDATA_IN LRCKI/SYNC BCKI/BIT_CLK VDD_1 GND_1 RESET AC97_MODE SDA SCL SA

SLEFT_B VDD_4 GND_4 LEFT_A LEFT_B RIGHT_A RIGHT_B VDD_3 GND_3 SRIGHT_A SRIGHT_B

33 32 31 30 29 28 27 26 25 24 23

+3.3V C13 LFEA LFEB +3.3V C15 100nF 100nF

XTO +3.3V C16 100nF C17 100nF

12 13 14 15 16 17 18 19 20 21 22

DDX4100

L2 +3.3V 100nH C18 100nF

SHEET 3: AUXILIARY DDX-4100 PROCESSOR FOR DESIGN EXAMPLE 2

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PRELIMINARY

L/R OUTPUTS: Refer to SHEET 4 (LEFT AND RIGHT OUTPUTS) L/R SURROUND OUTPUTS: Refer to SHEET 5 (LEFT AND RIGHT SURROUND OUTPUTS) CENTER OUTPUT: Refer to SHEET 6 (CENTER OUTPUT) SUBWOOFER OUTPUT: Refer to SHEET 7 (SUBWOOFER OUTPUT)

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PRELIMINARY

Appendix A DDX-4100 Overview

Provided is an overview of the DDX-4100 for quick references but, it is suggested that the user be familiar with the DDX-4100 Datasheet prior to proceeding. The DDX-4100 Digital Audio Processor performs preamplifier functions between the digital audio data input and the DDX power devices as shown in Figure 1. The processor supports two input configurations; AC97 input mode or Serial/SPDIF input mode, with the selection made via a dedicated pin.

SA 11

SCL 10

SDA 9

LRCK1/SYNC3 BICKI/BIT_CL 4 SDI_1/AC97_OUT SDI_2/AC97_IN 1 2

I2 S

I2 C ROM DDX

30 29 28 27 34 33 24 23 22

LEFT_A LEFT_B RIGHT_A RIGHT_B SLEFT_A SLEFT_B SRIGHT_A SRIGHT_B LFE_A LFE_B

RXP RXN

18 19

S/PDIF SRC DSP

21

36 40

LRCK0 BICKO

IS RAM AC97
RESET 7

37 38 39

SDO_1 SDO_2 SDO_3

PLL
14 XTI 15 XTO 43 CKOUT

PowerDown
44 PWDN

35

EAPD

DDX-4100 Block Diagram- Figure 1 Digital Audio Inputs In the Serial/SPDIF mode, a stereo S/PDIF or a 4 channel three-wire programmable serial input interface supports any sampling frequency in the continuous range from 32 to 96 KHz. The programmable serial interface supports up to four channels as two synchronized stereo data steams. It accepts all common formats including the popular IIS protocol. Operation of the S/PDIF or the Serial inputs is mutually exclusive. The SPDIF input routes its 2 channels to the left and right channels within the DDX-4100. The serial interface routes its 4 channels to the left, right, left surround, and right surround channels. In the design examples only the serial interface is used. The AC97 interface, mainly used on PC motherboards, is compliant with Audio Codec 97 Revision 2.1 specification in terms of the protocol used. AC97 is not covered in this application note. For AC97 applications assistance contact Apogee Technical Support at; http://www.apogeeddx.com/apogee_form.html. I2 C The DDX-4100 provides an I2 C control interface. This interface must be connected to the system microcontroller for control of the DDX-4100. The DDX4100 will operate only in slave mode. For specifics of the I2 C protocol refer to the DDX-4100 datasheet and DDX-4100 errata.

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PRELIMINARY

Sample Rate Converter The first processing block reached by the signal in the DDX4100 is the sample rate converter (SRC). The SRC resamples all incoming data to a constant output sample rate regardless of the input sample frequency. This sample rate is determined by the internal master clock and will be 48kHz when using the recommended 24.576MHz crystal. The SRC can handle input sample rates of 32kHz to 96kHz. It is required when using the SRC to disable the double buffering feature via configuration register A. It is also mandatory to apply a valid input signal to the DDX 4100 prior to unmuting. Note that the SRC lock indicator, (register 0x77, bit 0), incorrectly shows SRC lock valid at power up even with no signal applied, refer to DDX4100 errata at; http://www.apogeeddx.com/ER_DDX_4100.pdf. DSP The DDX4100 contains a fixed function 20-bit audio DSP (Figure 2 is an example of the digital audio signal flow in the DSP). This DSP performs the functions of tone control, programmable EQ, and volume control. The output of the DSP goes to the serial output ports and to the DDX blocks.

Bass / Treble

PreScale

Biquads

Volume

Figure 2: Signal Flow in the DSP The bass/treble tone controls only affect the inputs on the SDI_1 pin. When boosting using the bass/treble controls it becomes possible to clip the input signal. This is because the volume control is positioned after the bass/treble functionality. To avoid this possibility it is necessary to attenuate the input signal to the DDX-4100. In Appendix C more information on how to prevent clipping is provided. The programmable EQ allows download of user generated coefficients from a micro-controller and can generate high and low-pass filters for crossover and parametric filters for frequency response adjustment. Apogee provides a graphical interface filter generation software for generating coefficients formatted for downloading to the DDX4100. Detailed design information for filters supported by the DDX-4100 can be found at; http://www.apogeeddx.com/BQD_Appnote.PDF. The volume controls are independent per channel. DDX The DDX processing in the DDX-4100 converts the incoming 48kHz PCM data streams into a high-quality 384kHz DDX pulse width modulated (PWM) signals to drive the power devices Software Control Using the I2 C interface to write to internal registers controls the functionality of the DDX-4100. Table 1 shows an overview of the registers and their respective purpose. When using serial or SPDIF input, I2 C is the control interface and the registers are 8-bits wide with every address being used.

18

PRELIMINARY

Table 1 DDX-4100 Registers

DDX-4100 Datasheet Paragraph 12.1 12.2 12.3 12.4 12.5 12.6 12.7 12.8 12.9 Register Name RESET LRVOL TONE POWERDOWN AUDIO ID AUDIO STATUS SAMPLE RATE 6 CHNL. VOLUME CRA Serial / S/PDIF 00,01 02,03 08,09 26 N/A N/A N/A 36,38,39 5A, 5B AC97 00 02 08 26 28 2A 2C-34 36,38 5A
1

Comments Sets all registers to their default values. Unmute and sets Left & Right volume levels Sets Bass and Treble levels on Left & Right Channels Power-Down controls for internal clock and volume fadeout and mute. Identifies Extended Audio Features (AC97 only) Read-Only Extended Audio Feature Readiness (AC97 only) Sample Rate Control Registers (AC97 only) Mute and Volume control for LFE, Center (AC97 only), Left Surround and Right Surround Channels. Configuration Register A: Control of AC97, Double Buffer Mode, DDX Gain, Reset, Zero Detect and Power Mode, PLL factor and Bypass, MCKOut, I2S.SPDIF Select, SRC Threshold, DRLL Debug Mode and SRC Bypass. Configuration Register B: Control of I2S Input Alignment, BICK Polarity, BiCKI/BICKO and LRCKI/LRCKO Master/Slave, LRCKI/LRCKO Polarity, Input/Output MSB/LSB Select, I2S Output Alignment Phantom Center Channel Enable (AC97 only) Enable Static EQ and/or Side-Firing Surround Channels. Enable Bass Management (Mix 6 channels to SBW) Bypass DSP block BIST and Status Register; Read SRC and S/PDIF Lock, Auto-Mute on AC3 Frame Header or no CH1_STATUS EQ and Bass Management Coefficients and Scale Factors Vendor Ids, Read-Only.

12.10

CRB

5C, 5D

5C

12.11 12.12 12.13 12.14 12.15 12.16 12.17

PHANTOM STATIC EQ / SIDE BASS MGMT BYPASS BASR COEFFS VENDOR ID

N/A 71 73 75 77 78,79, 7A,7B 7C,7D, 7E,7F

60 70 72 74 76 78,7A 7C,7E

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PRELIMINARY

Appendix B 5.1 Channel Power Configurations Using the DDX-2060 and DDX-2100 Power Devices
There are several different 5.1 channel system configurations possible using the DDX chip set solution. For example, the block diagram for Design 1 demonstrates a solution that provides 5x35W plus 1x70W using two DDX-4100 devices and four DDX-2060 power devices. Since the DDX power devices can be configured in stereo or signal channel mode multiple configurations can be implemented to provide to meet the power output requirements of the system. As an example, eight configurations are shown below using the DDX-2060 and DDX2100 power devices. 5.1 Channel System Configurations Output Power Speaker Impedance # Devices Configuration* 6x35W 8 Ohms 3 DDX-2060s 5x35W + 8 Ohms 3 DDX-2060s 1x70W 4 Ohms 1 DDX-2060 6x70W 4 Ohms 6 DDX-2060s 5x70W+ 4 Ohms 5 DDX-2060s 1x140W 2 Ohms 2 DDX-2060s 6x50W 8 Ohms 3 DDX-2100s 5x50W+ 8 Ohms 4 DDX-2100s 1x100W 4 Ohms 1 DDX-2100s 6x100W 4 Ohms 6 DDX-2100s 5x100W+ 4 Ohms 5 DDX-2100s 1x200W 2 Ohms 2 DDX-2100s *Using a supply voltage of +28 VDC for the DDX-2060 and +36 VDC for the DDX-2100. Device Output Configuration Two channel Two channel Mono Mono Mono Mono Combined Two channel Two channel Mono Mono Mono Mono Combined

The system configuration power is determined by the supply voltage, the speaker impedance, the capabilities of the power device and how the power devices is configured (i.e., two channel, mono or mono combined). Lower power outputs can be obtained in each of these configurations if needed by reducing supply voltage or increasing speaker impedance. http://www.apogeeddx.com/Apogee_01_applications.PDF contains more detailed information , specifically, graphical plots of power output vs. speaker impedance and voltage are provided. If a power amp lifier is required for the subwoofer channel, typically referred to as the .1 channel, it is generally advantageous that this channel provide a higher power output. The original intention of the .1 channel was to provide more headroom at low-frequencies. Higher output from the subwoofer speaker compared to the other speaker outputs is suggested for proper playback of surround sound material.

20

PRELIMINARY

Appendix C Avoiding Signal Clipping when Using Bass/Treble Gain

The DDX-4100 includes a bass/treble function that can be set between +/- 12 dB of gain using the I2 C registers. In cases where the input signal level to the bass/treble block is above 12dB and the bass/treble settings are above 0 dB, signal clipping can occur. In order to best utilize this function, pre-scaling can be performed using the volume control in the surround decoder. When combined with the DDX-4100 volume control the overall desired system gain can be implemented. The table below shows the Decoder and DDX-4100 volume control registers for a given desired overall system volume. MASTER VOLUME TABLE Desired System Volume Setting 0dB -1dB -2dB : -11dB -12dB -13dB : -29dB -30dB : Decoder Volume Setting 0dB -1dB -2dB : -11dB -12dB -12dB : -12dB -12dB : DDX-4100 Volume Setting 0dB 0dB 0dB : 0dB 0dB -1dB : -17dB -18dB :

21

PRELIMINARY

Appendix D Using Volume Offsets to Increase Relative Gain on the Subwoofer Channel
It is suggested to have a volume level offset for the Subwoofer Channel. It is also recognized that a higher overall maximum gain is often needed for the subwoofer channel. Using Design 2 as an example we can accomplish this by using the Bass/Treble boost feature on the Subwoofer channel. In the auxiliary DDX-4100, Bass(U2), is used to add the desired gain to the subwoofer channel, t e Subwoofer Offset Volume Table h demonstrates this below. SUBWOOFER OFFSET VOLUME TABLE System Decoder Main Aux BASS(U2) Volume Volume 4100 4100 Bass/Treble Setting Setting Volume Volume Boost/Cut Setting Setting Setting 0dB 0dB 0dB 0dB +6dB -1dB -1dB 0dB 0dB +6dB : : : : : -11dB -11dB 0dB 0dB +6dB -12dB -12dB 0dB 0dB +6dB -13dB -12dB -1dB 0dB +5dB : : : : : -18dB -12dB -6dB 0dB 0dB -19dB -12dB -7dB -1dB 0dB : : : : : -29dB -12dB -17dB -11dB 0dB -30dB -12dB -18dB -12dB 0dB : : : : : Note that the Main 4100 drives L,R,LS and RS Channels and the Aux 4100 drives Center and Sub Channels.

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PRELIMINARY