reset

Up counter Port(clk,resetinput , z(0-3)output) Z(23)=S0 [SIGNAL] z(2)=S3 z(3)=S4 z(0)=S1 z(1)=S2

Binary to 7 segment display Port(A(0-3), z(0 to 6))

z(0)=Z(0) D I z(2)=Z(2) z(3)=Z(3) z(4)=Z(4) z(5)=Z(5) z(6)=Z(6) S P L A y

z(1)=Z(1)

clk

Clock devider circuit[up counter] port(clk-input, Z(0-23)-output )

AS shown this is internal architecture of our project. When we declare these components into single structure some more things have to define. Final architecture has ports 1 > CLK it difine clk as-clk=>CLK. 2> RESET it define reset as- reset=>RESET. 3> last o/p Z as shown in signals before display z(0)=>Z(0) All 3 components first individually saved and compiledthen implemented into final structure. Plz make sure new project.

1)
library ieee;

Clock Devider Circuit- upcnt_dvid

use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; entity upcnt_dvid is port (clk:in std_logic; z:out std_logic_vector(23 downto 0)); end upcnt_dvid; architecture behav of upcnt_dvid is signal y:std_logic_vector(23 downto 0); begin process(clk) begin if clk='1' then y<=y+1; end if; end process; z<=y; end behav;

*plz save file as the name of entity. Compile also.

2) UP-COUNTER - upcnt
library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; entity upcnt is port (clk,reset:in std_logic; z:out std_logic_vector(3 downto 0)); end upcnt; architecture behav of upcnt is signal y:std_logic_vector(3 downto 0); begin process(clk,reset) begin if reset='1' then y<="0000"; elsif clk='1' then y<=y+1; end if; end process; z<=y; end behav;

3) Binary to 7 segment display - hex7seg

library ieee; use ieee.std_logic_1164.all; entity hex7seg is port(A:in std_logic_vector(3 downto 0); z:out std_logic_vector(0 to 6)); end hex7seg; architecture behav of hex7seg is begin process(A) begin case(A) is when "0000"=> z<="1111110"; when "0001"=> z<="1100000"; when "0010"=> z<="1101101"; when "0011"=> z<="1111001"; when "0100"=> z<="0110011"; when "0101"=> z<="1011011"; when "0110"=> z<="1011111"; when "0111"=> z<="1110000"; when "1000"=> z<="1111111"; when "1001"=> z<="1111011";

when "1010"=> z<="1110111"; when "1011"=> z<="0011111"; when "1100"=> z<="1001110"; when "1101"=> z<="0111101"; when "1110"=> z<="1001111"; when others=> z<="1000111"; end case; end process; end behav;

In this 0 to 9 & A,b,C,d,E,F are definedall hex numbers. Now after all these 3 the final structure will start.

4)Final Structural Prject - hexdisp

library ieee; use ieee.std_logic_1164.all; entity hexdisp is port(CLK,RESET:in std_logic; Z:out std_logic_vector(0 to 6); E:out std_logic); end hexdisp; architecture struct of hexdisp is signal S0,S1,S2,S3,S4: std_logic; component upcnt_dvid is port(clk:in std_logic; z:out std_logic_vector(23 downto 0)); end component; component upcnt is port(clk,reset:in std_logic; z:out std_logic_vector(3 downto 0)); end component; component hex7seg is port(A:in std_logic_vector(3 downto 0); z:out std_logic_vector(0 to 6)); end component;

begin E<='1'; comp1:upcnt_dvid port map (clk=>CLK,z(23)=>S0); comp2:upcnt port map (clk=>S0,reset=>RESET,z(0)=>S1,z(1)=>S2,z(2)=>S3,z(3)=>S4); comp3:hex7seg port map (A(0)=>S1,A(1)=>S2,A(2)=>S3,A(3)=>S4,z(0)=>Z(0),z(1)=>Z(1),z(2)=>Z(2), z(3)=>Z(3),z(4)=>Z(4),z(5)=>Z(5),z(6)=>Z(6)); end struct;

plz compile..before save file into same project by SAME name as ENTITY NAME. Now Asssign pins CLKsystem clock pin RESETsystem reset pin Epin 21 or any of 7seg display ENABLE pin Z[0] t0 Z[6] in 7 seg display pin. Now implement. Enjoy..ravindra mathanker(9993699838)

Best of luck. Some syntax may be wrong by mistake so be carefull.