1

13 FIELD EFFECT TRANSISTOR (FET) AMPLIFIER

13.1 Introduction

Another type of transistor used in amplifiers is the Field effect Transistor (FET). The
FET is controlled by an input voltage whilst the BJT is controlled by an input current.

A general block diagram of a FET looks like:


G
S
D
V
GS
I
D


Figure 13.1

G is the Gate, S is the Source and D is the Drain. The input is the voltage V
GS
and
the output is the drain current I
D
.

There are various types of FET depending on their structure, for example Junction
FET. We will concentrate on the Enhancement MOSFET, which encompasses NMOS
and PMOS which we met when discussing logic gates (Section (5.4)).

13.2 Enhancement MOSFET

We will discuss the structure of the MOSFET in Section 17. For now we treat is as a
circuit element.

There are two types of Enhancement MOSFET:

n-channel (NMOS)

This has the conventional symbol:


Copyright 2005 by Pearson Education, Inc.
Upper Saddle River, New Jersey 07458
All rights reserved.

Figure 13.2

We will use the following simplified symbol that was used in the discussion of digital
logic gates:
2

Figure 13.3


p-channel (PMOS)

This has the conventional symbol


Copyright 2005 by Pearson Education, Inc.
Upper Saddle River, New Jersey 07458
All rights reserved.
Figure 13.4

with the following simplified symbol (used when discussing logic gates):


Figure 13.5

NMOS rather than PMOS is used in amplifier applications because electron mobility is
larger than hole mobility so n-channel devices are faster. Hence we will concentrate
on single transistor circuits using NMOS transistor.

13.3 Characteristic Curve

In order to design an amplifier around an NMOS transistor, we need to look at the
characteristic curve which relates the output (I
D
) to the input (V
GS
):

3


Copyright 2005 by Pearson Education, Inc.
Upper Saddle River, New Jersey 07458
All rights reserved.
Figure 13.6

Here, V
GS(th)
is a threshold voltage. The drain current, I
D
is given by

> +
s
=
) (
2
) (
) (
for ) 1 ( ) (
for 0
th GS GS DS th GS GS
th GS GS
D
V V V V V K
V V
I

(13.1a)

where K is a constant depending on the size and capacitance of the MOSFET, is a
constant with a value of approximately 0.01 V
-1
and V
DS
is the voltage difference
between Drain and Source. In many cases the term
DS
V in Equation (13.1a) can be
neglected.

It can be shown that the second Equation in (13.1a) is valid as long as the following
condition holds:

) (th GS GS DS
V V V > (13.1b)

where V
DS
is the voltage drop between Drain and Source.

Whenever we do a calculation for MOSFET amplifiers we must make sure that
Equation (13.1b) holds otherwise the amplifier will not work properly; a distorted
output signal will occur.

In addition we should check that V
GS
is above the threshold:

) (th GS GS
V V > (13.1c)


13.4 DC Biasing

Like with the BJT, in order to amplify ac signals, we need to determine a dc (bias)
operating point as indicated by Q in Figure 13.6. The minimum value of the input
Q
4
gate-source voltage (dc+ac) should be greater than V
GS(th)
otherwise clipping of the
output signal will take place. In MOSFET amplifiers, the voltage-divider bias method
used in BJT amplifiers is commonly used see Section 13.6.2 later.

13.5 Small Signal AC Model for NMOS

We now need to model the MOSFET for small ac signals.

Suppose Q-point is as shown below and i
d
and v
gs
are variations of the drain current
and gate-source voltage about their dc values I
D
and V
GS
:


Copyright 2005 by Pearson Education, Inc.
Upper Saddle River, New Jersey 07458
All rights reserved.
Figure 13.7

Now for small signal deviations around Q the curve of I
D
:V
GS
can be approximated by
a straight line and we can write

~
gs
d
v
i
slope at Q-point
m
g = (13.2)

where g
m
is known as the transconductance (units AV
-1
or Siemens (S)) which is the
inverse of the resistance.

Now slope at Q-point =
GS
D
dV
dI
(13.3)

Differentiating both sides of the lower equation in Equation (13.1a) with respect to
V
GS
and ignoring
DS
V on the right-hand side of this equation:

) ( 2
) (th GS GS
GS
D
m
V V K
dV
dI
g = = (13.4)

The lower equation in (13.1a) can be approximated by putting = 0 so that:

Q
v
gs
i
d
5
) (
2
) (
for ) (
th GS GS th GS GS D
V V V V K I > = (13.5)

Solving this equation for V
GS
V
GS(th)
:

K
I
V V
D
th GS GS
=
) (
(13.6)

Substituting for V
GS
V
GS(th)
from (13.6) into (13.4):

D
D
m
KI
K
I
K g 2 2 = = (13.7)

Hence the transconductance g
m
depends on both K (which depends on the physical
properties of the MOSFET) and on the dc operating conditions through the dc drain
current I
D
.

From Equation (13.2), we can write for the relation between the ac drain current and
the ac gate-source voltage as:

gs m d
v g i = (13.8)

with g
m
given by Equation (13.7).

This current is at the output of the NMOS and hence the output ac drain current is
modelled as a current source g
m
v
gs
.


Figure 13.8

In practice, there is also an ac resistance, r
ds
, between Drain and Source which is
defined by

D
DS
ds
dI
dV
r = (13.9)

To determine r
ds
we first note that

|
.
|

\
|
= =
DS
D D
DS
ds
dV
dI dI
dV
r
1
(13.10)
6
Differentiating both sides of the lower equation in (13.1) with respect to V
DS:

D th GS GS
DS
D
I V V K
dV
dI
= = ] ) ( [
2
) (

(13.11)


where we have used Equation (13.5) to substitute I
D
for the term in square brackets.

Substituting for
DS
D
dV
dI
from (13.11) into (13.10):

D
ds
I
r

1
= (13.12)

which, as for the transconductance, depends on the dc operating conditions through
I
D
.

Hence the modified model for the NMOS output including this resistance looks like:


Figure 13.9

For the BJT, the input was modelled by a dynamic resistance r
t
. Now because of its
physical properties, the MOSFET has a much larger input resistance that the BJT and
the former can be modelled as having an open-circuit as the input.

Hence the complete small signal ac model of the MOSFET looks like:



Figure 13.10

In some analyses, r
ds
is approximated by an open circuit but we shall keep this in.


7
13.6 Common Source MOSFET Amplifier

13.6.1 Circuit

The Source for the FET is analogous to the Emitter in the BJT. One can construct a
Common Source MOSFET amplifier similar to the Common Emitter (Figure 12.18) as
shown below:


Figure 13.11

v
SIG
and R
SIG
are the input voltage and resistance from the previous stage. R
L
is the
load resistance. R
1
and R
2
form a potential divider that fixes the gate-source
voltage, V
GS
. R
D
and R
S
are external resistors connected to the Drain and Source
respectively that are used in the dc biasing. C
1
and C
2
are isolation capacitors that
ensure that R
SIG
and R
L
do not affect the dc biasing. It turns out that, analogous to
R
E
in the BJT amplifier, R
S
lowers the ac gain. To prevent R
S
affecting the ac gain but
to ensure that it still can be used in biasing of the amplifier, a bypass capacitor C
S
is
connected across this resistor as indicated in Figure 13.11.

We will see later that the input impedance of the MOSFET is orders of magnitudes
larger than the corresponding value of the BJT. In particular, the MOSFETs input
impedance, R
in
, is much larger than the signal impedance R
SIG
. Now, as for the BJT
amplifier, we can define an attenuation factor for the MOSFET as:

SIG in
in
i
R R
R
+
= o

However, as normally R
in
>>R
SIG
then this factor can be approximated by 1 and we
will ignore the effect of the signal impedance on the voltage and current gains; we
will draw the arrow representing the input voltage across both the signal source and
R
SIG
to indicate this.


8
13.6.2 dc Bias Circuit

To set the correct DC conditions, e.g. find V
GS
and I
D
,we need to draw the dc bias
circuit which is obtained from Figure 13.11, by making all capacitors open-circuit.

Figure 13.12

In this circuit the source and drain currents are equal:

S D
I I = (13.13)

13.6.3 ac Small Signal Equivalent Circuit.

The derivation of the ac small signal equivalent circuit for midband frequencies for the
Common Source amplifier follows the same procedure as for the BJT Common Emitter
in Section (12.5.3.4). The dc voltage V
DD
is treated as ac ground and we assume
that capacitors C
1
, C
2
and C
s
are short circuits at mid-band frequencies. Hence after
finding the ac equivalents for the input and output circuits we come up with the
following circuit:

Figure 13.13
G
D
S
9

Note that at mid-band frequencies R
S
is shorted out by C
S
.

Putting in the ac model of the MOSFET, Figure 13.10, we arrive at the following ac
equivalent circuit for the NMOS amplifier:

Figure 13.14


We can further simplify the above circuit by combining in parallel R
1
// R
2
= R
in
and
r
ds
// R
D
// R
L
= R
out
:


Figure 13.15

Voltage Gain

Applying Kirchhoffs Laws:

At input :
gs in
v v = (13.14)

At output :
out gs m out
R v g v = (13.15)

Hence the voltage gain is given by

out m
gs
out gs m
in
out
V
R g
v
R v g
v
v
A = = = (13.16)
v
in
v
out
v
in
v
out
10
where R
out
= r
ds
// R
D
// R
L
(13.17)

Current Gain

We need to go to Figure 13.14 and combine R
1
and R
2
in parallel to form R
in
:
Figure 13.16


Take the input current as going through the source and the output current as going
through the load.

Now at the input :
in
in
in
R
v
i = (13.18)
and

L
out
out
R
v
i = (13.19)

Hence, from (13.18) and (13.19) the current gain is given by:

L
in
in
out
in
in
L
out
in
out
i
R
R
v
v
v
R
R
v
i
i
A . . = = = (13.20)

Using (13.16):

L
in
out m
L
in
v i
R
R
R g
R
R
A A = = (13.21)

Input Resistance

This is the resistance seen by the source looking in to the amplifier and is given by R
in

= R
1
// R
2
.

Output Resistance

This is the resistance seen at the output and is given by R
out
, Equation (13.17).

v
in
v
out
i
out
i
in
11
Worked Example

Figure 13.17

In the above circuit, the transistor is NMOS with K = 250 A V
-2
and threshold voltage
V
GS(th)
= 2V. The supply (drain) current is 1 mA and the voltage supply is V
DD
= 10 V.
The parameter in Equation (13.12) is 0.01 V
-1
and the voltage of the source with
respect to ground is 2 V. It is required that the output ac signal has the maximum
amplitude.

Assume zero signal resistance, R
SIG
= 0. The load resistance R
L
= 33 kO.

Compute appropriate values for the following:
R
s
, R
1
, R
2
, R
S
, R
D
, g
m,
ac voltage gain A
v
, ac current gain A
i
, input resistance R
in
and
output resistance R
out
.

Solution

Note that the bias circuit is given by















12


Figure 13.18

First we need to fix the drain voltage V
D
(see above) so that we gain maximum swing
of the ac signal at the output. This will be achieved if we obtain the maximum swing
of the total (dc+ac) drain voltage.

V
D
is the dc part of the drain voltage. On top of this dc component we are going to
superpose the ac voltage v
d
to form the total (dc+ac) voltage

v
D
= V
D
+ v
d
(13.22)

Now, the maximum value of v
D
is V
DD
which is 10V.

What about the minimum value of v
D
?

Note that from Equation (13.1b), the minimum allowed value of the total drain-source
voltage for the MOSFET to behave like an amplifier is:

) (
(min)
th GS GS DS
V V v = (13.23)

We have been given V
GS(th)
= 2V. We need to work out the dc value V
GS
.

We use the approximate relation (13.5):

2
) (
) (
th GS GS D
V V K I =

Putting in the given parameters for I
D
, K and V
GS(th)
:

2 6
) 2 ( 10 250 001 . 0 =

GS
V

Solving for V
GS
:

G
D
S
V
D
V
S
= 2V
A
B
V
G
V
GS
13
V
GS
= 4 V (13.24)

which is larger than V
GS(th)
so we are OK here.

Hence in (13.23):

v
DS
(min) = 4 2 = 2V

Hence the minimum value of the drain voltage (dc+ac) is given by

S DS D
V v v + = (min) (min) = 2 + 2 = 4V

Hence to avoid clipping : 10 4 < <
D
v .

To obtain maximum swing at output we fix the dc value of the drain voltage to be in
the middle of this range namely:

7 =
D
V V

To determine the Gate Voltage, V
G
,note that

S GS G
V V V + =

Hence from (13.24)

V
G
= 4+2 = 6V

Having found V
G
we can choose values for R
1
and R
2
in the potential divider from

DD G
V
R R
R
V .
2 1
1
+
=

Now there is no unique choice for R
1
and R
2
. As there is a negligible amount of
current entering the gate compared with base current for BJT, the transistor does not
load these two resistances. It is desirable to choose large values of these resistances
because it is usually desirable for an amplifier to have a large an input resistance as
possible so as to draw as little current as possible from the previous stage.

Hence possible choices for R
1
and R
2
are R
1
= 6 MO and R
2
= 4 MO.

We can now determine R
D
by applying Kirchhoffs Law between A and D:

V
DD
- I
D
R
D
= V
D


Hence
D
D DD
D
I
V V
R

= (13.25)

We have calculated V
D
to be 7V and have been given that V
DD
= 10V and I
D
= 10
-3
A

14
Hence 3
10
7 10
3
=

=

D
R kO (13.26)
To determine source resistance R
S
we note from (13.13) that the source and drain
currents are equal so that

V
S
= I
S
R
S
= I
D
R
S
(13.27)

Hence 2
001 . 0
2
= = =
D
S
S
I
V
R kO (13.28)

We have now determined the dc parameters. Now we must go the midband ac
equivalent circuit to determine the other parameters such as gain and input/output
resistances:


Figure 13.19

The transconductance g
m
and the ac drain source resistance r
ds
are determined by the
dc conditions through (13.7) and (13.12):

) ( 2
) (th GS GS m
V V K g = (13.29)

and

D
ds
I
r

1
= (13.30)

In Equation (13.29) putting in given and calculated values:

= =

) 2 4 ( 10 250 2
6
m
g 0.001 S (13.31)

and in Equation (13.30):

100
001 . 0 01 . 0
1
=

=
ds
r kO (13.32)

Hence from (13.17):

15
R
OUT
= 100kO // 3 kO //33 kO = 2676 O

Hence in (13.16): A
v
= -0.001 x 2676 = -2.676 (13.33)

R
IN
= 4 MO // 6 MO = 2.4 MO

Hence in (13.21): 6 . 194
10 33
10 4 . 2
2676 001 . 0
3
6
=

= =
L
in
out m i
R
R
R g A

Note: for an ideal load that is open circuit R
OUT
= r
ds
// R
D
=
913 . 2
10 103
3000 10 100
3
3
=

kO.

Hence in (13.16) : A
v
= -0.001x 2913 = -2.913 (13.34)

Comparing (13.33) and (13.34) the load has the effect of reducing the voltage gain
by over 8% from its ideal value when R
L
= .

13.7 Frequency Response of MOSFET Amplifiers

The above analysis has assumed that the isolation capacitors C
1
and C
2
and the by-
pass capacitor C
S
are short circuits. At low frequencies, these capacitors have non-
zero impedances and the gain decreases in frequency in a similar way to the BJT.

At high frequencies, the capacitances C
1
, C
2
and C
S
behave like short circuits, as they
do at mid-band frequencies, so do not affect the frequency response. However
intrinsic capacitances of the MOSFET and stray capacitances from the wiring do affect
the high frequency response and it turns out that these capacitances cause a low-
pass effect at high frequencies. Hence, like the BJT amplifier, the overall frequency
response is bandpass as illustrated in Figure 12.31.

13.8 Other MOSFET amplifier configurations

There are other MOSFET amplifier configurations, Common Gate (where the gate is
grounded) analogous to Common Base in BJTs) and Common Drain (where the drain
is grounded) analogous to Common Collector.

The MOSFET amplifier configurations have similar properties to the BJT counterparts,
for example Common Drain amplifiers have a voltage gain just less than 1 (similar to
Common Collector), so these amplifiers are sometimes called Source Followers; in
addition, these amplifiers have a large input impedance and a small output
impedance.


13.8 Comparison of BJT and MOSFET/JFET Amplifiers

Both types of amplifier are in widespread use. MOSFETs tend to be used at lower
frequencies with BJTs at higher frequencies. Comparing the FETs, then MOSFETs
have larger intrinsic noise than JFETs. MOSFETs also have a lot of intrinsic noise
compared with BJTs.

16
The voltage gain of a BJT Common Emitter amplifier (neglecting source resistance)
was found to be

t t
| |
r
R
r i
R i
v
v
A
LC
b
LC b
in
out
BJT
v
= = = (13.35)

where R
LC
is the resistance of the collector and load resistors in parallel.

Now the transconductance of a BJT is defined by

t
|
r
g
BJT
m
= (13.36)

Hence for a BJT CE amplifier, the voltage gain is given by

LC
BJT
m
BJT
v
R g A = (13.37)

From Equation (13.16), the voltage gain for a MOSFET Common Source amplifier is
given by

out
MOSFET
m
MOSFET
V
R g A = (13.38)

Now in general, g
m
BJT
>> g
m
MOSFET
hence BJT amplifiers tend to have a larger voltage
gain than FET amplifiers.

However FETs have larger input impedances this coupled with the lower power
consumption of FETS has led to CMOS technology (NMOS used with PMOS) being
used in integrated circuits such as logic gates (see Section 5.4).

MOSFETs are currently cheaper than BJTs to manufacture; however about half of all
instrumentation amplifiers use BJTs so this type of technology is still used.

Some examples from Texas Instruments web site:

INA116 Instrumentation Amplifier:

http://focus.ti.com/lit/ds/symlink/ina116.pdf

based on FETs

The INA118 is based on BJT technology:

http://focus.ti.com/lit/ds/symlink/ina118.pdf


Acknowledgements
I am grateful to Dr Ian Harrison and Dr Barrie Hayes-Gill for their advice on this
section.


17
17 THE MOSFET

17.1 Introduction

We have already seen how the MOSFET can be used in logic gates, memory and
amplifiers.

In this final section, we look at the structure of the MOSFET and explain how one can
control the current using an input voltage.

17.2 n-Channel Enhancement MOSFET Structure

We will concentrate on the n-Channel Enhancement MOSFET (NMOS) as this is the
most widely used FET. A simplified form of the structure is shown in Figure 17.1

Figure 17.1

The Gate is separated from the substrate by an insulating Silicon Dioxide layer. The
substrate consists of p-type silicon with heavily doped n-regions for the Source and
Drain. The Gate conductor (shown in black) is heavily doped polysilicon.

17.3 Principle of Operation

17.3.1 Linear Region

Suppose that a positive voltage, V
G
, is applied to the Gate and a voltage V
S
is applied
to the Source as shown in Figure 17.2:



Substrate
18

Figure 17.2

Suppose that V
G
> V
S
and let V
GS
= V
G
V
S
be the overall potential applied to the
Gate as shown above.

Conduction electrons (n-type carriers) are attracted to the positive potential of the
Gate and p-type carriers in the substrate are repelled away from the positive Gate.

If V
GS
exceeds a certain potential V
GS(th)
then there are more n-carriers than p-carriers
underneath the Gate and a there is a continuous conduction channel, consisting of n-
carriers, between the Source and Drain as illustrated in Figure 17.2. This layer is
referred to as an inversion layer as the effect of the Gate is to change the channel
from being p-type to n-type.

If one now applies a potential, V
D
, to the Drain such that V
D
> V
S
then a current will
flow in the n-channel; conduction electrons will flow to the right and a current will
flow to the left.

The higher V
GS
V
GS(th)
then the more n-type carriers that are present in the
continuous n-channel in Figure 17.2 hence the larger the conductance of the channel
(or lower the resistance).

To determine this relation, recall that resistance is related to resistivity by
A
L
R = (17.1)
Inverting this:

L
A
o = E (17.2)

V
G
V
S
V
D
+
19
where
R
1
= E is the conductance and

o
1
= is the conductivity.

Hence from (17.2) we can say that

o E (17.3)

Now from Equation (14.32):

n
nq o = (17.4)

where n is the number of charge carriers per unit volume and
n
is the mobility.

In Equation (17.4), nq represents the charge per unit volume so we can write:

Q o (17.5)

where Q = nq is the charge per unit volume.

Combining (17.3) and (17.5), we can say that the conductance is proportional to the
total charge per unit volume:

Q E (17.6)

Now Q is determined by how large V
GS
is above the threshold V
GS(th)
which is V
GS

V
GS(th)
. To see this, note that in Figure 17.2, the Gate is a conductor, the oxide is an
insulator and the n-channel is a conductor (for V
GS
> V
GS(th)
) . Hence together these
three components can be thought of as a capacitor:



Figure 17.3

Equal but opposite charge accumulates on the Gate and n-channel.

For a capacitor, the charge per unit volume is proportional to how much the Gate-
Source potential is above the threshold potential by:

( )
) (th GS GS
V V C Q = (17.7)

where C is the capacitance per unit volume. Note that if V
GS
< V
GS(th)
then Q is
effectively zero.

Combining (17.6) and (17.7) we can write:

V
GS
-V
GS(th)
20
) (th GS GS
V V E

or

( )
) (
'
th GS GS
V V K = E (17.8)

where K is a constant of proportionality.

What Equation (17.8) is saying is that the higher V
GS
is with respect to the threshold
voltage V
GS(th)
then the more negative carriers are attracted to the n-layer and the
higher the conductivity of the n-layer.

Now apply a small voltage V
DS
between Drain and Source as shown in Figure 17.2.
The n-channel is a conductor so, using Ohms Law, we can write for the current in this
channel, I
D
:

R
V
I
DS
D
= (17.9)

where R is the resistance of the n-channel.

Now resistance is related to conductance by

E
=
1
R (17.10)
Substituting for R from (17.10) into (17.9):

DS D
V I E = (17.11)

Substituting for E from (17.8) into (17.10):

DS th GS GS D
V V V K I ). ( '
) (
= (17.12)

which is our final result.

When Equation (17.12) holds, the MOSFET is said to be in the Linear Region where
I
DS
varies linearly with V
DS
.

17.3.2 Triode Region

In the previous section, we assumed that V
DS
was small enough so that it did not
affect the charge distribution in the n-layer. However, as the drain source voltage,
V
DS
, increases, then the charge distribution in the n-layer will change significantly as
shown below:



21

Figure 17.4

The Gate-Channel voltage now varies as one goes from the Source to the Drain.
To see this as we go around the circuit in Figure 17.4 from A to D to C there is an
increase of potential of V
GS
. Hence the Gate-Channel potential difference is V
GS
at A.

As we go around the circuit from B to D to C there is an increase in potential of V
GS

V
DS
. Hence the Gate-Channel potential difference is V
GS
V
DS
at B.

Therefore the Gate-Channel Voltage V
GS
varies approximately linearly from V
GS
at A to
V
GS
V
DS
at B i.e. it decreases.

As the charge induced under the gate is proportional to the voltage, this means that
more n-carriers are induced under the Source than under the Drain with a linear
reduction of charge as we move from Source to Drain. This is illustrated by the
decrease in the depth of n-carriers in the substrate as we go from A to B.

How does I
D
vary with V
DS
in this case?

Well, first we need to work out the charge per unit volume in the n-channel. This is
approximated by first working out the average of the maximum and minimum
voltages over the n-channel:
| |
B A AVE
V V V + =
2
1
(17.13)

where V
A
is the voltage at A (with respect to Ground) and V
B
is the corresponding
voltage at B.

Now we have V
A
= V
GS
and V
B
= V
GS
V
DS
. Hence in (17.13):

V
S
V
G
V
D
A
B
V
DS
V
GS
C
D
22
| |
DS GS DS GS GS AVE
V V V V V V
2
1
2
1
= + = (17.14)

Now the charge per unit volume in the n-layer is proportional to how much V
AVE
is
above threshold V
GS(th)
:

|
.
|

\
|
=
) (
2
1
th GS DS GS
V V V C Q (17.15)

Combining (17.6) and (17.15) we can write that:

|
.
|

\
|
= E
) (
2
1
'
th GS DS GS
V V V K (17.16)

where K is the same as in (17.8). Substituting for E in (17.11) we arrive at the
following result for I
DS
:

DS th GS DS GS D
V V V V K I .
2
1
'
) (
|
.
|

\
|
= (17.17)


Because of the reduction of carriers in the n-layer, then I
D
increases more slowly with
V
DS
. This region is called the Triode Region and is shown below in Figure 17.5:

Figure 17.5 Copyright 2005 by Pearson Education, Inc.
Upper Saddle River, New Jersey 07458
All rights reserved.
Note that the Linear Region is regarded as part of the Triode Region in the limit V
DS

0.

23
17.3.3 Saturation Region

In Figure 17.4, the voltage just under the drain is given by:

DS GS B
V V V = (17.18)

If V
B
= V
GS(th)
which is threshold for formation of a conductive n-channel, then the
charge goes to zero at this point.

From (17.18), the condition for this to occur is:

) (th GS DS GS
V V V =

or
) (th GS GS DS
V V V = (17.19)

We then have a condition called pinch off illustrated below:


Figure 17.6

If we put V
DS
= V
GS
V
GS(th)
into (17.17): then we obtain the result:

( )
2
) (
2
'
th GS GS D
V V
K
I = (17.20a)


and I
DS
is independent of V
DS
. Now if we increase V
DS
above
) (th GS GS
V V then pinch off
becomes even more severe as shown below:
V
S
V
G
V
D
24


Figure 17.7

What has happened is that p-type carriers have now been attracted to the region of
length AL where
) (th GS DS GS
V V V < i.e. voltage in this region below the threshold for n-
type carriers to be attracted to the Gate.

In this case, there is no longer a conduction path between Source and Drain. In
particular, Equation (17.9) now no longer holds and the current now no longer
increases with V
DS
.

What now happens is that the charge in the n-layer is still formed as shown and it is
pulled across the gap length AL by the Electric Field between C and D. It can be
shown that the current I
DS
is now given by Equation (17.20a) and no longer increases
with V
DS
. The current has therefore saturated and this region is called the
Saturation Region. This region is illustrated in the variation of I
D
with V
DS
in Figure
17.5.
An alternative way of writing Equation (17.20a) is to define
2
' K
K = so that

( )
2
) (th GS GS D
V V K I = (17.20b)

which is the relation quoted in Equation (13.5).

Using K, from Equation (17.17) , the current in the triode region is given by

DS th GS DS GS D
V V V V K I .
2
1
2
) (
|
.
|

\
|
= (17.20c)

It can be shown that K is given by
V
S
V
G
V
D
AL
25
(

=
L
W C
K
ox n
2
'
(17.21)

where
n
is the electron mobility, C
ox

is the capacitance in Figure 17.3, W is the
channel width (dimension going into the paper in Figure 17.1) and L is the length of
the n-channel. For further details please refer to Spencer and Ghausi Sections 2.6.1
to 2.6.3.

17.3.4 Variation of I
D
with V
DS
for Changing V
GS


Saturation occurs when V
DS
has reached a limiting value V
DS
LIM
where

) (th GS GS
LIM
DS
V V V = (17.22)

This value of V
DS
separates the Triode and Saturation Regions. Hence if V
GS
is
increased, then from (17.22) V
DS
LIM
increases and Saturation occurs at a higher value
of V
DS
. Similarly if V
GS
is decreased, then from (17.22) V
DS
LIM
decreases and
Saturation occurs at a lower value of V
DS
. This change in boundary between Triode
and Saturation regions is illustrated below with the boundary plotted as a solid curve:


Figure 17.8


17.4 Input Impedance

The input impedance is that of the MOS Capacitor illustrated in Figure 17.3. The
oxide has high resistivity, so the resistance is effectively infinite. At low frequencies it
can be assumed that there is no input current to the gate in which case the source
V
DS
= V
GS
V
GS(th)
26
and drain currents are equal : I
S
= I
D
. At high frequencies the gate capacitance must
be considered where it can be shown that its effect is to make the FET amplifier gain
go to zero as the input frequency becomes larger (Section 13.6.5).