CSULB -- CECS 285 Chapter Eleven Fall 2010 -- R.W.

Allison

An interrupt is the occurrence of a condition an event - which interrupts normal program flow

Interrupts allow a system to respond to asynchronous events (not in program flow) and handle the events while another task is running An interrupt driven system gives the illusion of doing many things simultaneously (multitasking on one CPU) The routine that deals with a specific interrupt is called an Interrupt Service Routine (ISR) or an interrupt handler Interrupts routines are activated by the occurrence of either an external or an internal event (a.k.a. exceptions) Interrupt routines are said to run in the background while the main system program runs in the foreground

CSULB -- CECS 285 Chapter Eleven Fall 2010 -- R.W. Allison

Interrupts allow the 8051 to respond to asynchronous events (external or internal) only when required.
o

The alternative is called polling testing status bits - which can be time consuming, wasting precious CPU resources/cycles

Interrupts introduce the concept of priority where one interrupt is given preference over another simultaneous interrupt Interrupt Vectors--where is the address of the ISR when a particular interrupt occurs? only when interrupts are enabled
8051 Interrupt Vector Table
Interrupt
Reset INT0 TF0 INT1 TF1 RI/TI TF2/EXF2

(Atmel 89C51RD2 has 3 more not covered)

Pin Flag Clearing
Auto P3.2 Auto Auto P3.3 Auto Auto Programmer Programmer

Vector Address
0000H 0003H 000BH 0013H 001BH 0023H 002Bh

Number Bytes
3 8 8 8 8 8 3

Comment
Power-on External Hardware Timer 0 External Hardware Timer 1 Serial Communication Timer 2

Each has 2 possible reasons for interrupt

CSULB -- CECS 285 Chapter Eleven Fall 2010 -- R.W. Allison 3

When an interrupt is activated the 8051

Finishes the instruction currently being executed Saves the current status of all the interrupts and stores the current PC Stack Vectors (i.e. jumps) to the corresponding location within the interrupt vector table, i.e. PC Vector Table address
Option 1: If the ISR fits in the available space you can immediately service the interrupt Option 2: If the ISR is too large then the vector table contains a long jump (ljmp) to the Interrupt Service Routing (ISR) The last instruction of the ISR is a reti (Return from Interrupt) Responsibility of ISR to save/restore any registers that it uses, including the PSW, having the same number of pushes and pops to/from the stack for the reti instruction to work correctly

Original PC is popped off the stack returning to where program was when the interrupt occurred

CSULB -- CECS 285 Chapter Eleven Fall 2010 -- R.W. Allison

All interrupts are disabled (masked) at system reset Software enables those interrupts required
IE (A8h) Interrupt Enable SFR is used to enable/disable interrupts
7 6 5 4 3 2 1 0

EA
EA IE.7

--

ET2

ES

ET1

EX1

ET0

EX0

ET2 ES ET1 IE.3 EX1 IE.2 ET0 IE.1 EX0 IE.0

IE.6 IE.5 IE.4

Global enable. If EA = 0, no interrupt is acknowledged. If EA = 1, each interrupt source is individually enabled or disabled by setting or clearing its enable bit Not implemented. Dont set. Enables/disables Timer 2 TF2 or EXF2 interrupt (8052) Enables/disables Serial Port RI or TI interrupt Enables/disables Timer 1 overflow interrupt Enables/disables External interrupt 1 Enables/disables Timer 0 overflow interrupt Enables/disables External interrupt 0

CSULB -- CECS 285 Chapter Eleven Fall 2010 -- R.W. Allison

Each interrupt source is individually programmed as being a high or low priority interrupt
Prioritized allows resolution of simultaneous interrupts Prioritized interrupts allow for preemptive interrupt handlers IP (B8h) Interrupt Priority SFR Priority is either high (1) or low (0) If an ISR is active and a higher priority interrupt occurs, it is interrupted (i.e. preempted). A high level ISR can not be interrupted.
--PT2 IP.7 IP.6 IP.5 Undefined Undefined Priority for Timer 2 interrupt

PS
PT1 PX1 PT0 PX0

IP.4
IP.3 IP.2 IP.1 IP.0

Priority for serial port interrupt

Priority for Timer 1 interrupt Priority for external 1 interrupt Priority for Timer 0 interrupt Priority for external 0 interrupt

CSULB -- CECS 285 Chapter Eleven Fall 2010 -- R.W. Allison

Each interrupt source is individually programmed to one of four priority levels (00, 01, 10, 11) IPH (B7h) Interrupt Priority HIGH IPL (B8h) Interrupt Priority LOW
Priority from highest to lowest (3,2,1,0) If an ISR is active and a higher priority interrupt occurs, it is interrupted. A higher level ISR can not be interrupted. Equal priorities yield to polling sequence (cf. page 75, AT8951RD2 spec)
--PT2 PS PT1 PX1 PT0 PX0 IP (H/L). 7 IP (H/L). 6 IP (H/L). 5 IP (H/L). 4 IP (H/L). 3 IP (H/L). 2 IP (H/L). 1 IP (H/L). 0 Undefined PCA (Programmable Counter Array)

Priority for Timer 2 interrupt Priority for serial port interrupt Priority for Timer 1 interrupt Priority for external 1 interrupt Priority for Timer 0 interrupt Priority for external 0 interrupt

CSULB -- CECS 285 Chapter Eleven Fall 2010 -- R.W. Allison

;--Upon wake-up go to Main, jump over the Interrupt Vector Table ORG 0000h ljmp Main ;bypassing the Interrupt vector table ORG iret ORG cpl reti ORG reti ORG reti ORG reti ORG reti 0003h 000Bh P2.1 0013h 001Bh 0023h 001Bh ;--External INT0 Vector ; ISR stub ;--Actual Timer 0 ISR that will ; toggle P2.1 pin ; to generate a square wave ;--External INT1 Vector ; ISR stub ;--Timer 1 Vector ; ISR stub ;--Serial Port Vector ;--Timer 2 Vector Setup Timer 0 ; ISR stub Enable Interrupts ;after vector space ;Timer 0, mode 2 (auto-reload) ;TH0=A4H for -92 ;make P0 an input port ;IE = 10000010 enable Timer 0 ;Start Timer 0 ;get data from P0 ; and echo it to P1 ;stay in this loop until ; we are interrupted by TF0

Actual Timer0 ISR

Interrupt Vectors

;--Main program for execution ORG 0030H Main: mov TMOD, #02h mov TH0,#-92 mov P0, #0FFh mov IE,#82h setb TR0 Back: mov A,P0 mov P1,A sjmp Back END

StartTimer 0
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8051 has two external interrupts: INT0 and INT1

Tied to external pins: INT0 (P3.2), INT1 (P3.3) P3.2 and P3.3 are general purpose I/O pins until the respective Interrupt Enable bits are set (i.e. EX0 and EX1, respectively)

Activation of external interrupts

8051 external interrupts activated in one of two ways (1) Level-triggered of (2) edge-triggered TCON.0 (IT0) and TCON.2 (IT1) defines interrupt type
IT0/IT1 = 0 for level-triggered interrupts (default) IT0/IT1 = 1 for edge triggered interrupts
Vcc

7 TF1

5 TF0

4 TR0

3 IE1

2 IT1

1 IE0

0 IT0 Pull-up
8051 INT1

TR1

TCON (88h)
CSULB -- CECS 285 Chapter Eleven Fall 2010 -- R.W. Allison

Level-triggered interrupts
INT0/INT1 held normally HIGH. A LOW level on one of these signals will trigger the respective interrupt The 8051 keeps sampling INTn for a LOW once each machine cycle
Some 8051s specify that the pin must be held in a LOW state until the start of the execution of the ISR. If the INTn pin is brought back to a HIGH before the start of the ISR, there will be no interrupt. Thus, to ensure activation of an external interrupt, it must remain LOW for at least 4 machine cycles

The LOW on the pin must be removed before the last instruction in the ISR (reti) is executed else another interrupt will occur

CSULB -- CECS 285 Chapter Eleven Fall 2010 -- R.W. Allison

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Edge-triggered interrupts
Setting IT1 or IT0 to 1 programs the 8051 to detect edge-triggered signals INT1/INT0 held normally HIGH. A HIGH-to-LOW transition on one of these signals will trigger the respective interrupt In edge-triggered interrupts, the INT1/INT0 signal must be held HIGH for at least one machine cycle, and then held LOW for at least one machine cycle to ensure that the transition is seen by the 8051 The 8051 automatically sets the respective External Interrupt Edge Flag (IE1/IE0) in the TCON register when using edge-trigerring Regarding the Interrupt Type bits (IT1/IT0) in the TCON register, the following two points must be emphasized:
Upon execution of a RETI instruction, the respective IEn bit will be cleared automatically, indicating the edge-triggered interrupt has been serviced While the ISR is being executed, the 8051 ignores all transitions on the external interrupt signals INT1/INT0

7 TF1

6 TR1

5 TF0

3 IE1

2 IT1

1 IE0

0 IT0 TCON (88h)

11

TR0

CSULB -- CECS 285 Chapter Eleven Fall 2010 -- R.W. Allison

External interrupt 1

Toggle an LED to indicate arrival of the interrupt (LOW) INT1 ISRs longer than 8 code bytes should implement a ljmp into normal code space Any other bugs?
ORG ljmp 0000h Main ;bypassing interrupt vector table

;--ISR for hardware interrupt INT1 to turn on LED ORG 0013H ;INT1 ISR 2 setb P1.3 ;turn on LED 2 mov R3,#255 ;load counter Back: 2 djnz R3,Back ;keep LED on for a while 2 clr P1.3 ;turn off the LED 1 reti ;return from ISR ;--MAIN program for initialization ORG 30h Main: mov IE,#10000100b ;enable external INT1 Here: sjmp Here ;forever loop END

9 bytes

The INT1 ISR is longer than 8 code bytes, hence it spills into the 8 bytes allocated for Timer1 ISR. Solution: place a ljmp INT1_ISR in vector table
CSULB -- CECS 285 Chapter Eleven Fall 2010 -- R.W. Allison 12

External interrupt 1 (ver. 2)

Fixing two bugs:

Original ISR was longer than 8 bytes (fix with ljmp) Original ISR didnt save/restore R3 (fix with push/pop)
ORG 0000h ljmp Main ;bypassing interrupt vector table ;--ISR for hardware interrupt INT1 to turn on LED ORG 0013H ;INT1 ISR ljmp Int1_ISR ; vector off to actual routine ;--MAIN program for initialization ORG 30h Main: mov IE,#10000100b ;enable external INT1 Here: sjmp Here ;forever loop Int1_ISR: push setb mov Back: djnz clr pop reti END
CSULB -- CECS 285 Chapter Eleven Fall 2010 -- R.W. Allison 13

03 P1.3 R3,#255 R3,Back P1.3 03

;save R3 ;turn on the LED ;load counter ;keep LED on for a while ;turn off the LED ;restore R3 and ; then return from ISR

TCON (88h)
Bit Symbol TCON.7 TF1 TCON.6 TR1 TCON.5 TF0 TCON.4 TR0 TCON.3 IE1 TCON.2 IT1 TCON.1 IE0 TCON.0 IT0 Comment T1 Overflow Flag T1 Run Control (1=ON, 0=OFF) T0 Overflow Flag T1 Run Control (1=ON, 0=OFF) EI1 edge flag. SET on H2L transition. Cleared by CPU I1 type control. 1=falling edge,0=low-level activated EI0 edge flag. SET on H2L transition. Cleared by CPU I0 type control. 1=falling edge,0=low-level activated

Edge-detect: the input must be held HIGH for one cycle and LOW for another. IE0/IE1 automatically cleared when CPU vectors to interrupt Level-activated: the input must be held until interrupt generated. Must also be de-activated before the ISR is completed. Usually the ISR acknowledges the interrupt and the interrupting device removes the interrupt request External Interrupts are sampled once each machine cycle so input should be held for at least 12 oscillator periods to ensure proper sampling

CSULB -- CECS 285 Chapter Eleven Fall 2010 -- R.W. Allison

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TI (Transmit Interrupt) is set when the last bit of framed data, the stop bit, is transmitted indicating that SBUF is empty and ready for another byte RI (Receive Interrupt) is set when an entire frame of data is correctly received indicating that SBUF now has a byte ready to be read Behavior of TI and RI is the same whether we are polling or using interrupts. Difference is how we detect and respond to its occurrence TI and RI are ORd to generate a single interrupt User must determine which is the source in the ISR Typical use relies on RI for data received but will poll TI to ensure data sent Analogous to receiving and generating a phone call Always clear TI or RI prior to execution of reti

CSULB -- CECS 285 Chapter Eleven Fall 2010 -- R.W. Allison

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Write a program to read data from P0 and echo it to P1continuously while giving a copy of it to the serial COM port to be transmitted out serially For setup purposes, assume XTAL = 11.0592 MHz with BAUD = 9600 Setup Code:
Main: mov P0, mov TMOD, mov TH1, mov SCON, mov IE, setb TR1 #0FFh #00100000b #0FDh #01010000b #10010000b ;Initialize P0 as 8 inputs ;Init Timer1 AUTO RELOAD (M2) ;Init Timer1 for 9600 BAUD ;Init UART 8-N-1; Rx Enabled ;Enable Serial Interrupt ;Start Timer 1

Positively: Excellence is in paying attention to details. Negatively: The devil is in the details. or, Whatever a man sows, that will he also reap.
CSULB -- CECS 285 Chapter Eleven Fall 2010 -- R.W. Allison 16

Setup code

Main:

Back:

ORG 0 ljmp Main ORG 23h ljmp Uart_ISR ORG 30h mov P0, #0FFh mov TMOD, #00100000b mov TH1, #0FDh mov SCON, #01000000b mov IE, #10010000b setb TR1 mov A, P0 mov P1, A mov SBUF, A sjmp Back ORG 100h jb TI, TX mov A, SBUF clr RI reti clr TI reti END

;VECTOR TABLE SETUP ;Reset to Main ;Vector off to the Serial ISR ;Start of Main code ;Initialize P0 as 8 inputs ;Init Timer1 AUTO RELOAD (M2) ;Init Timer1 for 9600 BAUD ;Init UART 8-N-1P; Rx Enabled ;Enable Serial Interrupts ;Start Timer 1 ;read Port0 ; and echo it to both Port1 ; and the serial I/F ;loop endlessly ;ISR for the Serial Port ;If TI then its a TX interrupt ;Else its RX so get char ; clear RI interrupt flag ; and leave ;It was a TX so clear TI flag ; and leave

Uart_ISR: Endless echo loop TX:

Serial ISR: was it TI or RI? Handle appropriately.

CSULB -- CECS 285 Chapter Eleven Fall 2010 -- R.W. Allison 17